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© 2015 Sarcina Technology LLC Sarcina Confidential & Proprietary
November 10, 2015
High Speed ASIC Packaging Trend: Integration, SKU, and 25G+
for MEPTEC and SEMI Symposium
Larry Zu Sarcina Technology LLC
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Package Performance Comparison
ASIC demands more package performance than mP
Source: Largest packages from 3 leading edge semiconductor companies in the world
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Application Microprocessor Network Processor ASIC Ethernet Switch ASIC
No. of Transistors 5.57 billion - 7 billion
Package Size 52.5mm x 51mm 52.5mm x 52.5mm 55mm x 55mm
No. of Cores 18 48 -
DDR4 2133 MT/s 2133 MT/s -
No. of Memory Channels 4 4 -
PCI Express Generation 3.0 x16 8 Gb/s x8 8 Gb/s -
SerDes None Multiple 10 Gb/s 128 ports at 25 Gb/s
SATA 3.0 None Multiple 6 Gb/s -
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ASIC Package Drives Packaging Technology
2
ASIC Package
Package Design
PCB Design
Model Extraction
Simulation Substrate
Fabrication
Assembly
Intellectual Property
25G+ SerDes
HDI, 25G+
All layer I/O
Channel with O/E
High Density IOs
IP Licensing
Warpage
Size, via stacking
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Multi-Die Integrated ASIC Packages
3
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Multi-Die Integrated ASIC Packages
4
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Large Package Warpage Issue Resolved
Allows package to be naturally relaxed and warped
Uses stencil with variable hole diameters in PCB assembly
US patent No. 20100143656 A1
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Stencil
Warped Substrate
PCB
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New Trend: Same-Die Multiple Packages
Time to market
Space constraint
Package cost reduction
Risk mitigation
Avoid high cost in Si tape out
Little engineering resources
Do it early at Silicon tape out
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25G+ SerDes Packaging Technology
7
Transmitter Pre-emphasis
Receiver Equalization
Automatic Adaptation
Impedance matching is still desired
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Bad Impedance Vs. Good Impedance
Impedance mismatch between package and PCB will
increase signal reflection from PCB with a higher return loss
reduce power transmitted to PCB
enlarge undershoot and overshoot
lower eye height
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Time (ps)
TD
R I
mpedance (W
) Bad Impedance Good Impedance
Ball
Bump Ball Bump
Mismatch
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Package Impedance Discontinuity and Enlargement Due to Reduced Rise Time
Same package design running at two different SerDes speeds
Impedance mismatch goes up as rise time is reduced
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Time (ps)
TD
R Im
pe
da
nce
(W
)
Rise-time=8 ps, 25-28 Gb/s
Rise-time=20 ps, 10 Gb/s
BGA
Ball C4
Bump
Via/
PTH
Trace
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25G+ Package Design Challenges: Vertical
At 25G+ vertical interconnection impedance mismatch No. 1 issue
Large capacitive coupling between SerDes and ground balls/planes
PTH differential impedance high
Irregular PTH and via design makes it harder to optimize
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Without
GND planes
With
GND planes
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Package Layer Stack Up & Material
Buildup dielectric layer: ABF-GX13, GX92, GXT-31, GZ41
Core layer: E700GR, E705G 11
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Package Information & Simulation Condition
14 (6-2-6) layer flip-chip BGA package
Organic substrate with 800 mm core & 1 mm ball pitch
25 Gb/s SerDes from C4 bump to BGA ball (including)
0-40 GHz model extraction with HFSS
8 ps rise time
25 Gb/s IBIS-AMI model
Simple TX and pure Rx with 100 W termination
PRBS-31 input pattern
Eye diagram captured at SerDes BGA ball
12
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Impedance Mismatch Reduced To <+10%
13
Time (ps)
TD
R Im
pe
da
nce
(W
)
Red. Typical 25G SerDes package design
Blue. Sarcina 25G+ package design technology
Ball
Bump
PTH/Via
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PKG Tx Eye Diagram Simulation Setup
14
PKG TX
RX
Probe Point (Rx output)
TX
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Package Tx Eye Diagram Improvement
15
Time (ps)
Vo
lta
ge
(V
) B
ER
5.7%
Eye
Width
Improvement
33.4 ps
Sarcina Invention for 25G SerDes
364 mV
Typical Design for 25G SerDes
31.6 ps
315 mV
15.5%
Eye
Height
Improvement
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PKG Tx Eye Diagram Simulation Setup
16
RX
Probe Point (Rx output)
TX PKG RX
PCB length = 20 mm
e=3.46, tan d= 0.002 100 W differential Zo
PKG TX
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Channel Eye Diagram Improvement
17
Time (ps)
Vo
lta
ge
(V
) B
ER
6.6%
Eye
Width
Improvement
18.7%
Eye
Height
Improvement
25.8 ps
Sarcina Invention for 25G SerDes
178 mV
Typical Design for 25G SerDes
24.2 ps
150 mV
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PAM4 Application
PAM4 cuts the PAM2 (NRZ) amplitude to 1/3
More demand to reduce PKG impedance discontinuity
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Summary
ASIC packaging started to be more challenging than microprocessor packaging
Multi-die package (MCM, SiP) is popular today
Same-die multiple packages are gaining acceptance
25Gbps NRZ (PAM2) SerDes and 56Gbps PAM4 SerDes demand packages with low impedance discontinuity
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