IE1204 Digital Design L7: Combinational circuits, Introduction ......IE1204 Digital Design L7:...

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IE1204 Digital Design

L7: Combinational circuits,Introduction to VHDL

Masoumeh (Azin) Ebrahimi (masebr@kth.se)

Elena Dubrova (dubrova@kth.se)KTH / ICT / ES

• BV 318-339, 60-65, 280-291,341-365

This lecture

IE1204 Digital Design, Autumn 2015 2

PLD (eg. PAL)

IE1204 Digital Design, Autumn 2015

Fan-in issue3

FPGA (eg. Cyclone II)

Typically 50000 logicelements

Technology : MUX tree4

Multiplexer (MUX)

• The multiplexer canselect which input youare going to connectto the output

• ”If S then X, else Y”1

Z = SX + SY

Multiplexer (MUX)

Z = SX + SY1

Multiplexer (MUX)

Z = SX + SY0

Implementation of functions usingMUXes

How can the following functionsbe implemented with a 2:1multiplexer?

• Z = B (INV)• Z = AB (AND)• Z = A + B (OR)• Z = A Å B (XOR)

Z = SX + SY

Quickie Question …

• How to connect the inputs of the MUX inorder to implement an inverter?

Inverter implemented with a MUX

Input x0

x0 0 1

Specification:if input = ’1’ then result <= ’0’;if input = ’0’ then result <= ’1’;

0 00 0 1

Z S X S Y

x x x NOT

= × + × =

Quickie Question …

• How to connect the inputs of the MUX inorder to implement an AND gate?

AND implemented with a MUX

• Specification:

0 00 1

01101 0 xxxxxYSSXZ ×=×+×=+=

• Specification:

0 00 1

01101 0 xxxxxYSSXZ ×=×+×=+=1

• Specification:

0 00 1

01101 0 xxxxxYSSXZ ×=×+×=+=0

OR implemented with a Mux

• Specification:

0 11 1

1 01 0 0 1

0 11 0 0

{ } ( )

Z x x x x x x

SX SY x x x x x

= + + =

= + = + + × =

= × + ×15

• Specification:

0 11 1

1 01 0 0 1

0 11 0 0

{ } ( )

Z x x x x x x

SX SY x x x x x

= + + =

= + = + + × =

= × + ×

• Specification:

0 11 1

1 01 0 0 1

0 11 0 0

{ } ( )

Z x x x x x x

SX SY x x x x x

= + + =

= + = + + × =

= × + ×

XOR implemented with a Mux

• Specification:

0 11 0

010101 xxxxxx

Å=×+×=

• Specification:

0 11 0

010101 xxxxxx

Å=×+×=

• Specification:

0 11 0

010101 xxxxxx

Å=×+×=

Hierarchy of MUXes

11100100

1 1 0 0

0 1 1 0

xyz 00 01 11 10

Implementation of larger functionswith MUXes

An (n + 1)-input function can be implemented with a MUX that has nselect inputs!

Choose any of the inputs as address inputs ...

... And minimize/implement function for each input.Draw new Karnaugh diagrams if necessary.

z 11100100

zyyxxzf ++=1

• Any Boolean function f (xn, ..., x1, x0) can be partitioned asf(xn, ..., x1, x0) = x0 f1(xn, ..., x1,1) + x0 f0(xn, ..., x1,0)

• The function can then be implemented with a multiplexer

Mapping into MUXes:Shannon decomposition (BV 6.1.2)

x0 123

• Any Boolean function f (xn, ..., x1, x0) can be partitioned asf(xn, ..., x1, x0) = x0 f (xn, ..., x1,1) + x0 f (xn, ..., x1,0)

• The function can then be implemented with a multiplexer

Mapping into MUXes:Shannon decomposition (BV 6.1.2)

x0 024

Mapping to MUXes:Shannon decomposition

• Any Boolean function f (xn, ..., x1, x0) can be decomposed(recursively) as

f(xn,...,x1,x0) = x0 f1(xn, ..., x1,1) + x0 f0(xn, ..., x1,0)= x1x0 f11(xn, ..., x2,1,1) + x1x0 f10(xn, ..., x2,1,0)+ x1x0 f01(xn, ..., x2,0,1) + x1x0 f00(xn, ..., x2,0,0)

• Right-hand side:– If x0 = 1 then the right term is zero. Then f is equal to the left term.– If x0 = 0, the left term is zero. Then f is equal to the right term.

• Left-hand side:– if x0 = 1, then f is equal to f (xn, ..., x1,1) (= left term on the right-hand side)– if x0 = 0 then f is equal to f (xn, ..., x1,0) (= right term in the right-hand side)

• Left-hand side = Right-hand side

)0,,...,()1,,...,(),,...,( 101001 xxfxxxfxxxxf nnn ×+×=

Right-hand sideLeft-hand side

Right termLeft term

Mux circuits

0 1 0 1

1 0 1 0

Address

AddressBut this is a memory

(ROM, RAM ...) Address pins

00 01 11 10

Look-up tables (LUT)

Two-input LUT

Programmablecell 1

A LUT with n inputs canrealize all combinationalfunctions with up to ninputs

Example: XOR gate

Two-input LUT

ProgrammedValues 1

1 1 01 0 10 1 10 0 0

• The simplest FPGA cell consists of a singletable (e.g. Look-Up-Table - LUT), a D flip-flop and a bypass MUX.

A simple FPGA cell

LUT D Q

ABCD M

D-flipflop will be explained soonin this course

One way to identify functions...

n inputs => 2(2n) possibledifferent Boolean functions

)(69960123 "0101100110100110"),,,( Hfxxxxf ==

The functions that are storedin a LUT are usuallynumbered after the numberthat is made up of the 1's inthe truth table / Karnaughmap.

Bit # 15 Bit # 0Bit # 1

LUT function number

69960123 "0101100110100110"),,,( fxxxxf ==

01236996 xxxxf ÅÅÅ=

With a LUT, all functions arerealized in the same way, so allof them have the same costOdd parity

• Mostly used as address decoders• Only one output is active when the

'enable' (En) signal is active• The active output is selected by a1a0

Decoder

En a1 a0 y0 y1 y2 y3

1 0 0 1 0 0 01 0 1 0 1 0 01 1 0 0 0 1 01 1 1 0 0 0 10 - - 0 0 0 0

y3y2y1y0

2-to-4 decoder

Demultiplexer

• The demultiplexer has basically the same functionas the decoder, but it is drawn differently

• The input I is connected to a selected output

I a1 a0 y0 y1 y2 y3

1 0 0 1 0 0 01 0 1 0 1 0 01 1 0 0 0 1 01 1 1 0 0 0 10 - - 0 0 0 0

y3y2y1y0

Read-Only Memory

0/1 0/1 ... 0/1

...am-1

Sel2m-1

dn-1 dn-2 …. d0

Programablebits

Three-statebuffers

Decoder

Encoders

• Encoder has the opposite function to adecoder, i.e. it translates 2N bit input into anN-bit code.– The information is greatly reduced

inputs

w2n 1-

noutputs

w0 w1 w2 w3 y1 y0

1 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1

Priority Encoder

• A Priority Encoder gives back the address of the input withthe lowest (or highest) indices that are set to 1 (or 0depending on what you are looking for)

• If all inputs are 0, the output z = 0, else z = 1

w0 w1 w2 w3 z y1 y0

1 - - - 1 0 00 1 - - 1 0 10 0 1 - 1 1 00 0 0 1 1 1 10 0 0 0 0 - -

The output is well-defined even ifseveral inputs areactive at the sametime.

Overview

y3y2y1y0

w3w2w1w0

Demultiplexer

Multiplexer

Decoder

Encoder

w3w2w1w0

noutputs

y3y2y1y0

ninputs

outputs

inputs

Equivalent

Z Used in priorityencoders

Code converters

• A code converter translates from one code toanother. Typical examples are:– Binary to BCD (Binary-Coded Decimal)– Binary to Gray code– 7-4-2-1 code– BCD to seven-segment decoder

abcdefg

A variant of the 7-4-2-1code is used today tostore the bar code

BCD-to-seven segment decoder

• BCD-to-7 segment decoder consists of 7 differentcombinatorial circuits, one for each segment

• To get optimal circuits, all 7 functions have to be minimizedsimultaneously so that common logic is shared

w0w1w2w3

Disadvantage of binary codes

· For safe data registration use Gray code· For data processing use binary code

Binary code, adjacent code words:1-2 double change3-4 triple change5-6 double change7-8 quadruple change!9-A double changeB-C quadruple change!D-E double changeF-0 quadruple change!

Can two bits change at exactly the same time?

• By changing the order of the codewords in abinary code, one construct codes in which nomore than one bit is changing at a time

• Such codes are called Gray codes

Gray code

0000, 0001, 0011, 0010, 0110, 0111, 0101, 01001100, 1101, 1111, 1110, 1010, 1011, 1001, 1000

Conversion between binary and Gray

Binary ® Gray:If Binary bit bn and bit bn-1 are different,the Gray code bit gn-1 is ”1", else ”0".

Gray ® Binary (most common transformation direction):If Binary bit bn and Gray code bit gn-1 are different theBinary bit bn-1 is ”1", else ”0".

Logic for Gray to Binary conversion

XOR-gate is ”1” if itsinputs are different! 4 bit code converter

Gray code to Binary code

Gray/Bin

Logic for Gray to Binary conversion

XOR-gate is ”1” if itsinputs are different! 4 bit code converter

Gray code to Binary code

Gray/Bin0 0 1 0

0 0 1 1

Introduction to VHDL

• VHDL is a language used to specify thehardware– HDL - VHSIC Hardware Description Language– VHSIC - Very High Speed Integrated Circuit– Used mostly in Europe

• Verilog is another language used to specifythe hardware– Used mostly in the United States

Why VHDL?

• VHDL is used to– verify that you have connected right by simulating the

circuit– describe the large structures in a simple way and then

generate the circuit by synthesis– allows for structured descriptions of a circuit

VHDL increases the level of abstraction!

• There are two types of VHDL code– VHDL for synthesis: The code is used as an

input to a synthesis tool which converts it intoan implementation (for example FPGA or ASIC)

– VHDL modeling and simulation code is used todescribe a system at an early stage. Since thecode can be simulated so you can checkwhether the intended functionality is correct

Types of VHDL code

Entity

ENTITY fulladder ISPORT( A,B,Cin : IN STD_LOGIC;

S,Cout : OUT STD_LOGIC);END fulladder;

The entity describes the ports to the outside of the circuit.The circuit as a block.

Architecture

ARCHITECTURE behave OF fulladder ISBEGIN

S <= A xor B xor Cin;Cout <= (A and B) or (A and Cin) or (B and Cin);

END behave;

Architecture describes the function inside the circuit.

Entity

• An entity describes a component's interface with theoutside world

• PORT-declaration indicates if it is an input or an output• An Entity is a symbol of a component.

ENTITY xor_gate ISPORT (x, y: IN BIT;

q: OUT BIT);END xor_gate;

yqxor_gate

Use English names for variable names in the code!

VHDL Basics

• PORT declaration establishes interface between thecomponent and the outside world

• A port declaration contains three things:– The name of the port– The direction of the port– Port's datatype

• Example: ENTITY test ISPORT ( name : direction data_type);

END test;

The most common data types

• Scalars (single-variable signals)– Bit ("0", "1")– Std_logic ('U', '0', ’1', 'X', 'Z', 'L', 'H', 'W', '-')– Integer– Real– Time

• Vectors (many-variable signals)– BIT_VECTOR - vector of bits– STD_LOGIC_VECTOR - vector of std_logic

Architecture

• An architecture describes the operation of a component• An entity can have many architectures, but only one can be

active at a time• An architecture corresponds to the component diagram or

behavior

ARCHITECTURE behavior OF xor_gate ISBEGIN

q <= a xor b after 5 ns;End behavior;

Code for Simulation

VHDL Example: 4/1 MUX

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY Multiplexer_41 IS

PORT(ce_n: IN std_logic; -- Chip Enable (active low)

data_in: IN std_logic_vector(3 DOWNTO 0);

sel: IN std_logic_vector(1 DOWNTO 0);

data_out: OUT std_logic); -- TriState Output

END ENTITY Multiplexer_41;

sel(1) sel(0)

data_out11100100

data_in(3)data_in(2)data_in(1)data_in(0)

VHDL Example: 4/1 MUX (cont.)

ARCHITECTURE RTL OF Multiplexer_41 IS

PROCESS(ce_n, data_in, sel)

IF ce_n = '1' THEN

data_out <= 'Z';

CASE sel is

WHEN "00"=> data_out <= data_in(0);

WHEN OTHERS => null;

END CASE;

END IF;

END PROCESS;

END ARCHITECTURE RTL;

sel(1) sel(0)

data_out11100100

data_in(3)data_in(2)data_in(1)data_in(0)

• The study material on synthesis shows anumber of VHDL constructs and theresulting hardware

• The following slides contain extra materialThe book gives many examples anddetailed explanations of VHDL

IE1204 Digital Design L7: Combinational circuits, Introduction ......IE1204 Digital Design L7:...

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