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IMEC IC-LINK ESCC COMPLIANT ASIC
MANUFACTURING AND QUALIFICATION
SERVICES
TOM RAMAN
Tom.Raman@imec.be
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© IMEC 2014
TOPICS
Imec, more than DARE
ASIC Supply Chain Flow
Test Success stories
Conclusions
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© IMEC 2014
IMEC, MORE THAN DARE
▸ Imec, more than the DARE library
▸ Imec is the one of the largest independent research
institutes worldwide
▸ The industrial arm of imec is branded imec IC-link
- Vision: to be an important actor in the delivery of Aerospace
silicon solutions to the European space industry
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IMEC, MORE THAN DARE
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IMEC, MORE THAN DARE
P62999-IM-14-PR01_03.10_ESCC_COMPLIANT_SERVICES DARE DAYS 2014
conce
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Pro
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Indust
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ion
time
Imec partners & subcontractors
Typical product development cycle
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IMEC, MORE THAN DARE
Imec IC-link offers besides the DARE library;
the following services▸ Wafer production
▸ Assembly according to chart F2, ESCC 9000
▸ Test development
▸ Screening according to chart F3, ESCC 9000
▸ Qualification according to chart F4, ESCC 9000
▸ Failure analysis
▸ Access to the imec IC-link network
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IMEC IC-LINK NETWORK
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TOPICS
Imec, more than DARE
ASIC Supply Chain Flow
Test Success stories
Conclusions
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ASIC SUPPLY CHAIN FLOW
Wafer foundry
•Dedicated mask-set
•MPW
Test house
•Wafer level test
•Wafer map generation
Assembly
•Package design
•According to chart F2
•Trace-ability with respect to wafer map
•SEM inspection
Final Test
•Test on packaged components
•Test over temperatures
Screening and Qualification
•Screening accto chart F3
•Qualification acc to chart F4
•Radiation test
Delivery to customer
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ASIC SUPPLY CHAIN FLOW –WAFER
FOUNDRY
Multi Project Wafer: Prototyping service▸ Prove the ASIC functionality
▸ Limited number of packaged samples (typical 40 pieces)
▸ Low cost
Flight Module production only with dedicated
mask-set▸ Dedicated mask-set
▸ Engineering run of 12 or 24 wafers
- Possibility to put wafers on hold for later mask-updates
▸ High NRE cost
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ASIC SUPPLY CHAIN FLOW
Wafer foundry
•Dedicated mask-set
•MPW
Test house
•Wafer level test
•Wafer map generation
Assembly
•Package design
•According to chart F2
•Trace-ability with respect to wafer map
•SEM inspection
Final Test
•Test on packaged components
•Test over temperatures
Screening and Qualification
•Screening accto chart F3
•Qualification acc to chart F4
•Radiation test
Delivery to customer
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WAFER PROBING
Purpose▸ Remove bad dies in early manufacturing stage
- Advantage Save packaging cost
- Failure due to functionality (electrical) or processing
Resources▸ Tester & test program
▸ Probe card
▸ Wafer prober (8” & 12” wafer probing capabilities)
Test flow▸ Wafer maps generated
▸ Bad dies Inked for identifications
▸ Good dies Sawing Packaging
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WAFER PROBING
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Probe needles
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WAFER PROBING
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ASIC SUPPLY CHAIN FLOW
Wafer foundry
•Dedicated mask-set
•MPW
Test house
•Wafer level test
•Wafer map generation
Assembly
•Package design
•According to chart F2
•Trace-ability with respect to wafer map
•SEM Inspection
Final Test
•Test on packaged components
•Test over temperatures
Screening and Qualification
•Screening accto chart F3
•Qualification acc to chart F4
•Radiation test
Delivery to customer
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ASSEMBLY SERVICES – PACKAGE
DESIGN
Flight modules need ceramic packages▸ Requirements are very strict (towards build-up,
material list etc…)
▸ Ceramic packages suitable for space are often “closed tools”
▸ Very expensive to customize dedicated packages
IC-link’s vision is to provide a set of “standard re-usable” space compliant package to the space community▸ Packages developed under ESA contract can be
offered as an “open tool” for other projects under ESA contract
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ASSEMBLY SERVICE - EXAMPLES
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8-layer CQFP 208
13-layer CQFP 256
4-layer CQFP 132
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ASIC SUPPLY CHAIN FLOW
Wafer foundry
•Dedicated mask-set
•MPW
Test house
•Wafer level test
•Wafer map generation
Assembly
•Package design
•According to chart F2
•Trace-ability with respect to wafer map
•SEM Inspection
Final Test
•Test on packaged samples
•Test over temperatures
Screening and Qualification
•Screening accto chart F3
•Qualification acc to chart F4
•Radiation test
Delivery to customer
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TESTING SERVICE
Test capabilities
Test hardware & test program development
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TESTING SERVICE – CAPABILITIES
▸ Many tester platforms available through partners to fit the needs for every application
- 1x Teradyne A565
- 2x Teradyne J750
- 1x Teradyne IntegraFlex
- 2x Teradyne MicroFlex
- 1x Teradyne UltraFlex
▸ Powerful Automated Test Equipment (ATE) available
Full family of portable tester systems (Hatinafamily)
Reliability tests▸ HTOL oven, capable of performing dynamic HTOL
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TESTING SERVICE – HATINA FAMILY
▸ Brand of Microtest developed portable testers
▸ Latest member of the family: DMT (Digital Mixed
Signal Tester)
▸ Fully configurable tester – suitable for radiation tests
– ATE testing as well as bench testing
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TESTING SERVICE - HATINA
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TESTING SERVICE
Test capabilities
Test hardware & test program development
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TEST DEVELOPMENT - HARDWARE
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TEST DEVELOPMENT - HARDWARE
Dedicated sockets, high quality POGO sockets
to guarantee signal integrity and minimize touch
on package pins
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TEST DEVELOPMENT –TEST
PROGRAM
▸ Characterization of the ASIC over samples
- Purpose: Deep understanding of all ASIC specs
- Histograms, statistical analysis, ...
▸ Production test program
- Purpose: Screen out production failures
- Flexibility to run the full program with a “push on the button”
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ASIC SUPPLY CHAIN FLOW
Wafer foundry
•Dedicated mask-set
•MPW
Test house
•Wafer level test
•Wafer map generation
Assembly
•Package design
•According to chart F2
•Trace-ability with respect to wafer map
•SEM Inspection
Final Test
•Test on load board
•Test over temperatures
Screening and qualification
•Screening accto Chart F3
•Qualification acc to Chart F4
•Radiation tests
Delivery to customer
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PROCUREMENT FLOW
Production control
Screening
Qualification
Generic flow for qualification testing of ESCC 9000 compliant parts
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• Wafer probing – full traceability
• Radiation tests with portable test system
• Dynamic power burn-in
• DUT at temperature
• Auxiliary components at room
temperature
• Dynamic HTOL (operating life test)
• DUT at temperature
• Auxiliary components at room
temperature
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PROCUREMENT FLOW – PBI/HTOL
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Bottom side,
External comp’s @RT
Top side
HTOL/Burn-in oven
ASIC is in functional
mode – patterns running
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RADIATION TESTING - SEEThermocouple
Signals to monitor
DUT
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RADIATION TESTING - SEE
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DMT
SEE DMT
load board
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RADIATION TESTING -TID
▸ In-situ testing with a production test program on
Hatina DMT for deep understanding of the ASIC
behavior under radiation
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TID load board,
10x devices
Dosimeters
Intermediate test
set-up, DMT
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ASIC SUPPLY CHAIN FLOW
Wafer foundry
•Dedicated mask-set
•MPW
Test house
•Wafer level test
•Wafer map generation
Assembly
•Package design
•According to chart F2
•Trace-ability with respect to wafer map
•SEM Inspection
Final Test
•Test on load board
•Test over temperatures
Screening and qualification
•Screening accto Chart F3
•Qualification acc to Chart F4
•Radiation tests
Delivery to customer
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© IMEC 2014
TOPICS
Imec, more than DARE
ASIC Supply Chain Flow
Test Success stories
Conclusions
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TEST SUCCESS STORIES
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ESA Qualified
to enter space
DROM Multicore
DSP
DPCG1
ADC & DAC
IP blocks
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© IMEC 2014
TOPICS
Imec, more than DARE
ASIC Supply Chain Flow
Test Success stories
Conclusions
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CONCLUSIONS
Imec IC-link ▸ is a specialized and tailored service provider
▸ capable of offering the services to design, produce and
qualify your ITAR-free ASIC, from prototype to flight
module
▸ Envisions to be a provider of custom “standard”
packages
▸ Delivers a state-of-the-art test solution through best-
in class subcontractors
▸ Aims to be an enabler of a European centered space
compliant supply chain
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QUESTIONS?
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CONTACT PERSONS
ASIC Design manager▸ Steven Redant: steven.redant@imec.be
ASIC volume production manager:▸ Danny Lambrichts: danny.lambrichts@imec.be
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