INTERNET OF THINGS: DRIVING TECHNOLOGY TRENDS ON … · internet of things: driving technology...

transcript

INTERNET OF THINGS: DRIVING TECHNOLOGY TRENDS ON SYSTEM SCALING ANDSEMICONDUCTOR MANUFACTURING EFFECTIVENESS

LODE LAUWERS

VICE PRESIDENT, PHD

BUSINESS DEVELOPMENT & SALES

MAY 2015

THE CONFAB 2015: Exploring the Edges of IoT and Mobile

Drones

Smart TextilesSmart Cars

Smart Homes Source: http://blogs.jabil.com/2014/08/13/internet-of-things-infographic/

Smart Watch

Smart Phones

Laptop

THE IOT PREMISE: EveryThing connected, managed, securedBillions of wirelessly interconnected devices will communicate intelligently

Smart Glasses

Source: Market Realist

#CONNECTED DEVICES: A MATTER OF MATH

Source: Bosch; IDC

KEY DRIVERS IN IOT ECOSYSTEM

Source: Bosch

IOT CHALLENGES: READINESS CHECKLIST

Source: TI

TECHNOLOGY CHALLENGES

IOT SYSTEM INNOVATION

NEW SYSTEMARCHITECTURE

NOVEL MEMORYTECHNOLOGY

SPECIALTYDEVICE

NEW APPLICATIONULP DRIVEN

System applications requirements

Performance1Top/s100Gop/s10 Gop/s10Mop/s

500 Watt

(mains level)

(battery level)

100mWatt

(battery level)

(ambient level)

1Pop/s

100 Watt

I/O bandwidth100Gbp/s1Gbp/s10 Mbp/s1Mbp/s 1Tbp/s

Off Chip

Memory

Performance: Operations per second (Ops)

Memory: # Bits

I/O bandwidth: Bits per second (bp/s)

Stationary

Mobile

Ambient

500 Watt

(mains level)

(battery level)

100mWatt

(battery level)

(ambient level)

1Pop/s

100 Watt

Off Chip

Memory

Memory: # Bits

Stationary

Mobile

Ambient

Increased Performance @ constant power density

Wired, heat dissipation constrained

Increased Performance @ constant leakage

Cost trade-off

Wireless, battery constrained

Ultra low power, cost trade-off

Wireless, energy scavengers

500 Watt

(mains level)

(battery level)

100mWatt

(battery level)

(ambient level)

1Pop/s

100 Watt

Off Chip

Memory

Memory: # Bits

More performance per Watt:

1. Technology: transistor improvement

2. Circuit: e.g. Near Threshold Computing (NTC)

3. Architecture: e.g. Multi-Core, Neuromorphic

13imec confidential

Imec Logic Device RoadmapDevice Technology Features

production

2013 - 2014 2015 - 2016 2017 - 2018 2019 - …

16 -14nm 10nm 7nm 5nm

Vdd (V) 0.8 0.8-0.7 0.7-0.5 0.7-0.5

Device FinFET (Bulk, SOI), FDSOI FinFET (Bulk, SOI) FinFET (GAA, QW, SOI) GAA lateral NW; (Vert. NW)

FinFet width (nm)

FinFET pitch (nm)

42-48nm

30-32nm

21-24nm

14-16nm

Gate Stack HKMG HKMG HKMG HKMG

CPP (nm) 64-80nm 50-64nm 32-42nm 22-32nm

Channel n/p Si / SiGe Si / SiGe (Ge>80%) Si / SiGe (Ge) Si / SiGe (IIIV / Ge)

S/D Strain N S/D Si:P

P S/D eSiGe (55%)

Low-k spacer

N S/D Si:P:C

P S/D eSiGe (>60%)

Low-k spacer

N S/D Si:P:C

P S/D eSiGe (>60%)

Low-k spacer

Lgate (nm) 20-25nm 15-20nm 10-15nm 10nm

Planar SOI Bulk FinFET SOI FinFET SiGe/Ge channel IIIV channel Lateral Nanowire Vertical Nanowire

Improve Electrostatics

Improve Performance

15 20 25 3010

Gate length (nm)

Tapered Fin

FinW=7-10nm

Straight Fin

FinW=7-8nmUltra-Thin Fin

FinW=5nm

Gate-All-Around Nanowire

Nanowire = 7nm

N22N14N10N7N5

FinFETs

(Vdd ~ 0.7-0.8V)

0.1 0.2 0.350

200Closed symbols: D

2 anneal

SiGe25% FinFET

SiGe25% GAA

Gate length (mm)

SiGe25%

Improve Device ElectrostaticsFrom finfets to lateral nanowires

Introduction of Gate-All-Around Nanowires to improve device electrostatics beyond N10

N14 FinFET

Gate-All-Around NW

Si1-xGex (x>0.7)

Si(100)HAADF STEM

Improve PerformanceHETEROGENEOUS CHANNELS: INTEGRATING GE AND IIIV ON SI

Defect Trapping

InGaAs

Ssat (mV/dec)

sGe QW FinFET

(STI last)

(300mm Fab 2013)

(0.5V)

State-of-the-art Si

FinFETs (0.8V)

TSMC Ge Bulk

FinFET (0.5V)

(IEDM 2013)

Ssat (mV/dec)

Nature2010

InAs-O-I

Lee, VLSI 2013

InAs channelIntel 2009

InGaAs planar

planar

InAs planar

(Chang,,TSMC)

IEDM 2013 (0.5V)

Sematech

InGaAs

IMEC-Lab InGaAs planar

(0.5V)

IMEC-300mm

InGaAs FinFET

(0.5V)

State of Art Si

FinFETs (0.8V)

IMEC-300mm InGaAs

GAA (0.5V)

16imec confidential

Imec logic BEOL roadmapImprove RC parasitics and electro-migration

production

2013 - 2014 2015 - 2016 2017 - 2018 2019 - …

16 -14nm 10nm 7nm 5nm

Contact Self-aligned, adv. Contact

beyond Ni

Self-aligned, adv. Contact

beyond Ni

Contact pitch (nm) 64-80nm 50-64nm 32-42nm 22-32nm

Low k 2.5 – 2.4 2.5 – 2.3 (air gaps 1.3x) 2.4 – 2.1 (air gaps 1.3x) 2.4 – 1.9 (air gaps 1.3x)

Metallization PVD TaN/Ta

PVD RF CuMn

ECD Cu

PVD TaN

CVD Co or Ru

PVD Cu + ECD Cu

CVD Mn(N)

CVD Ru or Co

ECD seed + ECD Cu ELD/CVD Cu; (Cu alternative)

Metal pitch (nm) 56-64nm 40-45nm 28-32nm 20-22nm

e-Memory (um2) SRAM 0.08-0.07 SRAM 0.06-0.05 SRAM < 0.05 SRAM < 0.05; (STT-RAM)

Lower Resistance

Lower Capacitance

Advanced Cu / low k engineering

Contact

• Significantly improved contact

resistivity with Ti direct or MIS

contact on Si-high P with laser anneal

• Demonstrated k=2.2 integrated;

improved yield with UV treatment post

deposition

Metallization

D02 D03 D04 D05 POR50

W = 23nm

• Liner/barrier optimization, able to

fill 22nm half pitch trench with good

contact resistance

N10 metallization schemes benchmark

N10 via chains metallized

Local Interconnect +

Trench Contact

Fin S/D Epi

PATTERNING CHALLENGESEUV

193i Multi patterning EUV lithography DSA

N7 Fin

SAQP 11nm

Cut litho

Core 2 etch

Spacer 2 + Core 2

removal

Core 1 + spacer 1

Spacer 2 transfer

Fin Etch

Advanced patterning readiness

▸ N10 BEOl LE^3 process (P=45nm)

▸ N7 SAQP Process (FP=22nm))

▸ M1 design flow for N7 (M1H+M1V)

▸ Various alternative resist materials

under evaluation

▸ N10 BEOl SE EUV NXE3300 process

(P=45nm)

▸ EUV pellicle development: membrane

materials, primary mounting options,

lifetime testing of integrated pellicle

solutions

~24 defects /cm2

2.5 hr anneal

(Oct “14)

▸ Defect reducton from >200 to 24/cm2

Post-trim 45nm hp Post-DSA 15nm hp

▸ 9x pattern frequency multiplication for

holes resulting in post-DSA 15nm hp

▸ Surface conditioning leading to better

placement accuracy

lution

InAs Nano wire

on <111> Si

LOGIC BEYOND 10nm FINFETVERTICAL NANOWIRES, 2DMATERIALS.... THE NEXT SWITCH?

FINDING THE NEXT SWITCH

Graphene Logic

Ultimate

NAND2 Benchmark: Praveen Raghavan

(Imec)

After Nikonov & Young (Intel 2012)

InAs TFET

All Spin Logic

MTJ Logic

Spin Wave

CMOSFET continues to be

more efficient with scaling

Spin wave devices: no transport of

electric charge, low energy and power,

potentially slow (low wave velocity)

10-1 100 101 102 103 104

Delay, ps

Tunnel FET allows for Ultra Low Power (at cost of performance?)

Spin Wave Computing adds functionality to or could replace existing CMOS technologies

CMOS circuit

25 transistors

> 100 interconnect vias

Waveguide

Transducer

I = Input

O = Output

CI/CO = Carry

in/out

Wave computing circuit

5 transducers, 4 wave-guides

and 5 vias

Process integration : 3D stacking on CMOS

CMOS level

Example: 1-bit full adder in CMOS and wave computing technology

Power / Performance comparison

• Circuit simplification leads to smaller circuits despite larger CD

• Simplified process integration

• IMEC benchmarking indicates about 100× lower power for large arithmetic circuits

500 Watt

(mains level)

(battery level)

100mWatt

(battery level)

(ambient level)

1Pop/s

100 Watt

40nm imec SOC chip reduced Vdd, T. Gemmeke, DATE 2015

Actual scaling due

to variability

Ideal scaling ≈ VDD2

Scaling down to FinFET:

Improved electrostatics allows better

low Vdd operation

The potential gain of Near Threshold Operation

500 Watt

(mains level)

(battery level)

100mWatt

(battery level)

(ambient level)

1Pop/s

100 Watt

Off Chip

Memory

Memory: # Bits

More data per Watt:

1. Technology: memory improvement

2. System: e.g. more on chip memory (reduce off-chip BW)

Capacity

On Chip

Working memory

Mass storage

Need for new memory technologiesExisting technologies challenged beyond 18nm

MEMORY: BEYOND 20nm

STT MRAM

DRAM replacement beyond 20nm

Non-volatile memory for

both embedded and stand-alone

applications

<20 nm

STT RAM

Re RAM

Flash replacement beyond 10nm

Non-volatile memory

High speed, low energy, superior scalability, CMOS

compatible

3D SONOS

Flash replacement to 10nm

Non-volatile memory

Memory cells implemented in vertical

plugs consisting of 8,16,32 ... stacks

SRAM DRAM HDD

NANDNOR

Emerging Memory Benchmarking

STT-MRAM has the best combination of speed/endurance for SRAM/DRAM replacement.

RRAM has potential for e-NVM and IOT devices in cost tradeoff

Likely industry memory roadmap

2014 2015 20172012 2019 2021

RRAM, STT, PCM?

Planar FG

4Gb 8Gb 16Gb

DRAM DRAM: MIMCAP scaling with high-k optimization

STT-MRAM

Planar FG

64Gb 128Gb 256Gb 512Gb 1Tb

FLASHConventional wrap Floating Gate

Planar Floating Gate

3D NAND

STORAGE

MEMORY

RRAM/CBRAM / PCM

STT-MRAM

SRAMeSTT-RAM

3D NAND

Samsung

20nm FG

Micron

16Gb CBRAM

ISSCC 2014

Increasing need for non-

volatile embedded

low-voltage

memories

(reduces off-chip

Path to ultra-low

standby power

systems.

E-NVM:

2B$ by 2018

Automotive, smart cards,

New apps,

IOT device...

3D & OPTICAL IO

Optical IO: extension of 3D stacking

Further performance boosting, extreme high-bandwidth

Optical interconnects using silicon photonics instead of electrical interconnects

Fabrication of optical components by using CMOS processing techniques and equipment

Need for best-in-class optical components

3D STACKINGMEMORY / LOGIC / 3D ENABLED SCALABLE I/O

Multi-die Memory stack

- Combined with logic I/O circuit

DRAM Logic DRAM Logic I/O

High performance devices: 3D integration using a Si Interposer

Wide I/O memory on SOC logic

3D-SIC 3D-SOC 3D-IC

Wiring level Global Semi-global Intermediate Local FEOL

2-tier

Multi-tier FEOL

TSV Pitch 10 7 5 µm 10 7 5 µm “ TSV” after stack “TSV” after stack No TSV

Contact Pitch:

Rel. density:µbump pitch:

4020105µm

1 41664

Cu TSV –Cu pad:

10 7 5

16 33 64

5 1 µm

64 1600

2 µm 0.5 µm

800 6400

200 100 nm

4 104 1.6 105

< 100 nm

> 1.6 105

Stacking

Method

D2D, D2W

Stacked die

B2F / F2F

W2W (D2W)

Contact at bond

interface

Contact after stacking

Si layer-to-wafer

stacking

2nd Tier Device fab.

after stacking

Monolithic

Device-level stacking

3D Technology Landscape

2nd FEOL

after stacking

(Overlay 2nd tier defined by litho scanner

alignment)

(Overlay 2nd tier defined by W2W

alignment/bonding)

• Via middle: successful integration

3x50um via middle TSV using WN

barrier / ELD NiB seed and ECD Cu

fill, resulting in champion reliability

• Via last on carrier: successful 5x50

&10x50um integration

• Via last on bonded Si wafers: 2x20um

TSV demonstrated

3D Advanced process integration

TSV Scaling

Via middle Via last

Micro-bump and stacking

• ubump scalability towards 10um pitch

using ELD coating

• Cu-Cu bonding using ELD Au to

enable Sn wetting

• Oxide-oxide bonding with bond

strength >1.5mJ/m2, W2W overlay

Thermo-mechanical impact

• Electrical: Estimation impact TSV and

ubump stacking on N7 devices.

• Micro-bump mechanical strain impact

on high mobility channel devices

Optical I/O: system scaling projection

Package I

CMOS tech node 20-28nm 14nm 10nm 7nm 5nm

I/O Bandwidth 2.5Tbps 5Tbps 10Tbps 25Tbps 50Tbps

I/O Energy 10pJ/bit 5pJ/bit 1-2pJ/bit 0.1-1pJ/bit 50-500fJ/bit

Channel Rate up to 35Gb/s up to 50Gb/s up to 70Gb/s up to 100Gb/s up to 140Gb/s

Cost Target $$$$/Tbps $$$/Tbps $$$/Tbps $$/Tbps $/Tbps

Optical I/O Distance

& Appl.

5m to 2km

Network

1m to 2km

Backplane

5cm to 2km

5mm to 2km

Interposer

1mm to 2km

Datacenter NetworkRack-to-rack:5m-500m+

Datacenter switch/router interconnect

Source: LightCounting Backplane/BoardPackage-to-package: 5cm-5m

Logic-to-DRAM, logic-to-logic, ...

Source: Intel

Chip/Interposer1mm-5cm, interposer interconnects

Logic-to-logic, logic-to-memory, ...

Source: nVidia

Increasing system requirements for I/O drive

Optical interconnects to ever shorter link distances

Optical I/O: Technology Roadmap

Package I

CMOS tech node 20-28nm 14nm 10nm 7nm 5nm

I/O Bandwidth 2.5Tbps 5Tbps 10Tbps 25Tbps 50Tbps

I/O Energy 10pJ/bit 5pJ/bit 1-2pJ/bit 0.1-1pJ/bit 50-500fJ/bit

Channel Rate up to 35Gb/s up to 50Gb/s up to 70Gb/s up to 100Gb/s up to 140Gb/s

Cost Target $$$$/Tbps $$$/Tbps $$$/Tbps $$/Tbps $/Tbps

Optical I/O Distance

& Appl.

5m to 2km

Network

1m to 2km

Backplane

5cm to 2km

5mm to 2km

Interposer

1mm to 2km

Optica

ptions

Packaging &

Assembly

Optical Module

on Board

Optical Module

on Package

Optical Module

on Interposer

Optical Interposer Wafer-bonded

Optical Layer

Lasers Flip-chip III-V die Flip-chip III-V die Flip-chip III-V die Flip-chip III-V die

Monolithic Ge or III-V

Flip-chip III-V die

Monolithic Ge or III-V

Modulators Si Mach-Zehnder Si Mach-Zehnder

Ge EAM

Si SL-MZ or Ring

Ge EAM

Si SL-MZ or Ring

Ge or III-V EAM

Graphene/BTO

Detectors Ge p-i-n PD Ge p-i-n PD Ge APD Ge APD or III-V

Graphene PD

Ge APD or III-V

WDM Multiplexing CWDM-4 CWDM-4

DWDM-8

CWDM-4

DWDM-16

CWDM-4

DWDM-32

CWDM-4

DWDM-64

Optical Channel SingleMode Fiber SingleMode Fiber SingleMode Fiber

MultiCore Fiber

Optical PCB

SingleMode Fiber

MultiCore Fiber

Optical PCB

SingleMode Fiber

MultiCore Fiber

Optical PCB

Optical

moduleLogic die

Optical

interposer

Optical PCB

Logic die

Optical PCB

Optical

layerLogic layer

Optical

moduleLogic die

Optical PCB

Optical

moduleLogic die

Stringent requirements for optical I/O (BW density, ernergy, cost) drives:

• Optical module integration closer to the host IC

• Development of a low-power, high density Silicon Photonics Technology

EMERGENCY & SECURITY SMART LIVING RETAIL & SHOPPING INTERACTIVE GAMING

ENVIRONMENTAL MONITORING AUTOMOTIVE SPORTS UTILITIES

AGRICULTURE CONSUMER ELECTRONICS HEALTHCARE CONSTRUCTION

SMART APPLICATIONS

SENSORMODULES

WIRELESSCONNECTIVITY

FLEX TECHNOLOGIES

imec develops solutions for the

MULTI GAS SENSOR AIR QUALITY MONITORING

ION SENSOR PLATFORM FOR FLUIDIC ANALYSISWATER QUALITY MONITORING

HYPERSPECTRAL IMAGINGUNIQUE SPECTRAL FINGERPRINT

HYPERSPECTRAL IMAGER LOW-POWER - PORTABLE - AFFORDABLE

AGRICULTURECAMERAS ON DRONES INSPECT FOOD ON THE FIELD

Image courtesy of Volt Robotics

RGB HYPERSPECTRAL

AGRICULTURECAMERAS ON DRONES INSPECT FOOD ON THE FIELD

automotivesmart mobility

FOOD QUALITYINSPECTION

MEDICAL GRADE CONSUMER DEVICESKIN CARE MONITORING

low-power radio for personal area networks

RECORD LOW POWER 5mW: 2X BETTER THAN OFF THE SHELFSTATE-OF-THE-ART PERFORMANCE: -95dBm SENSITIVITYMULTI-STANDARD

low-power radio for smart infrastructure

RECORD LOW POWER 4mW RX: 10X BETTER THAN OFF THE SHELFBEST IN CLASS PERFORMANCE: -120dBm SENSITIVITYMULTI-STANDARDHIGH LEVEL OF INTEGRATION

wifi for sensors smart buildings

LOWEST POWER: ACTIVE & DEEP SLEEP> 1KM DISTANCEPRE-STANDARD COMPLIANT SYSTEM: IEEE 802.11ah

SHORT DISTANCE - HIGH DATA RATEmm-WAVE : 60GHz PHASED ARRAY RADIO

AUTONOMOUS DRIVING & ACTIVE SAFETY79GHz RADIOS

THIN-FILM ELECTRONICSRFIDS - NFC TAGS - MEMORIES - ANTENNAS - DISPLAYS - SENSORS

SMART RFID TAGSBRAND AUTHENTICITY - ADVICE

SMART RFID TAGSAUTHENTICITY - CORRECT USE

HIGH-RESOLUTION FLEXIBLE DISPLAYSVERY THIN <25 MICRON - VERY FLEXIBLE - LOW COST

improved (chronic/acute) disease management

Bron foto: http://www.clemson.edu/glimpse/?p=1179

MEDICAL QUALITY DATA & SOLUTIONSIN EVERYONE’S REACH

empower people for disease prevention & healthier lifestyle

IMEC WEARABLE HEALTH AND LIFESTYLE MULTI-SENSOR PLATFORM

ULTRA-LOW POWER MULTI-SENSOR PLATFORMMEDICAL QUALITY DATA

ECG PATCH

ULTRA-LOW POWEREMBEDDED ARTEFACT REDUCTIONACTIVITY TRACKING & ENERGY EXPENDITURE

SAMSUNG DIGITAL HEALTH PLATFORMEMPOWERED BY IMEC MULTI-SENSOR PLATFORM

imec generic EEG development platform

BASED ON IMEC TECHNOLOGY

FROM PLATFORM TO PRODUCT FOR CLINICAL RESEARCH

nanoelectronics enable disruptive innovation in healthcare

CELL SORTING CHIPMILLIONS OF CELLS/MINUTE

SINGLE CELL ANALYSISPOWERFUL INSTRUMENTATION - LOW COST

DNA ANALYSISSPECIFIC MARKERS

RESPONSE TO DRUGSALLERGIESFOOD SENSITIVITYRISK TO DEVELOP CERTAIN DISEASE

TESTS TO GIVE BEST COMBINATION OF DRUGSCHEAP - FAST - POINT OF CARE

TOWARDS PERSONALIZED DRUGSAUTOMATED TESTING OF THOUSANDS OF CANDIDATE DRUGS ON CULTURED TISSUES

NEED FOR ENERGY EVERYWHERESAFETY - FAST CHARGING - LOW VOLUME & WEIGHT - RELIABLE

ENERGY STORAGE3D SOLID-STATE BATTERIES: HIGH POWER & HIGH SPEED & ENERGY DENSITY

imec global collaboration platform

LamRESEARCH

IMEC CORE CMOS PROGRAM:

BUILDING A ‘LAYERED ECOSYSTEM’...

.... OF WORLDWIDE PARTNERSHIPS

IMEC CORE CMOS PROGRAM:

BUILDING A ‘LAYERED ECOSYSTEM’...

SUPPLIER HUBNEUTRAL PLATFORM FOR EARLY AND STRONG INVOLVEMENT OF EQUIPMENT AND MATERIAL SUPPLIERS IN PROCESS DEVELOPMENT

Patterning center motivation

Increasing R&D challengesIncreasing R&D cost

Consolidating industry

Cost sharingRisk mitigation

Maximum leveraging of full eco-system

Increased supplier involvement & commitment

= Patterning Center

Increased critical mass on unit process developmentMost advanced equipment at affordable conditions

SUPPLIERS HUB

Increased supplier involvement & commitment

Increased critical mass on unit process development

Most advanced equipment at affordable conditions

MAXIMISED VALUE CHAIN LEVERAGING

Core partner fees are minimized through maximized leveraging of other key players in value chain:Imec has successfully attracted increased participation of leading edge fabless companiesImec is successfully engaging increased participation and commitment of leading edge equipment and material suppliers

FABexpansion

Fab3 project

SEPTEMBER 2015

NOVEMBER 2015

MARCH 2015

MAY 2015

SUMMARY

• The IoT information universe demands an increase for data / bandwidth / low power.

• Innovation is needed at device technology, circuit and architecture level to find solutions to

serve this wide spectrum of applications.

LOGIC BEYOND 5nm2D MATERIALS

INTERNET OF THINGS: DRIVING TECHNOLOGY TRENDS ON … · internet of things: driving technology...

Documents