Post on 28-Jul-2020
transcript
PUBLIC USE
JIM BRIDGWATER
SENIOR PRODUCT MANAGER
FTF-NET-N1865
MAY 17, 2016
FTF-NET-N1865
INTRODUCING THE QorIQ LS1012ATHE WORLD'S SMALLEST AND LOWEST POWER
64-BIT PROCESSOR
PUBLIC USE1 #NXPFTF PUBLIC USE1 #NXPFTF
AGENDA
• Introduction to the QorIQ LS1012A Architecture and
Schedule
• Identify Target Markets and Differentiating Features
• Describe NXP Enablement Plans
• Call to Action
PUBLIC USE2 #NXPFTF
LS1012A Block Diagram
• Single ARMv8 64-bit Cortex-A53 processor
˗ 1840 DMIPS / 2240 Coremark @ 800MHz
˗ NEON Co-processor and DP FPU
˗ 256 KB L2 cache with ECC
• Memory Controller
˗ DDR3L up to 1000 MHz
˗ 16-bit data bus, 1 chip select
• High Speed Interconnect
˗ 1x PCI Express Gen2
˗ 1x SATA Gen3
˗ 1x USB 3.0 w/PHY
˗ 1x USB 2.0 w/ULPI
• Ethernet Packet Accelerator
˗ 2x GbE (2.5G or 1G)
• Datapath
˗ Packet Acceleration Engine (PPFE)
˗ Security acceleration engine (SEC)
• 2x SD 3.0/SDIO/eMMC
• QSPI, 1x SPI, 2x UART, 2x I2C
• 2x I2S, 5x SAI
• Secure Boot, Trust Architecture, ARM TrustZone
• Advanced Power Management
• Package: 9.6x9.6mm, routable in 4-layers
CCI-400 Coherent Interconnect
Secure Boot
Trust Zone
Power Management
2x SD 3.0/SDIO/eMMC
2x I2C
2x I2S, 5x SAI
QSPI, 1x SPI
2x UART
64-bit
DDR2/3
Memory
Controller
16-bit
DDR3L
Memory
Controller
64KB
SRAM
GPIO, JTAG
SEC
256KB L2
ARM
Cortex-A53
32KB
L1-D
32KB
L1-I
1x USB3.0 + PHY3-Lane 6GHz SERDES
PC
Ie 2
.0
PPFE
SA
TA
3.0
Gb
E
Gb
E
Samples Production
April-2016 Q4-2016
1x USB2.0
Sec Monitor
PUBLIC USE3 #NXPFTF
LS1012A High Level Features
• Processor Complex
− 64-bit ARM Cortex-A53 up to 800 MHz
>2200 Coremarks under 2W
NEON SimD / DP FPU
32KB/32KB L1 Parity protected Cache & 256KB L2 Cache with ECC
• Data Interfaces (up to 2x 6GHz SerDes Lanes)
− 2x Gb Ethernet (2.5G/1G)
− 1x USB3.0 w/PHY
− 1x USB2.0 w/ULPI
− 1x PCIe Gen2 (5 GHz) (x1)
− 1x SATA-3 (6 GHz)
• Control I/Os
− 2x I2C, 1x SPI
− 2x UARTs
− 2x I2S, 5x SAI
− Watchdog/Timers
− 16 dedicated GPIOs, 6 PWM Capable
• Memory Interfaces
− QSPI (NOR flash)
− 1x SPI
− 2x SDIO 3.0
− DDR3L-1066 MHz (16b)
• Packet Acceleration
− Packet Acceleration Engine
2Gbps of PPPoE/NAT routing with 390B packets
RSO/LRO offload
− Hardware Security Engine
400 MB/s block mode encryption
AES256 CBC, ECB, XTS
XOR
• Hardware/Silicon Security
− Secure Boot, JTAG Blocking, 8Kb OTP Memory
− ARM TrustZone + Trust Architecture
− DRM compliance
• Battery Operation
− Dynamic Frequency Scaling (DFS) with integrated power management
− USB charging
PUBLIC USE4 #NXPFTF
LS1012A Packet Forwarding Engine – Performance Estimates
NAT routing targets should be achieved with minimal CPU impact for IPV4/6
acceleration
Ethernet to Ethernet: NAT Routing
Frame
Size
Bi-dir
thruput
(IPV4) –
Mbps
Bi-dir
thruput
(IPV6) -
Mbps
CPU
utilization
target
64 2000 2000 <5%
128 2000 2000 <5%
256 2000 2000 <5%
512 2000 2000 <5%
1024 2000 2000 <5%
1280 2000 2000 <5%
1518 2000 2000 <5%
TCP (ac) UPD (ac) TCP (n+ac) UDP (n+ac)
TX Target 850 956 1050 1200
RX Target 850 957 1050 1200
0
200
400
600
800
1000
1200
1400
Th
rup
ut
Mb
ps
WLAN to Ethernet
PUBLIC USE5 #NXPFTF
LS1012A Ultra-low Form-factor Package
• Innovative Laminate BGA Technology
− Signal pins in outer two pad rows with 0.5mm
pitch
− Inner balls with 0.8mm pitch used only for power
and ground
• Supports cost-effective 4-layer PCB
• Enables designs with severe space
constraints
9.6mm
9.6mm
PUBLIC USE6 #NXPFTF
LS1012A Power Management Features
• Packet-forwarding engine offloads CPU and
reduces power consumption
• Typical 1W power consumption when active
• Dynamic Frequency Scaling
• On-chip temperature monitor
• Clock-gating of major functional blocks
PUBLIC USE7 #NXPFTF
LS1012A Security & Trust Architecture Features
A53
Internal BootROM
Security Fuse Processor
PPFE
DDRC
TZ
AS
C
SEC 5.5
IPsec ucode
Security Monitor
Secure Debug Ctrl
HP_TMP
PROG_SFP
DESAAESA
Job Queue
Controller
DECO
DM
AR
TIC
MDHAPKHA RNG
OCRAM
TZ
PC
TZ
MA
Security Capabilities Supported
• Secure boot – hardware root of
trust
• Secure key handling
• Tamper detection
• Secure manufacturing
• Secure debug
• ARM TrustZone
• Cryptographic acceleration
PUBLIC USE8 #NXPFTF
LS1012A Cryptographic Acceleration Features
• (1) Public Key Hardware Accelerator (PKHA)
• RSA and Diffie-Hellman (to 4096b)
• Elliptic curve cryptography (1024b)
• Supports Run Time Equalization
• (1) Random Number Generator (RNG)
• NIST Certified
• RNGB in P1010, RNG4 in PSC9131
• (1) Message Digest Hardware Accelerators (MDHA)
• SHA-1, SHA-2 256,384,512-bit digests
• MD5 128-bit digest
• HMAC with all algorithms
• (1) Advanced Encryption Standard Accelerators (AESA)
• Key lengths of 128-, 192-, and 256-bit
• ECB, CBC, CTR, CCM, GCM, CMAC, OFB, CFB, and XTS
• (1) Data Encryption Standard Accelerators (DESA)
• DES, 3DES (2K, 3K)
• ECB, CBC, OFB modes
• (1) CRC Unit
• CRC32, CRC32C, 802.16e OFDMA CRC
• Header & Trailer off-load for the following Security Protocols:
• IPSec, SSL/TLS, 3G RLC, PDCP, SRTP, 802.11i, 802.16e, 802.1ae
CHAs
DESAAESA
Job Queue
Controller
Descriptor
ControllerD
MA
RT
IC
MDHAPKHA RNG
Job Ring I/F
Function Rate (Gbps)
AES 1.6
3DES 1.4
SHA-256 1.9
RSA (TBD)
IPSec 1.6
IPSec @ (IMIX) 1.1
PUBLIC USE9 #NXPFTF
LS1012A
ENABLEMENT
PUBLIC USE10 #NXPFTF
LS1012A
VR5100
PMICK22USB to JTAG
KW41ZBLE /
ThreadSDHC2
eMMC
memory
SDIO Wi-
Fi Module
Arduino
Shield Header
RGMII256MB
16b DRAM
128MB
NOR Flash
QuadSPI
DDR3L
PCIe Half-height
mPCIe Connector
GbE
PHY
I2C1
SAI2
GbE
SATA3SATA
SGMIIGbE
GbE
PHY
USB2.0 & 3.0 USB
Connector
LS1012A-RDB Board
Features
• 128MB NOR Flash
• 256MB DDR3L DRAM
• 2x GbE
• 1x mPCIe
• 1x SATA
• USB3.0
• USB2.0
• KW41Z 2.4GHz radio
supports Thread &
Bluetooth Low Energy
• Arduino Shield header
for expansion
PUBLIC USE11 #NXPFTF
LS1012A-RDB
mPCIe
Slot
1 GbE
1 GbE
SD
card
Slot
Arduino
Shield
SATA
WiFi
US
B
KW41Z
Top side Bottom side
PUBLIC USE12 #NXPFTF
LS1012A Software Offering
Software Platform Description Pricing Enables
SDK (Yocto-based) • General-purpose Linux SDK,
supporting all QorIQ
processors
• Yocto build environment
• Free of charge • Scalable networking,
industrial and consumer
applications
• Migration from older QorIQ
devices
Application Solution
Kit (BHR)
• Optimized Linux networking
solution with hardware packet
acceleration
• OpenWRT build environment
• $10,000 for
source code
• Binary image
free of charge
High performance and fast time
to market for broadband
networking applications such as
gateways & routers
Application Solution
Kit (NAS)
• Optimized Linux networking
solution with hardware packet
acceleration
• OpenWRT build environment
• $10,000 for
source code
• Binary image
free of charge
High performance and fast time
to market for consumer network
attached storage & other HDD
or SSD based applications
PUBLIC USE13 #NXPFTF
ASK Pricing
Part number Resale
Price
Description Tech support by
FAE/DFAE/ TIC
Support & Maintenance by
Factory Software Team
LS1012A-SW-ASK $10,000 LS1012A OpenWRT Linux Application Solution Kit
(ASK)
Yes Not Included
*VoIP firmware and Packet forwarding Engine firmware are always supplied as binary libraries
ASK licensing
Part number Description Tech support by
FAE/DFAE/ TIC
Support & Maintenance by
Factory Software Team
ASK-SERVICE LS1012A Software Feature Request NRE Yes Included in Premium Level Support
NRE features
Part number Resale
Price
Description Ability to request
custom features
Support & Maintenance by
Factory Software Team
LS1012A-SWSP-PRM $50,000 LS1012A Software Support Plan - Premium Level
250 Hours / 12 Months
Yes Yes
LS1012A-SWSP-PLS $25,000 LS1012A Software Support Plan - Plus Level
100 hours / 12 months
No Yes
ASK Commercial Support Plans
PUBLIC USE14 #NXPFTF
Software Commercial Support Program
Support Level Premium Plus
Part Numbers LS1012A-SWSP-PRM LS1012A-SWSP-PLS
New ASK software releases* ● ●Assigned a Voucher ID for
software support issues ● ●Access to test codes to facilitate
early feature integration ● ●Ability to request custom features
●Software support hours included
250 100
Annual Fee $50,000 $25,000
QorIQ LS1012A ASK Support Plan Options
PUBLIC USE15 #NXPFTF
LS1012A Timeline
Q1 Q2 Q3 Q4
Mar Apr May Jun Jul Aug
NXP TechForum
May 16-19, Austin
Press Announcement
Feb 22, Embedded World
Nuremberg, Germany
Jan Feb
LS1012A
Samples
LS1012A RDB
Samples
Sep
Channel Launch
Oct Nov
LS1012A RDB
Production
LS1012A
Production
Software
EAR-1
Software
EAR-2
Software
Alpha
Software
Rev0.6
PUBLIC USE16 #NXPFTF
TARGET MARKETS &
DIFFERENTIATED
FEATURES
PUBLIC USE17 #NXPFTF
LS1012A Differentiated Features & Target Applications
Performance starts with the core
• First 64-bit ARM Cortex-A53 core to be offered in a sub- 10x10 mm package, delivering over 2,000 CoreMark® of performance at 1W (typical) for outstanding performance at exceptionally low power utilization
• Best in class 2.5 CoreMark / mW ratio
Broadest range of peripheral and I/O features in the sub-$10 ASP price range
• Only product in its class to offer Packet Acceleration for IP forwarding and NAS, delivering ourstanding packet throughput for this power/package envelope
• Trust and Security acceleration enables root of trust and high performance encryption consistent with much higher cost microprocessors
• First in its class to offer 64-bit support for battery powered mobile applications and performance efficiency
• Only 1W 64-bit processor to combine USB 3.0 with integrated PHY, PCIe, 2.5 Gigabit Ethernet and SATA3 on a single SoC to enable lower system-level costs
• Enables low-cost, 4-layer board level designs together with high system level integration to support ultra-small form factor systems
LS1012A Target Applications
Consumer NAS
Value tier IOT gateway
Battery Powered Mobile NAS
Entry BB Ethernet Gateway
Trusted Gateway
Industrial Automation & Control
Building Control systems
Ethernet Drives
Networked Audio
DDR3L
ControllerL2 Cache w/ECC
USB3.0
w/PHY
Cortex-A53ARMv8 64b Core
L1 Cache w/ECC
Serial IO
PCIe SATA 3
1x GbE
Packet Engine Security Engine
USB2.0 1x GbE
PUBLIC USE18 #NXPFTF
USE CASE
EXAMPLES
PUBLIC USE19 #NXPFTF
IOT Gateway Use CaseValue IOT Gateway
PUBLIC USE20 #NXPFTF
Value IoT Gateway with Audio Networking
PUBLIC USE21 #NXPFTF
Consumer NAS/DAS Use Case
Consumer NAS/DAS
w/optional Wi-Fi
PUBLIC USE22 #NXPFTF
Ethernet Drive and USB to SATA DAS Use Cases
Ethernet Drive
USB to SATA Bridge
PUBLIC USE23 #NXPFTF
Battery Powered Portable NAS Use Case
Portable NAS/Router with
battery power option
PUBLIC USE24 #NXPFTF
BB Ethernet Gateway Use Case
Entry BB Ethernet Gateway
PUBLIC USE25 #NXPFTF
Collateral
Available Now on Extranet:
• Datasheet (preliminary)
• Reference Manual (preliminary)
Going Live on 22nd February:
• Press release
• Product Summary Page
• Fact Sheet
Available by channel launch:
• Tools Summary Page
• LS1012A-RDB & documentation
• Videos
• White Papers
• Application Notes
• Kill sheets
• Distributor communicator
• Demos
• Blogs
PUBLIC USE26 #NXPFTF
3rd Party Support
We are currently in discussion with the following 3rd parties to support
LS1012A:
• WindRiver: WRLinux & VxWorks
• Mentor Graphics
• MontaVista
• Multiple EBS partners
• ODMs in Taiwan
• Greenhills
• And others
PUBLIC USE27 #NXPFTF
Part Numbers
• Evaluation board: LS1012ARDB: $495 Resale
• Extended temp part numbers to follow later
LS1012 Family Part Numbers
Device Part Number TEMP Security CPU / DDR
LS1012A
LS1012ASN7EKA S N 600/1000
LS1012ASN7HKA S N 800/1000
LS1012ASE7EKA S E 600/1000
LS1012ASE7HKA S E 800/1000
PUBLIC USE28 #NXPFTF
SUMMARY & CALL
TO ACTION
PUBLIC USE29 #NXPFTF
QorIQ LS1012A Summary
• LS1012A is the world’s smallest and
lowest power 64-bit processor
• LS1012A brings line-rate networking
performance to
− IOT Gateways
− Networked Audio
− Industrial control
− Ethernet drives
− Etc
• Press announcement on 22nd February
• First samples in April, early boards in
May, channel launch in June 2016
PUBLIC USE30 #NXPFTF
Call to Action
• Promote the LS1012A to your customers!
• Look for key customers for early engagement
• Part numbers are active – please register opportunities in CRM
• Make sure your local distributor branch offices are aware
• Use social media to spread the word
PUBLIC USE31 #NXPFTF
LS1012A OVERVIEW
TECHNICAL SESSION
PUBLIC USE32 #NXPFTF PUBLIC USE32 #NXPFTF
AGENDA
• Introduction to the QorIQ LS1012A Architecture
Details
− Clocking and POR
− Pin Multiplexing
− SerDes and Ethernet
− Other Interfaces
• Enablement Tools and Board Bring Up
• Summary
PUBLIC USE33 #NXPFTF
LS1012A Block Diagram • Single ARMv8 64-bit Cortex-A53 processor
• 1840 DMIPS / 2240 Coremark @ 800MHz
• NEON Co-processor and DP FPU
• 256 KB L2 cache with ECC
• Memory Controller
• DDR3L up to 1000 MHz
• 16-bit data bus, 1 chip select
• High Speed Interconnect
• 1x PCI Express Gen2 (RC/EP)
• 1x SATA Gen3
• 1x USB 3.0 w/PHY
• 1x USB 2.0 w/ULPI
• Ethernet Interfaces
• 2x GbE (2.5G or 1G)
• 1 RGMII
• Datapath
• Packet Acceleration Engine (PPFE)
• Security acceleration engine (SEC)
• 2x SD 3.0/SDIO/eMMC
• QSPI, 1x SPI, 2x UART, 2x I2C
• 2x I2S, 5x SAI
• Secure Boot, Trust Architecture, ARM TrustZone
• Advanced Power Management
• Package: 9.6x9.6mm, routable in 4-layers
1x USB3.0 + PHY
1x USB2.0
CCI-400 Coherent Interconnect
Secure Boot
Trust Zone
Power Management
2x SD 3.0/SDIO/eMMC
2x I2C
2x I2S, 5x SAI
QSPI, 1x SPI
2x UART
64-bit
DDR2/3
Memory
Controller
16-bit
DDR3L
Memory
Controller
64KB
SRAM
GPIO, JTAG
SEC
256KB L2
ARM
Cortex-A53
32KB
L1-D
32KB
L1-I
3-Lane 6GHz SERDES
PC
Ie 2
.0
PPFE
SA
TA
3.0
Gb
E
Gb
E
Sec Monitor
PUBLIC USE34 #NXPFTF
Product ComparisonFeature LS1012A LS1024A LS1021A
CPU/number of cores ARMv8 - A53; single core
64 bit
ARMv7: dual-core Cortex A9 32
bit
ARMv7: Dual core; Cortex A7,
32 bit
Interconnect CCI-400 AMBA AXI/AHB @250MHz CCI-400
Interrupt Controller GIC-400 GIC v1.0 GIC-400
Frequency(Core/Platform/DDR)
(MHz)
800/250/500 1200/500/533 1000/300/1600
Clocking Single source Crystal Oscillator Single source Crystal Oscillator Single Source Oscillator
DDR DDR3L (MMDC)** DDR3 DDR3L/DDR4
Network/Packet processing PFE PFE eTSEC 2.0
Crypto SEC Third-party IP block SEC
PCIe Gen 2 (5Gb/s)
Supports RC/EP
Gen 2 (5Gb/s) Gen 2 (5Gb/s)
Supports RC
SATA SATA 6Gb/s SATA 6Gb/s SATA 6Gb/s
Boot Sources QSPI NOR, I2C, SPI, UART, SATA QSPI/IFC/SD MMC
Package Type FC-LGA FC-PBGAH FC-PBGA
Power / Size / Pin Count <3W / 9.6mm x 9.6mm / 211 4W(typ) / 21mm x 21mm / 625 3.82W(max) / 19mm x 19mm /
525
Key differentiators
ARMv8, 64 bit
Low cost
Low Power
**From i.MX processor family
PUBLIC USE35 #NXPFTF
Product Comparison (Cont’d)
Feature LS1012A LS1024A LS1021A
TMU Y N Y
Secure Boot Y Y Y
ARM Trust Zone ARMv8 Trust Arch Y N
IOMMU N N SMMU
eSDHC 2x eSDHC
(SD/SDIO/eMMC/eSDIO), 4 bit
N 1x eSDHC
(SD/SDIO/MMC/eMMC/eSDIO),
8 bit
SPI/I2C/QSPI/FTM/FlexCAN/S
AI/GPIO
SPI, 2x I2C, QSPI, 2x FTM,
2x SAI, GPIO
2x SPI, I2C, GPIO SPI, 3x I2C, QSPI, FTM, 4x
FlexCAN, 4x SAI, GPIO
USB 3.0/USB 2.0 USB 3.0 with PHY/ USB 2.0
ULPI
USB 3.0 with PHY/
USB 2.0 with PHY
USB 3.0 with PHY/ USB 2.0
ULPI
PUBLIC USE36 #NXPFTF
CLOCKING & POR
PUBLIC USE37 #NXPFTF
LS1012A Single Source Clocking Scheme
125M RGMII ref CLKCGA PLL1 /2
EXTAL
A53 Core Cluster
32KB
I-Cache
32KB
D-Cache
256KB L2 cache
PLATFORM
PLL
/4Platform clock
eSDHC
IP Blocks/2
Clo
ck
Sele
ctio
n
Oscill
ato
r
XTAL
100M
125M (SYSCLK)
125M Differential
SerDes PLL1
SD1_REF_CLK1_P/N Clo
ck
se
l
Optional Serdes ref clk
125M/100M default
RCW[CGA_P LL1_RAT]
RCW[C1_PLL_SEL ]
500M DDR Controller
1000M
QSPI
RCW[SerDes _INT_REFCLK]
USB PHY
SerDes PLL2
25M input from
On board Crystal
PFE
PUBLIC USE38 #NXPFTF
POR Signals Considerations
• HRESET_B signal doesn't exist
• RESET_REQ_B signal is multiplexed with QSPI_A_DATA3, GPIO1_14 and IIC2_SDA
− The primary function is QSPI_A_DATA3. If device fails to read RCW, RESET_REQ_B will not be asserted
− RESET_REQ_B may not be available if any of the alternate functions is used
• ASLEEP is multiplexed with USB1_PWRFAULT and GPIO2_01
− Multiplex options can be chosen using RCW
• To debug POR sequence, user may want to select RESET_REQ_B and/or ASLEEP in RCW
• Crystal oscillator as the primary source of clock
• Minimum ramp rate for VDD is 0.06V/ms
− VDD should ramp up within 16ms
PUBLIC USE39 #NXPFTF
POR Sequence
• PORESET should be asserted when power starts ramping up
• External crystal provides 25 MHz sinusoidal input
• cfg_eng_use and cfg_eng_use_2 are internal POR config pins sampled when VDD ramps up
• 25MHz is fed to a PLL which outputs 125 MHz single ended for platform PLL, 100MHz single ended for CGA1 PLL, and 125MHz differential for SerDes PLL
− The 125 MHz single ended output is referred as SYSCLK in LS1012A documents
• PORESET is required to asserted for 32 SYSCLKs after stable SYSCLK is available
− Minimum assertion time for PORESET is 100ms
• cfg_rcw_src is sampled at PORESET de-assertion
• RCW is read from QSPI memory.
− QSPI is the only external memory for storing RCW
• Platform and Core PLLs start locking based on RCW fields
• PBI is read after platform clock is available
− PBI must write boot vector location at SCRATCHRW2 register
• ASLEEP is de-asserted
• A53 comes out of reset and jumps to boot vector location programmed at SCRATCHRW2 register
PUBLIC USE40 #NXPFTF
LS1012A Boot Option – QSPI
• QSPI is the only option for loading RCW from external memory, in 1-bit mode
− Other option is hard coded RCW
• A53 fetches first instruction from address 0x0000_0000
• BOOTROM present in 0x0000_0000 jumps execution to location fed in SCRATCHRW2 register
• PBI should populate SCRATCHRW2 register with start address of the boot image
• QSPI is XIP (execute-in-place) memory
− PBI may write start address of QSPI boot image in SCRATCHRW2 register
− Boot image in QSPI can be directly executed in place
• Hard-coded RCW option should only be used to restore/program the RCW on blank QSPI
memory
Note
PUBLIC USE41 #NXPFTF
Boot Image from PCIe – Use Case 1
• QSPI has to be present on board
− The RCW has to be fetched from QSPI
• If LS1012A is configured as PCIe EP, the RC is supposed to write boot image on LS1012A’s memory space
− Load RCW & PBI from QSPI
− The PBI should point SCRATCHRW2 register to a firmware in QSPI
− The link training will start after PBI is executed
− The firmware in QSPI will
Configure DDR controller to make DDR SDRAM accessible
Configure inbound windows to make CCSRBAR and DDR SDRAM accessible to RC
Set CFG_READY to make configuration space available to RC
Wait in a loop for a flag to be written by RC
− The RC will
be able access config space as soon as CONFIG_READY is set
After enumeration, write boot image on DDR SDRAM
Write start vector of boot image in a pre-defined location say U_BOOT_START
Set a predefined flag to indicate boot image is ready to be used
− The EP will read U_BOOT_START after RC sets the flag and jump to execute from boot image
PUBLIC USE42 #NXPFTF
Boot Image from PCIe – Use Case 2
• QSPI has to be present on board
− The RCW has to be fetched from QSPI
• If LS1012 is supposed to boot from boot image available in PCIe memory
− Load RCW & PBI from QSPI
− The PBI should create appropriate PCIe outbound window to make boot image available
− The PBI should point SCRATCHRW2 register to PCIe memory
− The link training will start after PBI is executed
− The ARM A53 will fetch its code from PCIe
PUBLIC USE43 #NXPFTF
Boot Image From SD/eMMC
• QSPI has to be present on board
− The RCW has to be fetched from QSPI
• If boot image is available in SD/eMMC card
− Load RCW & PBI from QSPI
− The PBI should point SCRATCHRW2 register to firmware in QSPI
− The firmware in QSPI will
Configure DDR controller to make DDR memory accessible
Configure eSDHC controller
Copy boot image from pre-defined location on SD/eMMC card to DDR memory
Jump execution to the start address of boot image on DDR memory
PUBLIC USE44 #NXPFTF
PIN MULTIPLEXING
PUBLIC USE45 #NXPFTF
LS1012A PinMux OverviewD
1_M
DQ
[15:0
]
D1_M
DM
[1:0
]
D1_M
DQ
S[1
:0]
D1_M
DQ
S_B
[1:0
]
D1_M
BA
[2:0
]
D1_M
A[1
5:0
]
D1_M
WE
_B
D1_M
RA
S_B
D1_M
CA
S_B
D1_M
CS
_B
D1_M
CK
E
D1_M
CK
D1_M
CK
_B
D1_M
OD
T
D1_M
DIC
UA
RT
1_S
OU
T
UA
RT
1_S
IN
IIC
1_S
CL
IIC
1_S
DA
QS
PI_
A_D
AT
A0
QS
PI_
A_D
AT
A1
QS
PI_
A_D
AT
A2
QS
PI_
A_D
AT
A3
QS
PI_
A_S
CK
QS
PI_
A_C
S0
SD
HC
1_C
MD
SD
HC
1_D
AT
[3:0
]
SD
HC
1_C
LK
SD
HC
1_C
D_B
SD
HC
1_W
P
SD
HC
1_V
SE
L
SD
HC
2_C
MD
SD
HC
2_D
AT
[3]
SD
HC
2_D
AT
[2]
SD
HC
2_D
AT
[1]
SD
HC
2_D
AT
[0]
SD
HC
2_C
LK
PO
RE
SE
T_B
TA
_T
MP
_D
ET
EC
T_B
CLK
_O
UT
PO
RE
SE
T
Tam
per
Dete
ct
CL
K_
OU
TG
PIO
RE
SE
T_R
EQ
_B
AS
LE
EP
GP
IO
SD
1_T
X_P
[2:0
]
SD
1_T
X_N
[2:0
]
SD
1_R
X_P
[2:0
]
SD
1_R
X_N
[2:0
]
SD
1_R
EF
_C
LK
1_P
SD
1_R
EF
_C
LK
1_N
SD
1_IM
P_C
AL_T
X
SD
1_IM
P_C
AL_R
X
US
B1_D
_P
US
B1_D
_M
US
B1_V
BU
S
US
B1_ID
US
B1_T
X_P
US
B1_T
X_M
US
B1_R
X_P
US
B1_R
X_M
US
B1_R
ES
RE
F
US
B1_D
RV
VB
US
US
B1_P
WR
FA
ULT
EM
I1_M
DC
EM
I1_M
DIO
EC
1_T
XD
[3]
EC
1_T
XD
[2]
EC
1_T
XD
[1]
EC
1_T
XD
[0]
EC
1_T
X_E
N
EC
1_G
TX
_C
LK
EC
1_R
XD
[3]
EC
1_R
XD
[2]
EC
1_R
XD
[1]
EC
1_R
XD
[0]
EC
1_R
X_C
LK
EC
1_R
X_D
V
D1_M
VR
EF
TD
1_A
NO
DE
TD
1_C
AT
HO
DE
SAI1
SAI3, SAI4
Rx Only
USB 2.0 ULPI
GPIO
FTM1, FTM2
SPI
SAI3
SAI4
Rx
GPIO GPIO
QS
PI
2 b
it
IIC
2
QS
PI
2 b
it
QS
PI
2 b
it
QS
PI
2 b
it
GPIO
FT
M1
FT
M2
USB1 (3.0)
eSDHC1 eSDHC2
3 Lane
SerDes Se
rDe
s
Re
fclk
Se
rDe
s
EM
I1
RGMII Ethernet (EC1)
GPIO
DDR3L UA
RT
1
IIC
1
QSPI 4 bit
GP
IO
SAI 2, SAI3, SAI4
PUBLIC USE46 #NXPFTF
LS1012A PinMux Overview – A
D1_M
DQ
[15:0
]
D1_M
DM
[1:0
]
D1_M
DQ
S[1
:0]
D1_M
DQ
S_B
[1:0
]
D1_M
BA
[2:0
]
D1_M
A[1
5:0
]
D1_M
WE
_B
D1_M
RA
S_B
D1_M
CA
S_B
D1_M
CS
_B
D1_M
CK
E
D1_M
CK
D1_M
CK
_B
D1_M
OD
T
D1_M
DIC
UA
RT
1_S
OU
T
UA
RT
1_S
IN
IIC
1_S
CL
IIC
1_S
DA
QS
PI_
A_D
AT
A0
QS
PI_
A_D
AT
A1
QS
PI_
A_D
AT
A2
QS
PI_
A_D
AT
A3
QS
PI_
A_S
CK
QS
PI_
A_C
S0
SD
HC
1_C
MD
SD
HC
1_D
AT
[3:0
]
SD
HC
1_C
LK
SD
HC
1_C
D_B
SD
HC
1_W
P
SD
HC
1_V
SE
L
RE
SE
T_R
EQ
_B
eSDHC1
GPIO
DDR3L UA
RT
1
IIC
1
QSPI 4 bit
GPIO GPIO
QS
PI
2 b
it
IIC
2
QS
PI
2 b
it
QS
PI
2 b
it
QS
PI
2 b
it
GPIO
FT
M1
FT
M2
PUBLIC USE47 #NXPFTF
LS1012A PinMux Overview – B
SD
HC
2_C
MD
SD
HC
2_D
AT
[3]
SD
HC
2_D
AT
[2]
SD
HC
2_D
AT
[1]
SD
HC
2_D
AT
[0]
SD
HC
2_C
LK
PO
RE
SE
T_B
TA
_T
MP
_D
ET
EC
T_B
CLK
_O
UT
EX
TA
L
XT
AL
SC
AN
_M
OD
E_B
TC
K
TD
I
TD
O
TM
S
TR
ST
_B
TJT
AG
_E
N
TB
SC
AN
_E
N_B
PO
RE
SE
T
Tam
per
Dete
ct
CL
K_
OU
T
EX
TA
L
XT
AL
Re
se
rve
d
TJT
AG
_E
N
TB
SC
AN
_E
N_B
GP
IO
GP
IO
SA
I5 T
x
SA
I5 T
x
SA
I5 T
x
FT
M_E
XT
CLK
SA
I5 R
x
SA
I5 R
x
SA
I5 R
x
SPI
eSDHC2 JTAG
GPIO
FTM1, FTM2
GPIO
UART2
SAI1
PUBLIC USE48 #NXPFTF
LS1012A PinMux Overview – C
AS
LE
EP
GP
IO
SD
1_T
X_P
[2:0
]
SD
1_T
X_N
[2:0
]
SD
1_R
X_P
[2:0
]
SD
1_R
X_N
[2:0
]
SD
1_R
EF
_C
LK
1_P
SD
1_R
EF
_C
LK
1_N
SD
1_IM
P_C
AL_T
X
SD
1_IM
P_C
AL_R
X
US
B1_D
_P
US
B1_D
_M
US
B1_V
BU
S
US
B1_ID
US
B1_T
X_P
US
B1_T
X_M
US
B1_R
X_P
US
B1_R
X_M
US
B1_R
ES
RE
F
US
B1_D
RV
VB
US
US
B1_P
WR
FA
ULT
EM
I1_M
DC
EM
I1_M
DIO
USB1 (3.0)3 Lane
SerDes Se
rDe
s
Re
fclk
Se
rDe
s
EM
I1G
PIO
PUBLIC USE49 #NXPFTF
LS1012A PinMux Overview – D
EC
1_T
XD
[3]
EC
1_T
XD
[2]
EC
1_T
XD
[1]
EC
1_T
XD
[0]
EC
1_T
X_E
N
EC
1_G
TX
_C
LK
EC
1_R
XD
[3]
EC
1_R
XD
[2]
EC
1_R
XD
[1]
EC
1_R
XD
[0]
EC
1_R
X_C
LK
EC
1_R
X_D
V
D1_M
VR
EF
TD
1_A
NO
DE
TD
1_C
AT
HO
DE
RGMII Ethernet (EC1)
SAI 2, SAI3, SAI4
SAI3
SAI4
Rx
SAI3, SAI4
Rx Only
USB 2.0 ULPI
PUBLIC USE50 #NXPFTF
LS1012A PinMux (Cont’d)
RESET_REQ_B
The RESET_REQ_B is selected automatically by hardware if ITS=1
Software cannot change the muxing using PMUXCR.
If ITS =0, the selection will depend on RCW bits
In case of secure boot only 2-bit QSPI is available
JTAG IOs
The JTAG IOs are muxed with functional signals.
The selection is done through another IO - TJTAG_EN.
The TJTAG_EN must be driven 0 if other functions have to be selected on JTAG IOs.
5 JTAG pins used for other functional protocol when TJTAG_EN is 0 would not be tested through
Boundary Scan.
TA_TMP_DETECT_B
The selection between TA_TMP_DETECT_B and GPIO muxed on it is through Fuse and not RCW.
If ITS fuse set, TA_TMP_DETECT_B is selected, otherwise GPIO
PUBLIC USE51 #NXPFTF
Dynamic Pin Mux Control
All LS1012A pinmuxing is controlled through RCW or POR.
However QSPI pins muxing can be changed by software at runtime.
This allows the user to use QSPI IOs for boot and then use these IOs for GPIO.
This is done by the SCFG_PMUXCR0 Register in the CCSR space.
Note: The mux control change is only supported for QSPI to GPIO functionality change.
Note: The muxing must only be changed after booting/ QSPI access is done and complete (i.e. only after System
Ready).
PUBLIC USE52 #NXPFTF
Other Important Muxing on LS1012A
• USB_DRVVBUS and PWRFAULT
− DRVVBUS for the USB 2.0 controller is not provided.
This will be implemented by the external transceiver.
The Controller can write to the external ULPI PHY registers to control the DRVVBUS.
• The PWRFAULT for USB 2.0 is implemented as follows:
− SCFG bit USB_PWRFAULT_SELCR[31] (offset x414):
0 - PWRFAULT tied to 0 (no PWRFAULT)
1 - PWRFAULT shared with the USB 3.0 signal (IO)
• EMI Interface Muxing
− The MDIO could be directed to internal SerDes or external PHYs
− Configure using MDIOSELCR[0] (Offset- 0x484)
MDIOSELCR[EMI1_MDIO] Source/destination select
0: MDIO to/from SerDes(default)
1: MDIO to/from external Ethernet PHY (through IO)
• The MDC goes to both destinations always.
PUBLIC USE53 #NXPFTF
SERDES &
ETHERNET
PUBLIC USE54 #NXPFTF
LS1012A SerDes
• Single SerDes module with 3 data lanes supported on the device.
• Two PLL’s used for clocking individual lanes.
• PLL1 Reference Clock pinned out on the package, provides clock to both PLL
• Option to provide PLL1 reference clock (controllable via RCW)
With an external differential 100 MHz or 125 MHz clock.
Can be driven internally with a 125MHz clock derived from the 25MHz on chip crystal oscillator.
• LS1012A supports the following protocols through SerDes
1. One PCIe (x1) (2.5/5.0 Gbps)
RC/EP support
2. One SATA (1.5/3.0/6.0 Gbps)
3. Up to two 1000 Base-KX
4. Up to two SGMII 2.5G
5. Up to two SGMII
PUBLIC USE55 #NXPFTF
LS1012A SerDes Lane Multiplexing
“mn” indicates MAC#
SRDS_PRTCL_S1
RCW[128:143]
Lane A Lane B Lane C Lane D RGMII Per lane
PLL
mapping
Considerations of this SerDes
protocol (validate with Mohit S)
0x0000 unused MAC #2 2222 Both PLLs should be powered down using RCW bits
SRDS_PLL_PD_S1 (RCW[168:169])
0x2208 sg.m1
(2.5G)
sg.m2
(2.5G)
UN
US
ED
SATA - 1122 2.5G SGMII requires 125MHz SerDes clock input on
PLL1
0x0008 Unused Unused SATA MAC #2 1122 PLL1 cannot be powered down as common clock is
used.
0x3508 sg.m1 PCIe(x1) SATA MAC #2 1122
0x3305 sg.m1 sg.m2 PCIe(x1) - 2222 PLL1 is unused, should be powered down using
using RCW bits SRDS_PLL_PD_S1 (RCW[168:169])
0x2205 sg.m1
(2.5G)
sg.m2
(2.5G)
PCIe(x1) - 1122 2.5G SGMII requires 125MHz SerDes clock input on
PLL1
0x2305 sg.m1
(2.5G)
sg.m2 PCIe(x1) - 1222 2.5G SGMII requires 125MHz SerDes clock input on
PLL1
0x9508 TX_CLK PCIe(x1) SATA MAC #2 1112 TX_CLK is a 100MHz clock output on Lane A for EP
0x3905 sg.m1 TX_CLK PCIe(x1) MAC #2 1112 TX_CLK is a 100MHz clock output on Lane B for EP
0x9305 TX_CLK sg.m2 PCIe(x1) - 1112 TX_CLK is a 100MHz clock output on Lane A for EP
PUBLIC USE56 #NXPFTF
TX_CLK is an output signal on one of the 3 Serdes lanes of LS1012A.
It provides a 100 MHz differential reference clock that can be used by an Endpoint.
This facilitates a low cost solution by eliminating the need for an onboard clock source for the EP
SRDS_PRTCL_S1
RCW[128:143]
Lane A Lane B Lane C Lane D Considerations of this SerDes
protocol
0x9508 TX_CLK PCIe(x1) SATA 100MHz clock output on Lane A for EP
0x3905 sg.m1 TX_CLK PCIe(x1) 100MHz clock output on Lane B for EP
0x9305 TX_CLK sg.m2 PCIe(x1) 100MHz clock output on Lane A for EP
PUBLIC USE57 #NXPFTF
RGMII interface is driven by MAC2 of PFE.
SGMII on SerDes lane A is driven by MAC1
SGMII on SerDes lane B is driven by MAC2
PFE
MUX
SerDesLane A Lane B
MAC1 MAC2
2.5G/1G/100M/10M FD
No Half Duplex2.5G/1G/100M/10M FD
No Half Duplex
RGMII
(EC1)
PUBLIC USE58 #NXPFTF
Ethernet Management Interface (MDIO)
MDIO registers have been changed from earlier SoCs
MDIO_CTL and MDIO_DATA are no more there
Hence MDIO driver update is required for LS1012A
MDIO registers in LS1012A are:
MII Speed Control Register (MSCR) for MDC configuration
MII Management Frame Register (MMFR) for MDIO data
transfers
Interrupt Event Register (EIR) for MII Event
For internal SerDes register programming use PHY_ADDR = 0x0
For EMI muxing between external and Internal PHY access refer
to the Pinmux section
PUBLIC USE59 #NXPFTF
OTHER INTERFACES
PUBLIC USE60 #NXPFTF
LS1012A eSDHC
LS1012A supports two eSDHC interfaces
eSDHC1:
Supports only SD cards
Card initialization happens at 3.3V, but can dynamically switch to 1.8V controlled by the
SDHC1_VSEL output pin
eSDHC2:
Supports 1.8V embedded SDIO and 1.8V eMMC
4 bit interface
PUBLIC USE61 #NXPFTF
MMDC-DDR ControllerThe DDR Controller on LS1012A Supports
16-bit data bus width (2 x8 DRAM or 1 x16 DRAM)
ECC not supported
Only one chip select.
Maximum size supported is 2GB (2x 8Gbit density DRAM)
The only Data rate supported is 1000MT/s.
Supports DDR3L(1.35V) mode only.
Configurable timing parameters
Configurable refresh scheme
Supports various ODT control schemes
Power Saving
Support of self-refresh mode entry automatically or through software negotiation.
Supports various calibration processes which can be performed either automatically by hardware or manually
through software.
PUBLIC USE62 #NXPFTF
ENABLEMENT TOOLS
& BRING-UP
PUBLIC USE63 #NXPFTF
CodeWarrior Flash ProgrammerLS1012A
connected
CWTAP
LS1012A QDS
connected
CWTAP
• Enables bare board QSPI
Flash programming via JTAG
• Provides both command line
as well as GUI versions
Snips of the tool exercised on actual Si
QSPI Flash
device part
number
PUBLIC USE64 #NXPFTF
QCVS Pinmux Tool
Type project
name
Choose
SoC
Choose
PinMuxing
componen
t
• Allows the user to select the
interfaces using a very
convenient GUI
• Shows the selected as well
as eliminated interfaces.
• Generates report of the pin
assignments.
PUBLIC USE65 #NXPFTF
SoC peripherals
list Peripheral no
longer
available[grey]
Assignable
peripheral [black]
Assign/remove
peripheral button
Last assigned
peripheral [yellow]
Eliminated by last
assigned
peripheral [yellow]
QCVS Pinmux Tool
PUBLIC USE66 #NXPFTF
Generate
Pinmuxing
report
QCVS Pinmux Tool
Pin Muxing
report
PUBLIC USE67 #NXPFTF
QCVS DDR Tool Overview
• Supports NXP DDR controllers on QorIQ LS [and PA]
SoCs
• All DDR types for both discrete and DIMM
implementation
• Has two major components: configuration and validation
PUBLIC USE68 #NXPFTF
DDR Configuration and Validation
DDR controller
properties
DDR controller
registers
Generated C
code
Constraint
errors and
warnings
PUBLIC USE69 #NXPFTF
DDR Validation: The Art of Shmooing
PUBLIC USE70 #NXPFTF
• How to quickly bring up LS1012A on a new board? (Key
points which should be considered)
On initial boards keep below mentioned provisions to allow quick
board bring up and iron out board/Software issues:
− Keep an option of Hard coded RCW. (cfg_rcw_src)
− Keep an option to enable/disable JTAG using TJTAG_EN POR
signal for debuggability.
− The above can be removed on production boards if not required.
• Take due care of pinmuxing and carefully select the RCW
bits. Also be aware of the constraints.
− In some cases RESET_REQ_B is not always available to signal
internal errors
− JTAG is muxed so debug of interfaces which are muxed with
JTAG cannot be debugged using JTAG.
• Keep the Bring-up tools like QCVS and CW Flash
programmer handy.
70
BRING-UP
PUBLIC USE71 #NXPFTF
PUBLIC USE72 #NXPFTF
PUBLIC USE73 #NXPFTF
Key Architectural Aspects of Other Interfaces, Check Them Out
As Well• SAI
• FTM
• USB
• QSPI: Only 2 bit interface available in Secure Boot Use cases
• DSPI: Only Master Mode is supported
• UART
− UART1 does not support Flow control. UART2 supports Flow control.
PCIE_PME (for power management) which is supported. There is nothing done at IP/SoC level. This functionality is emulated using GPIO. No PME pin is used.
There is no dedicated DMA controller in LS1012A. Instead, the SEC coprocessor is also used as a DMA engine as necessary.
WIP
PUBLIC USE74 #NXPFTF
• GPIO
− There are 2 GPIO controllers supported-
GPIO_1[0:31] and GPIO_2[0:17].
Following are output only GPIOs: GPIO_1[0], GPIO_1[4], GPIO_1[5],
GPIO_1[20], GPIO_1[23], GPIO_1[29] GPIO_1[31], GPIO_2[0], GPIO_2[15],
GPIO_1[11], GPIO_1[12]
Following GPIO is input only GPIO: GPIO_2[17]. This is because it is muxed
with TA_TMP_DETECT_B and creates contention during the reset.
• External Interrupt : No external IRQ signals supported on LS1012A
• WatchDog: 2 Watchdog units. One should is for secure software (WDOG2) and
non secure can use WDOG1.
• Clock sources
− 1) IP clock (platform clock)
− 2) 32k RTC
WIP
PUBLIC USE75 #NXPFTF
Key Architectural Aspects of Other Interfaces
• SAI
− Note: SAI*_BCLK is input only for all 5 SAI interfaces as the use case is always 'slave mode‘ only.
− Note: SAI1 and SAI2 support full Duplex operation, while SAI3, SAI4 and SAI5 support only Simplex operation.
• FTM
• USB
.
• QSPI: Only 2 bit interface available in Secure Boot Use cases
• DSPI: Only Master Mode is supported
• UART
− UART1 does not support Flow control. UART2 supports Flow control.
PCIE_PME (for power management) which is supported. There is nothing done at IP/SoC level. This functionality is emulated using GPIO. No PME pin is used.
There is no dedicated DMA controller in LS1012A. Instead, the SEC coprocessor is also used as a DMA engine as necessary.
WIP
PUBLIC USE76 #NXPFTF
LS1012A eSDHC Interface – Supported SD Card Modes
Mode eSDHC1 eSDHC2 Comments
SD (SD cards/SDIO cards/embedded SDIO)
SD memory card in Default (25MHz) / High speed (50MHz)
Yes No Cards are supported on
eSDHC1 interface due to availability of CD and WP pins.
Only embedded devices (SDIO, eMMC) are supported on
eSDHC2 interface. Software needs to assume card is
always present.
SDIO card in
Default(25MHz)/High speed (50MHz)
Yes No
SD memory card SDR50 Yes NoCard initialization happens in DS/HS mode at 3.3V and
later switches to SDR50 mode at 1.8VSDIO card
SDR50Yes No
SD memory card DDR50 Yes No Card initialization happens in DS/HS mode at 3.3V and
later switches to DDR50 mode at 1.8VSDIO card DDR50 Yes No
SD memory card SDR104 Yes No Card initialization happens in DS/HS mode at 3.3V and
later switches to SDR104 mode at 1.8VSDIO card SDR104 Yes No
eSDIO SDR50 No Yes
Only 1.8V eSDIO devices supported (on eSDHC2)eSDIO DDR50 No Yes
eSDIO SDR104 No Yes
PUBLIC USE77 #NXPFTF
LS1012A eSDHC Interface – Supported MMC/eMMC Modes
Mode eSDHC1 eSDHC2 Comments
MMC/ eMMC
MMC card in
Default(20MHz)/Highspeed (52MHz)
No No MMC is not supported.
eMMC DDR mode No Yes
1.8V only eMMC devices supportedeMMC HS200 No Yes
Default / High speed No Yes
PUBLIC USE78 #NXPFTF
What is Not Supported?
• DDR: NO ECC
• No IEEE 1588
• No HRESET
• RESET_REQ_B only available in Secure boot
• ASLEEP muxed with USB
• JTAG muxed
• Only 2 bit QSPI available with Secure boot
• Runtime pinmux provision available for selected
signals:
− QSPI and GPIO
78
PUBLIC USE79 #NXPFTF
MDC (MSCR Register Bit Description)
MAC pclk = 250MHz
Ratio for ~2MHz MDC clock = 0x3E
(d’62)
MDC clock = 250/2(62+1) = 1.984MHz
write_reg (0x4200044
,0x27C)
PUBLIC USE80 #NXPFTF
MDIO Register Programming Considerations• If the MSCR register is written to a non-zero value in the case of writing to MMFR when MSCR
equals 0, an MII frame is generated with the data previously written to the MMFR. This allows
MMFR and MSCR to be programmed in either order if MSCR is currently zero.
• If the MMFR register is written while frame generation is in progress, the frame contents are
altered. So poll EIR(MII) interrupt indication to avoid writing to the MMFR register while frame
generation is in progress.
MMFR register bit
Description ->->->
PUBLIC USE81 #NXPFTF
DDR Configuration and DDR Validation Tool
• DDR Configuration Tool
− Allows configuration of DDR controller memory mapped (in CCSR) registers
− View DDR controller memory mapped registers on a bit field level
− Can read DDR configuration from various sources (memory dump, DIMM’s SPD, directly from target [in the making…])
− Generates DDR initialization code in various formats: uBoot data structure, plain C code, GDB script
• DDR Validation Tool
− Picks an optimal value for a DDR controller setting by determining its working range and using the midpoint
− For behaviors/settings where the controller itself finds the optimal value during initialization, DDR Validation determines and reports the working range (i.e., read/write margins)
PUBLIC USE82 #NXPFTF
DDR Validation
What does optimal mean?
• In the context of the DDR Validation tool, it
means the most likely to work in varying
conditions (e.g., voltage and temperature)
It does not mean “fastest”. It means “reliable”
PUBLIC USE83 #NXPFTF
DDR Validation
• For both services provided by DDR
Validation, the key is determining the
working range of a setting.
• How does the QCVS DDR tool do that?
Shmooing
PUBLIC USE84 #NXPFTF
DDR Validation
• An optimal DDR controller setting is determined by trying a value, running a set of
tests, changing the value, running the tests again, and so on. Optimal value is the
midpoint of the passing range.
• You define what the “set of tests” consists of
− Choose from: BIST, DMA, Write-Read-Compare, Walking Ones, Walking Zeros and even
custom tests.
• The larger the test set, the longer the validation takes, but the more confidence
you’ll have in the results
PUBLIC USE86 #NXPFTF
ATTRIBUTION STATEMENT
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, CoolFlux, EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE, JCOP, LIFE VIBES, MIFARE, MIFARE Classic, MIFARE
DESFire, MIFARE Plus, MIFARE FleX, MANTIS, MIFARE ULTRALIGHT, MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET, TrenchMOS, UCODE, Freescale,
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