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transcript
IROC Technologies
General Presentation
June 2014
2
Who is IROC Technologies?
History: Established in 2000 in France as a spin-off from a R&D lab
US Corp launched in 2001
Memory BIST product & team acquired by Synopsys in 2004
Activity: Solutions for analyzing and improving the overall reliability of devices
Focus on Single Event Effects
Moving on process variability, environment stress, ageing
Leading commercial provider of soft error solutions: More than 200 soft error test campaigns
Serving major players in many segment of the industry (foundries, fabless, IDM, system houses)
Solutions roadmap in line with market needs
Established network of well recognized collaborators: nuclear database, neutron labs, alpha counting equipment suppliers
SEEs – Why Should I Care
Usual fields: Aero-space applications
A satellite was launched from Baikonor Cosmodrome, Kazakhstan on 31 May 2005
Failed during the 5th orbit instead of after a total of 253 orbits (2% use)
Failure Site ->
Source: Reno Harboe-Sørensen, ESA-ESTEC, ” Radiation Effects in Spacecraft Electronics“, 5th LHC Radiation Workshop –Nov-29, 2005.
A latch-up condition in a SRAM was concluded as the possible cause
SEEs: Coming down to Earth 1970’s: First studies on SRAM susceptibility to alpha particles… and still many years later:
2000’s: Alpha problems in CPU cache memories (used in high-reliability servers) Elections in Belgium: electronic voting machines on 05/18/2003 (Schaerbeek):
More votes compared to number of registered persons: shift of … 4096 votes ! A SEU effect on 13th bit in SRAM was considered as the possible causes
Now: Atmospheric neutrons, low energy protons, multi-cell errors, transients, X-rays dose effects in DRAMs
Backgrounder: The Soft Error/ SER Problem
Nuclear Physics
Understanding the Phenomena Requires a Combination of
Nuclear Physics & Semiconductor Device Physics
Neutrons
@ sea levelSi 25Mg+α
28Al+p
24Mg+n+α
Ions
Si
Transistor Bit flip,
Transient pulse
Silicon Reaction
e-
e-
e-
Electrons
PackagingImpurities
α e-
n
10B
nth7Li+α
e-
SER trends in Cells wrt Process Node
0
100
200
300
400
500
600
700
050100150200
SBU Average/node
MCU Average/node
Expon. (SBU Average/node)
Expon. (MCU Average/node)
Even though per memory bitcell SER sensitivity is decreasing, overall FIT per SoC is
increasing
SRAM SER FIT rate per node
FIT/Mb
0
100
200
300
400
500
600
700
0100200300400
FF SEU FIT rate per node
SEU Average/node
Linear (SEU Average/node)
Atmospheric Neutron Results
Alpha results are similar assuming an Ultra Low Alpha Emissivity Rate package
1
10
100
1000
020406080100120140160180200
Memory SER Logic SER (Seq + Comb)
Expon. (Memory SER) Expon. (Logic SER (Seq + Comb))
Typical SoC SER FIT rate per design
Node (nm)
FIT
SER trends in SoC wrt Process Node
Raw Cell SER Circuit SER System SER User SER
En
vir
on
men
t
SEEs: A challenging aspect of System Reliability
Single Event Effects (SEEs) - A threat to all the reliability metrics Data Integrity Availability Maintainability
Managing SER aspects – an industry-wide topic Inter-company collaboration – materials suppliers, foundries, IP & chips
providers, system integrators, etc Intra-company collaboration – system architect, reliability engineer,
hardware designer, software engineer
SE
R D
ata
Functional Failure
IROC Scope and Objectives
Single Event Fault
Single Event Transient
Single Event UpsetSingle Event Latchup,
SEGR, SEB
Soft Error
Soft Error in Logic
SBU, MBU in memory
Abstraction Level Increases => Sophisticated SEE Analysis
Device Complexity Increases => Innovative Test Methodology
TCAM
Test chips
Standard memories:
SRAM, DRAM,
FLASH, etc
FPGAs:
SRAM, FLASH,
Fuse-based, etc
CPUs, ASICs Boards Devices
IROC Offer Positioning
Foundry Libraries Design Packaging System
Cell level AnalysisLibrary characterizationFIT predictionCell optimizationTFIT tool
Circuit AnalysisDesign characterizationRisk assessmentIntrinsic FIT predictionSoCFIT tool
SER Product TestingLibrary level (characterization)Chip level (ASER/RTSER)System level (Platform Testing)Wafer alpha emission analysisPackaging Alpha emission analysis
Design SupportPatented solutions for librariesPatented solutions for designs
DE
SIG
N S
ER
VIC
E &
T
OO
LS
TE
ST
SE
RV
ICE
IROC delivers test and design solutions to ensure
that soft error risks are addressed and eradicated
SER Test Activities at IROC
Accelerated Neutron Shuttle Program
Multiple users at the same time (stack of daughterboards) allows creating
more testing opportunities for the industry.
Soft Error Testing: Accelerated Testing Sites
Triumf,
Vancouver
TSL, Sweden
Los Alamos
National Labs
Neutron Shuttle Schedule
• IROC tests mostly with white/atmospheric spectrum neutron labs
• Alpha particles test performed at IROC. Available year round
• Gamma, protons, heavy ions: pending customer need
From Components Testing…
SRAM SEU, MBU, SEL, SEFI
TCAM SRAM-like Analysis +
Search mode SEEs
DRAM Detection of memory upsets and Tref evolution
FPGA Detections in configuration memory, block RAM, F/F and logic
block upsets
ASIC and SoC Detections in embedded memories and F/F upsets.
… to Motherboard and Device Testing
Other Radiation Testing
Beam Types Heavy Ions: Jyvaskyla (Finland), UCL-HIF (Belgium), IPN (France)
Protons: UCL-LIF (Belgium), TSL (Sweden)
Alpha: in-house capabilities; Californium: ESA ESTEC, Laser Beam: EADS (France)
Applications Dedicated SET/SEU test chips: ATMEL, CNES, EADS, MindSpeed
CPUs, microcontrollers: ATMEL, CNES, ESA, e2v, EADS (+Freescale)
Memory devices: STM, ATMEL, others
ASICs, SoCs: ATMEL, Thales, CNES
Military/Aero-Space activities TID: C60 registered and calibrated source in France
Displacement damage effect
Prompt dose effect (X flash)
Dedicated Test-Chips for SER Measurements
SET
Test
SEU
Test
SET
Probe
Validation at
high frequencies
Process Technology characterizationTransient
Pulse
Width
Speed
Test
SEU rate
SET rate
Alpha Counting
Alpha Particles Contamination Issues
The semiconductor industry has reached an extremely high level of transistor integration (65 or 45nm nodes)
As a consequence, the technology is losing its natural immunization against environmental aggressions (radiations, alpha particles).
Alpha particles are generated by traces of radioactive material in the packaging. They have a very high ability to generate upsets.
Industry requirements call for very low to ultra low alpha emissions of materials (.01 to .001 alpha/cm2/hr)
More and more manufacturers need to verify the emission level and the immunization of their design.
IROC and Alpha Sciences, as third party independent specialists, help the industry tackle these issues
Types of Samples Measured
Pellets
(Molding compounds)
Si wafers
(up to 300mm)
Powder Samples
Solder Balls
Paste Samples
(solder paste)
Packaged chips
or devices
ASI Ultra Low Background Counters
• Widely used in the Industry
Hundreds of counters shipped, decades of experience in the field
• Simple and easy to use
Plug and play solution, very stable, low maintenance systems
• Highly Versatile
For any type of sample: solid, powder, paste, non conductive, you name it!
• Very Low background on an economical system
Best accuracy for the price!
We measure any type of material or devices (as long as it fits into the counting chamber)
Measurement duration takes 2 to 3 days, depending on the size of devices and alpha activity (low activity can take longer to improve the accuracy)
We sell entire alpha counting system for ASI.
(please contact us for price and conditions)
Measurement takes place either in the US or in France, for more flexibility and convenience
For more information, visit: http://www.IROCtech.com/sol_test_115.html
Our Offering
SER Simulation Tools
SER DB
Analyzed SoCdesignSPICE NetList
Response model
SoC RTL/Netlist
TFIT
SoCFIT
Analysis/Prediction platform
A cell level soft error simulator: Input : Cell netlist, technology response model, particle type,
cell layout geometry Output : SEU FIT / MCU FIT / Current pulse
Limited requirement: Access to Spice Simulator tool
Targeted Users:
Memory Designers and Bit Cell Developers
IP Development Teams (At IDM, Foundries or Fabless)
Support of different radiation environments:
Ions (Heavy & Alpha)
Atmospheric neutrons
Very fast and accurate simulator (silicon test correlated)
Charge coupling and charge sharing effects included
TFIT Overview
IROC
Technologies
User
InputConfiguration
parametersSPICEnetlist
ModelCard
Output
TFITSPICE
Simulator
SET/SEUCross section
SEU FITMCU FIT patterns
Processresponse models
Secondary Particles Nuclear
Database
TFIT Positioning in the Design Flow
MNQN
MPQN
MPQT
MNQT
QT
MNA1 MNA2
QN
Lb1 Lb2
WL
TransistorCell State
Transistor FITQT QN
MPQT 0 1 211
MPQN 0 1 211
MNQT 1 0 67
MNQN 1 0 67
MNA1 1 0 61
MNA2 0 1 61
SRAM FIT =
∑transistors
Transistor FIT
Number of different states=
678
2= 339 Failures / Mbit /10
9hours
SPICE NetList
Transistor FIT
Current Curves
TFIT
TFIT Typical Case
Cell layout contribution to FIT rate (influence of layout geometry)
SRAM SERSEU: SBU/MCU
Sequential SERSEU: State dependence, Master/Slave Contribution
Combinational SERSET
SET Statistics: PW, Frequency
Cell State/Load Influence
Cell SER Analysis – TFIT Results
Single Event Fault
Single Event Transient
Single Event Upset
Soft Error
Soft Error in Logic
SEU in memory = Soft Error
Functional Failure
Single Event Fault ► Soft Error(In-clock-cycle propagation)
Highly automated probabilistic toolsSoft Error ► Functional Failure(many clock cycles propagation)
Accelerated simulation approach
Circuit SER Analysis – The SoCFIT Platform
A circuit level SEE assessment platform
Input : Gate level netlist and timing files, RTL, SER Database
Output : FIT rate, map of contributors, deratings
Targeted users:
ASIC Designers needing Soft Errors budget assessment
Soft Error sensitivity analyses
Based on SER DB for memory and logic elements
Integrates Logic, Timing and Application (RTL) derating
Checks Efficiency of ECC and higher level mitigation techniques
Uses automated fault injection techniques
SoCFIT Overview
SoCFIT Platform Modules
Logic
derating
Time
derating
Functional
derating
Memory blocks(SER)
CombinationalLogic (SET)
SequentialLogic (SEU)
Arc
hite
ctu
ral M
odule
SE
RA
rch
Mem
FDR
SEU
FDR
SEU
TDR
Limited requirement: timing analysis or synthesis tool access (SEU TDR)
SER DB needed for the technology (built with TFIT or Test)
Reportin
g M
odule
SE
RS
cope
SEU
LDR
SET
FDR
SET
TDR
SET
LDR
User Case Flow
Default FIT Analysis
Within Spec? Refine FIT Analysis
FIT Analysis OK Error Mitigation
Select FIT DB
Load Design
Default de-rating
Hierarchical results
Per-instance data
Various data plots
Specify protection
User de-rating
Applicative de-rating
List of critical blocks
Contributors to FIT
Interactive optimization
Yes
Yes
No
No
Design Services
Design Services: Analysis
SER Analysis and qualification
New technologies SER characterisation & improvement
Specific test chip design and analysis
Design and system SER analysis
SER as a part of the overall system reliability
Design Services: SER Improvement
SER Improvement
Custom protection methodologies and design flowsfor the hardening of electronic devices
Software tools for design automation (logic &memory)
Hardened cells and IPs
Consulting for fault-tolerant design of ICs and
systems (including COTS-based)
SER Evaluation: A Growing and Rewarding Activity