*Kavita Arora (M3-1) Lisa Gentry (M3-2) Steven Wasik (M3-3) Karolina Werner (M3-4)

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M3: ProDiver 525M3: ProDiver 525*Kavita Arora (M3-1)*Kavita Arora (M3-1)Lisa Gentry (M3-2)Lisa Gentry (M3-2)Steven Wasik (M3-3)Steven Wasik (M3-3)Karolina Werner Karolina Werner (M3-4)(M3-4)

Stage : Stage : 9 Mar 299 Mar 29Chip Level Chip Level SimulationSimulation

Overall Project Objective:To design a chip for a SCUBA diver that does real-time calculations to warn To design a chip for a SCUBA diver that does real-time calculations to warn the diver of safety concerns including decompressions sickness and lung the diver of safety concerns including decompressions sickness and lung overexpansion.overexpansion.

Design Manager: Design Manager: Steven BeigelmacherSteven Beigelmacher

M3: ProDiver 525M3: ProDiver 525

StatusStatus• Schematic Verification (done)Schematic Verification (done)• LVSLVS

– PressureCalc(done)PressureCalc(done)– timetoflight (done)timetoflight (done)– timeleft (done)timeleft (done)– ascensionWatch (done)ascensionWatch (done)– getK (done)getK (done)– safetyWatch (done)safetyWatch (done)– maxDepth (done)maxDepth (done)– bottomTime (done)bottomTime (done)– Top (done)Top (done)

• Spice Entire Chip (6 out of 8 modules)Spice Entire Chip (6 out of 8 modules)

Verilog Verification (gate Verilog Verification (gate level)level)

MATLAB:depthvector = [80*ones(1,60*35) 40*ones(1,60*20) 0*ones(1,60*40)];[bodyvector,out]=pressurecalculator(depthvector);bodyvector(60*35): ans = 25.5304bodyvector(60*55): ans = 28.3850bodyvector(60*95): ans = 18.2900

SCENERIO: diver goes 80 feet for 35 min, 40 feet for 20 min, 0 feet for 40 min

VERILOG:time= 2,safetywatch = 0Test where the user will go down to 80 feet for 35 minutes, then 40 feet for 20 minutes, then 0 feet 40 minutestime= 6090,safetywatch = 1time = 6305,pres=25,depth= 80time= 9054,safetywatch = 2time = 9908,pres=28,depth= 40time= 10272,safetywatch = 1time= 12165,safetywatch = 0time = 17110, pres=18,depth= 0

Top Level SchematicTop Level Schematic

Internal RoutingInternal Routing

Top LayoutTop Layout

Summary of Design Summary of Design CharacteristicsCharacteristics

Final area 203*151=30653

Transistor Count 10110

Transistor Density 0.329820898

Aspect Ratio 1.344370861

Why Modular Spice Why Modular Spice Simulation Strategy ?Simulation Strategy ?

• Due to the large no. of edge cases, this Due to the large no. of edge cases, this simulation strategy gives us greater accuracy simulation strategy gives us greater accuracy than a single global vector set wouldthan a single global vector set would

• Testing time for global testing is unfeasible Testing time for global testing is unfeasible because it takes on the order of 150 clock because it takes on the order of 150 clock cycles to cause some outputs to change cycles to cause some outputs to change

• This is quicker and allows us to better focus This is quicker and allows us to better focus our energiesour energies

Spice Simulation Spice Simulation StrategyStrategy• Used vector sets from the verilog Used vector sets from the verilog

verificationverification• Tested the edge casesTested the edge cases• In order to decrease testing time, we In order to decrease testing time, we

brought lower order bits out of the brought lower order bits out of the modules (shows seconds as well as modules (shows seconds as well as minutes, and uses fractions of a minutes, and uses fractions of a pressure unit)pressure unit)

Bottom Time Bottom Time InputsInputs

Bottom Time Bottom Time OutputsOutputs

Get K InputsGet K Inputs

Get K OutputsGet K Outputs

Max Depth1 Max Depth1 InputsInputs

Max Depth1 Max Depth1 OutputsOutputs

Max Depth2 Max Depth2 InputsInputs

Max Depth2 Max Depth2 OutputsOutputs

PressureCalc: case X=0; PressureCalc: case X=0; Y=0Y=0

PressureCalc: 2PressureCalc: 2ndnd set of inputs set of inputs x=0,y=0x=0,y=0

PressureCalc outputs: x=0, PressureCalc outputs: x=0, y=0y=0

PressureCalc 2PressureCalc 2ndnd set of outputs: x=0, set of outputs: x=0, y=0y=0

PressureCalc: x=0 PressureCalc: x=0 y=1y=1

PressureCalc: 2PressureCalc: 2ndnd set of inputs - x=0 set of inputs - x=0 y=1y=1

PressureCalc Outputs: x=0, PressureCalc Outputs: x=0, y=1y=1

PressureCalc 2PressureCalc 2ndnd set of Outputs: x=0, set of Outputs: x=0, y=1y=1

PressureCalc: x=1, y=0PressureCalc: x=1, y=0

PressureCalc: 2PressureCalc: 2ndnd set of x=1, y=0 set of x=1, y=0

PressureCalc Outputs: x=1,y=0PressureCalc Outputs: x=1,y=0

PressureCalc 2PressureCalc 2ndnd set of Outputs: set of Outputs: x=1,y=0x=1,y=0

PressureCalc: x=1,y=1PressureCalc: x=1,y=1

PressureCalc: 2PressureCalc: 2ndnd set of inputs set of inputs x=1,y=1x=1,y=1

PressureCalc Outputs: PressureCalc Outputs: x=1,y=1x=1,y=1

PressureCalc 2PressureCalc 2ndnd set of Outputs: set of Outputs: x=1,y=1x=1,y=1

SafetyWatchSafetyWatch

Clock SpeedClock Speed• Critical Path – From Critical Path – From

the depth input the depth input through through pressureCalc, then pressureCalc, then through through safetywatch, and safetywatch, and out to the out to the safetywatch output safetywatch output signalsignal

• Estimated Final Estimated Final Clock Speed 1HzClock Speed 1Hz

Critical Path LayoutCritical Path Layout

Spice glitchSpice glitch• **error**: only 1 connection at node 29:318**error**: only 1 connection at node 29:318• Correction: a floating unconnected wire in the Correction: a floating unconnected wire in the

designdesign

Power ConsumptionPower Consumption• Strategy to test power consumption – Strategy to test power consumption –

test the effects of several different test the effects of several different power levels on the module in order power levels on the module in order to find the lowest at which it still to find the lowest at which it still works.works.

• Also, we want to see if making any Also, we want to see if making any optimizations to the layout to optimizations to the layout to decrease power consumption decrease power consumption

Questions?Questions?

*Kavita Arora (M3-1) Lisa Gentry (M3-2) Steven Wasik (M3-3) Karolina Werner (M3-4)

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