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7/28/2019 Lab05 Lecture
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Multiplexer,
Encoder andDecoder
Lab 05Prepared By: Rakesh Mahto
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Objective Basic of Multiplexer
Basic of Decoder
Basic of Encoder
VHDL Code for Decoder
VHDL Code for Encoder
Using Components in VHDL
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MultiplexerInput S1 S0 B
A3
A2
A1
Output
B
0 0 A0
0 1 A11 0 A2
1 1 A3
A0
case S isS1 S0
VHDL
Code
when “00” => B <=A(0);
when “01” => B <=A(1);
when “10” => B <=A(2);
when others => B <=A(3);
end case;
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Decoder
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Decoder
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Encoder An encoder performs the inverse function of a
decoder. If input yi is 1 and the other inputs are 0,then abc outputs represent a binary number
equal to i.
For example, if y3 = 1, then abc = 011.
If more than one input is 1, the highest numberedinput determines the output.
An extra output, d, is 1 if any input is 1, otherwise d is0. This signal is needed to distinguish the case of all 0inputs from the case where only y0 is 1.
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8-to-3 Priority Coder
y0 y1 y2 y3 y4 y5 y6 y7 a b c d
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1X 1 0 0 0 0 0 0 0 0 1 1
X X 1 0 0 0 0 0 0 1 0 1
X X X 1 0 0 0 0 0 1 1 1
X X X X 1 0 0 0 1 0 0 1
X X X X X 1 0 0 1 0 1 1
X X X X X X 1 0 1 1 0 1X X X X X X X 1 1 1 1 1
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VHDL code for decoder
process (I)begin
case I iswhen "00" => O <= "0001";when "01" => O <= "0010";when "10" => O <= "0100";when "11" => O <= "1000";when others => O <= "XXXX";
end case;
end process;
Note: Input andoutput areconsidered asStd_Logic_Vector
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VHDL code for encoder
entity prio_encoder42 is port(r: in std_logic_vector(3 downto 0);
code: out std_logic_vector(1 downto 0);
active: out std_logic
); end prio_encoder42;
architecture cond_arch of prio_encoder42 isbegin
code <= "11" when (r(3)=’1’) else
"10" when (r(2)=’1’) else"01" when (r(1)=’1’) else"00";
active <= r(3) or r(2) or r(1) or r(0);end cond_arch;
input Output
r code active
1XXX 11 1
01XX 10 1
001X 01 1
0001 00 1
0000 00 0
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Component Declarationcomponent component_namegeneric(
generic_declaration;
generic_declaration;…………
);
Port(
port_declaration;
port_declaration;……….
);
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Components in VHDLarchitecture xor_arch of even_detector is
signal odd: std_logic;begin
even <= notodd <= a(2) xor a(1) xor a(0);end xor_arch;
Courtesy: Dr. James Plusquellic
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Continue…
Courtesy: Dr. James Plusquellic
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architecture str_arch of even_detector is component xor2-- declaration for xor gateport( i1, i2: in std_logic; o1:out std_logic); end component;component not1 -- declaration for
inverter port(i1: in std_logic;o1: out std_logic); end component;signal sig1,sig2: std_logic;
begin
-- instantiation of the 1st xor instance unit1: xor2
port map (i1 => a(0), i2 => a(1), o1 => sig1);
-- instantiation of the 2nd xor instance unit2: xor2
port map (i1 => a(2), i2 => sig1, o1 => sig2);
---instantiation of inverter unit3: not1
port map (i1 => sig2, o1 => even);
end str_arch;
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Reference Pong P. Chu, “ RTL Hardware Design Using VHDL”.
Charles H. Roth Jr., Larry L. Kinney, “Fundamentals of
Logic Design”.