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UC Berkeley EE241 B. Nikolić
EE241 - Spring 2001Advanced Digital Integrated Circuits
Lecture 23Clock Distribution and Generation
UC Berkeley EE241 B. Nikolić
Reading� Chapter 13, Clock Distribution by Bailey� Chapter 12, PLLs and DLLs by Maneatis
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Clock Uncertainty� Clock skew (spatial uncertainty)
» Systematic» Random
� Clock jitter (temporal uncertainty)» Short term: cycle-to-cycle changes
UC Berkeley EE241 B. Nikolić
Clock Distribution
Tree Common, e.g. IBM S/390
Clock grid
DEC Alpha
Length-matched Serpentines
Intel P6
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Final Stage: Tree vs. Grid
Courtesy of IEEE Press, New York. 2000
RC-matched Tree Grid
UC Berkeley EE241 B. Nikolić
PredriverBinary tree H - tree
X - treeArbitrary matched tree
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Clock Distribution
CLOCK
H-Tree Network
Observe: Only Relative Skew is Important
Example:PowerPC 603Gerosa, JSSC 12/94
UC Berkeley EE241 B. Nikolić
Clock Network with Distributed Buffering
Module
Module
Module
Module
Module
Module
CLOCK
main clock driver
secondary clock drivers
Reduces absolute delay, and makes Power-Down easierSensitive to variations in Buffer Delay
Local Area
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Example IBM S/390
Clock skew
Webb, JSSC 11/97
UC Berkeley EE241 B. Nikolić
Clock Tree Delays
Restle, VLSI’98
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IR Emission Images
Centralbuffer
Clockrepeaters
Sectorbuffers
Localclocks
Sanda, ISSCC’99
UC Berkeley EE241 B. Nikolić
Example: DEC Alpha 21164
Clock Drivers
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Clock Skew in Alpha Processor
UC Berkeley EE241 B. Nikolić
DEC Alpha Evolution
Clock driver placements
21064 21164 21164
Gronowski, JSSC 5/98
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Clock Skews
2106421164
21264
UC Berkeley EE241 B. Nikolić
Hybrid Grid
DEC Alpha 21264Bailey JSSC 11/98
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Alpha 21264
UC Berkeley EE241 B. Nikolić
Alpha 21264 GridsGlobal clock Major clock grids
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Data-Dependent Gate Loading
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Multi-GHz Clock Networks
http://www.research.ibm.com/people/r/restle/MGHz.html
Phillip Restle, IBM Research
IEEE SSCTC Workshop on Design for Multi-GigaHertz Processors,
San Fransico, Feb. 7, 2000
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Clock Generation
PhaseDet
ChargePump
FilterDL
PD CP VCO÷N
Delay-Locked Loop (Delay Line Based)
Phase-Locked Loop (VCO-Based)
U
D
U
D
fREF
fO
fO
fREF
Filter
UC Berkeley EE241 B. Nikolić
Phase-Locked Loop Based Clock Generator
Phasedetector
Chargepump
Up
Down
Loopfilter
VCO
Clock decode &
buffer
Divide byN
Reference clock
Localclock
φ1 φ2 ...
Vcontr
Acts also as Clock Multiplier
Up
Down
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Loop Components� Phase Comparator
» Produces UP/DN pulses corresponding to phase difference� Charge Pump
» Sources/sinks current for duration of UP/DN pulses� Loop Filter
» Integrates current to produce control voltage� Voltage-Controlled Delay Line
» Changes delay proportionally to voltage� Voltage-Controlled Oscillator
» Generates frequency proportional to control voltage
UC Berkeley EE241 B. Nikolić
DLL Locking
Courtesy of IEEE Press, New York. 2000
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PLL Jitter
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Clock Deskewing
Geannopoulos, ISSCC’98
Two clock spines, two DLLs, and a PD that controls them
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Clock Ring
Shibayama, ISSCC’98
Clocks routed in parallel,opposite directionsLCG aligns to the middle
UC Berkeley EE241 B. Nikolić
Synchronous Distributed Oscillators
Mizuno, ISSCC’98
VCOs
# of nearest neighbors
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Distributed PLLs
Gutnik, ISSCC’2000
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Intel ItaniumTM
Rusu,ISSCC’2000
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Intel ItaniumTM