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1Ken Wyllie, CERN LHCC, 12th March 2013
LHCb Upgrade Electronics
Status
On behalf of the LHCb collaboration
LHCC, 12th March 20132Ken Wyllie, CERN
Outline
Architecture review(s)
Overview of sub-detectors
Overview of common electronics
Conclusions
LHCC, 12th March 20133Ken Wyllie, CERN
Ken Wyllie, CERN 3
HLT
Current
HLT++
Upgrade
1MHzeventrate
40MHzeventrate
Readout Supervisor
L0 Hardware Trigger
Readout Supervisor
Low-level Trigger
50 Tb/s
Upgrade Architecture
LHCC, 12th March 20134Ken Wyllie, CERN
Architecture Review
TELL40
SOL40
LHCC, 12th March 20135Ken Wyllie, CERN
Review summary 1
Agenda (5/12/12) + Review Report:
https://indico.cern.ch/conferenceDisplay.py?confId=212204
Many thanks to our external reviewers:
• Alex Kluge (NA62, ALICE)• Philippe Farthouat (ATLAS)• Jorgen Christiansen (PH-ESE)
Presentations on: 1. Front-end & Back-end2. Timing & Fast Controls3. Expt. Control System4. DAQ-interface5. Infrastructure
LHCC, 12th March 20136Ken Wyllie, CERN
Positive feedback from reviewers: ‘NO SHOWSTOPPERS’-------------------------------------------------------------------------------Specific points on:
• Obsolescence
• Buffering on TELL40
• TELL40 firmware organisation
• Using Cu-links Tell40 <-> DAQ
• Tight schedule of ASICs-------------------------------------------------------------------------------Updated specifications note: LHCb-PUB-2011-011
Review summary 2
‘old’ systems under review
buffering being implemented
firmware coordination startedworkshop
in April
links under study with CERN & contractors
manpower + stronger collaboration
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Review of architecture implementation proposed by each sub-detector
• check feasibility
• check all architecture features included
• ideas from external reviewers
• prepare solid ideas for TDR
Specific mandate to 2 external reviewersDocumentation prepared in advance by sub-detectors
Sub-detector Architecture Reviews in 2013
Outer Tracker 6th March Upstream Tracker October
Calorimeter 12th June VeLo To be confirmed
RICH September SciFi/Inner Tracker To be confirmed
Muon October
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Sub-detectors: VeLo + Si trackers
VeLo:
Timepix3 submission imminent
Precursor to Velopix: design to start immediately
TOTTime of Arrival
Q(t)
clock
timeDiscr. out
thr
SALT chip (UT, IT, VeLo-strips)
Front-end + ADC (6-bits):
prototypes submitted
shaper5pF – 45pF
0ns 25 50 75
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Sub-detectors: Trackers
Outer Tracker:TDC in FPGA on prototype module
Also test of:DC-DC convertorsoptical link
SciFi:PACIFIC chip: design started.Specific issues with signal shape
ADC
LHCC, 12th March 201310Ken Wyllie, CERN
Sub-detectors: Particle-IDRICHPrototyping with existing or new chip (Maroc/Claro) connected to MaPMT
CalorimeterNew chip ICECAL:Tested with prototype digital module
MuonNew proposal to re-build ‘off-detector’ modules (obsolescence)
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Common Electronics Status 1
Common Electronics
LHCC, 12th March 201312Ken Wyllie, CERN
We rely HEAVILY on ‘White Paper’ projects (CERN-PH):
• GBT chipset 15,000 pieces• Versatile Link 9,000 pieces• DC-DC power convertors few 1000 pieces
Common Electronics Status 2
GBTX chip layout
Versatile link dual-transmitter
DC-DC convertor
LHCC, 12th March 201313Ken Wyllie, CERN
TELL40: Significant progress
AMC40 available soon for usersbuffering to be implemented
ATCA40: 1st prototype under test
ATCA infrastructurehardware investigationsoftware for control/monitoring
Firmware organisation Workshop at CERN 9/10 AprilALL sub-detectors will be present
formattingbuffering etc etc
Common Electronics Status 3
LHCC, 12th March 201314Ken Wyllie, CERN
Proposal to transmit detector data directly to surface (TELL40s)
Technically feasible?Tested 400m single fibre with VL
+ Tell40-AMC: OKHigh quality fibre: expensive…….Try lower grade + 12-way ribbon
Financially feasible?Discuss with companies:• Procurement• Installation• Testing
Optical fibres
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ConclusionElectronics architecture blessed by reviewersClear guidelines for sub-detector implementation
Already huge progress by sub-projects
2013 is a crucial year:
Manpower must increase
Detector requirements must be clear to allow good electronics design
- critical items are ASIC designs