LnA Design_group5

transcript

Design of 60 GHz Receiver in

Team 5:

Hao Wang

Ming Ding

Mayur Sarode

Assignment

Goals:

• Use 57 to 64 GHz unlicensed band

• Over 1 Gbps of bit rate at a distance of 10 m

• Cost <10 euro's

• Robust receiver

Challenges:

• Use latest CMOS technology (65nm - 45 nm)

• Selecting channel BW, modulation

• Specifications of the Digital part of the system

/ name of department PAGE 130-5-2010

Evaluating the Link Budget

Contribution Running total

TX power +10dBm 10dBm

TX antenna gain 10dB 20dBm

Path loss over 10m -68.1188dBm -48.1188dBm

Rx antenna gain 10dB -38.1188dBm

Background noise -174dBm/Hz -174dBm/Hz

Noise BW(3Ghz) +94.7712 -79.2288dBm

Noise figure of RX +10dB -69.2288dBm

SNR at output -38.1188-(-69.2288)=31.11

Required SNR 10dB

System margin 21dB

Oxygen absorption can be omitted here

Path loss more complicated

Bit rate calculation

2*log (1 ) 14.863C BW SNR

We use 10 Gbps

We use 16-QAM modulation, which

The required Bandwidth

12Gbps/4b=3GHz

System Specification

Specifications achieved unit

Technology 45-130 65 nm

Supply Power - 1.2 V

Power <1000 39.4296 mW

cost <10 5.4 euro

Noise Figure 10 1.93 dB

RF frequency 57-64 60.91 GHz

LO frequency 55-64 57.91 GHz

IF frequency 3 3 GHz

Bond wire:1nH/mm

Bond pad~ 100 fF

Choice of Architecture(1)

To design a Low noise amplifier, Mixer and the oscillator

Low IF architecture was selected.

Monolithic integration

LNA matching

LPF filter

LO leakage

Sensitive to noise

Gain and phase match

Choice of Architecture(2)

Antennas

• Omnidirectional antennas provide limited gain and bit rate

• Using directional and array of antennas to meet the requirements

• Use of phase shifters to improve SNR of a receiver

• It reduces multipath propagation

• FiltersLow pass filter at the output mixer

The CMOS technology

We choose 65 nm for our design

Trade off between design bottleneck and benefits of scaling

Advantages

Higher speed, higher integration

Challenges

• Increasing leakage

• Reduction in voltage supply

• Process variability

• Parasitic effects and impedance matching

System performance

Noise Figure IIP3 Gain SNR Power

consumed

1.425dB -24.55 dB 21.521dB ????? 39.4296mW

New System Performance

Figure(dB)

IIP3(dB) Gain(dB) SNR Power

consumed

1.3971 -14.42 17.768 ???? 52.79

LOW NOISE AMPLIFIER

DESIGN

Survey of LNA’s

Paper CMOS

Supply

(volt)

topology specifications

60 GHz compact

LNA in 65 nm

65 1.2 3 stage single

ended topology

Center

Frequency=57 GHz

Gain=19.1

NF=5.5 dB

A 60GHz Low-

Noise High-

Linearity Receiver

Front-End Design

90 1.2 Single stage

cascode

NF=9.6,

IP3=-14

gain =10 dB

A 60-GHz CMOS

Receiver Front-End

130 1.2 Common gate

topology

Voltage gain:28 dB

NF:12.5,

Power :9mw

60-GHz Receiver

and Transmitter

Front-Ends in 65-

nm CMOS

65n 1.2 5 stage Cascode

topology

20 dB gain

Choice of topology

• Choice between common gate,cascode and common

source

In this a assignment a combination of cascode and common source amplifier is used

Design of the circuit

/Courtesy:LNA-ESD co design for fully integrated CMOS wireless receiversPAGE 1330-5-2010

Passive and active component

specifications

Length=0.065e-6 m

Ft=190MHz

These formula are based on the short channel model of CMOS

Design of the second Stage

•C1 is taken as a bond pad capacitance

•L1 is the bond wire used for output matching

•CL is designed by

•Ld and the source inductance of M1 is

designed to maximize gain.

•RL is designed for a quality factor of 10

Design of circuit (2)

• Biasing of CMOS with a current mirror (1.72mA)

• Reduces channel length modulation effect

WIout L

L•Reduction in noise finger with number of fingers

•ESD protection at the gate

•Input and output bond pad capacitance

•Noise in the power supply lines

•Input /output matching

Components specifications

Parameter Designed Values Optimized Values

Width 9.954 um 10 um

Ls(for Ft=190 GHz) 4.18e-11 H 3.35e-11 H

Lg 5.55e-10 H 2.75e-10 H

Ld 7.063e-12 H 4e-10 H

CL 8.74e-14 F 8.79e-14 F

RL 303.479 ohm 303.479 ohm

Performance(1)

Performance(2)

Performance(3)

1dB compression

point= -20 dBm

K>1 for the 60Ghz

Performance

Specifications

RF_power IP3in IP3out_upper IP3out_lower

-12 -12.437 7.369 7.282

1st and 3rd order spectrums

LNA achieved specifications

Specifications

S(2,1) (power again) 19.25 dB

Voltage gain 18.54 dB

Third order intercept(IIP3) -12 dBm

Noise figure 1.206 dB

1 dB compression point -20dBm

Center frequency 60.91 GHz

Power dissipation 31.03 mW

Future Developments

• Replacing inductors with Microstrip transmission lines, coplanar

waveguides

• Resistance and Inductance of interconnects

• Effects of variation in temperature

• Effect of the substrate

Corrections made to the LNA

• Biasing of the output stage. The output stage was biased with a

resitor of 10K ohm from the drain to the source.

New performance(1):Noise Figure

•Noise figure

New performance(2): S parameters

New performance(3): 1 dB compression

point and stability

New Performance(3):Input output

matching

New performance(4):IIP3

RF_power IP3in IP3out_upper IP3out_lower

-12 -12.621 7.185 7.284

New Specifications

Specifications

S(2,1) (power again) 16.25 dB

Voltage gain 14.925 dB

Third order intercept(IIP3) -12.621 dBm

Noise figure 1.206 dB

1 dB compression point -19dBm

Center frequency 60.91 GHz

Power dissipation 44.4mW

LnA Design_group5

Education