MARTE/CCSL,TimeSquare & K-PassaA design platform using MoCCs for

embedded model-based engineering

C. André, J. Boucaron, A. Coadou, J. DeAntoni, B. Ferrero, F. Mallet, R. de Simone

AOSTE Project INRIA/I3SSophia Antipolis, France

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Context

Modeling environments for real-time embedded and distributed systems

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Context

Modeling environments for real-time embedded and distributed systems

Conceptual diagrammatic representations Structural

Components / interactions Dynamics/Behavior

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Context

Modeling environments for real-time embedded and distributed systems

Conceptual diagrammatic representations Structural

Components / interactions Dynamics/Behavior of individual

components State-based control flow Activity-based data flow Constrained programs with “same”

expressivity

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Context

Modeling environments for real-time embedded and distributed systems

Conceptual diagrammatic representations Structural

Components / interactions Dynamics/Behavior of individual components

State-based control flow Activity-based data flow Constrained programs with “same” expressivity

Dynamics/Behavior of system results from combining component behaviors

according to structure

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Example of architecture modeling

Platform-Based Software Design Flow for Heterogeneous MPSoCK. POPOVICI, X. GUERIN, F. ROUSSEAU, P. S. PAOLUCCI, A. JERRAYAACM Transactions on Embedded Computing Systems, Vol. 7, No. 4, Article 39, Publication date: July 2008.

Structure

Behavior

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Example of architecture modeling

Platform-Based Software Design Flow for Heterogeneous MPSoCK. POPOVICI, X. GUERIN, F. ROUSSEAU, P. S. PAOLUCCI, A. JERRAYAACM Transactions on Embedded Computing Systems, Vol. 7, No. 4, Article 39, Publication date: July 2008.

Structure

Behavior

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Example of architecture modeling

Platform-Based Software Design Flow for Heterogeneous MPSoCK. POPOVICI, X. GUERIN, F. ROUSSEAU, P. S. PAOLUCCI, A. JERRAYAACM Transactions on Embedded Computing Systems, Vol. 7, No. 4, Article 39, Publication date: July 2008.

Structure

Behavior

Elaboration phase (SystemC)

Simulation

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Traditional component approach

Structure Black-box + Interfaces (Ports, Data Types)

Behavioral abstraction Messages + possibly period and

performance requirements

What we find missing: Detailed definition of timing and

synchronization properties Communication protocol requirements

This missing information is often deported elsewhere

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Traditional component approach

Structure Black-box + Interfaces (Ports, Data Types)

Behavioral abstraction Messages + possibly period and performance

requirements

What we find missing: Detailed definition of timing and

synchronization properties Communication protocol requirements

This missing information is often deported elsewhere

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Time & Semantics

Logical functional time Functional: sequence of

reaction steps Multiple times (local /

global) Synchronization

primitives → constraints between local activation times

Synthesis / Compilation

Process networks (SDF), synchronous reactive formalisms, statecharts

“physical” time Extra functional

Single time (total order)

Timing constraints to be satisfied at execution

Simulation semantics possibly different from synthesis

UML, SystemC

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Time & Semantics

Logical functional time Functional: sequence of

reaction steps Multiple times (local /

global) Synchronization

primitives → constraints between local activation times

Synthesis / Compilation

Process networks (SDF), synchronous reactive formalisms, statecharts

“physical” time Extra functional

Single time (total order)

Timing constraints to be satisfied at execution

Simulation semantics possibly different from synthesis

UML, SystemCHDLs

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Semantics

Logical functional time Functional: sequence of

reaction steps Multiple times (local /

global) Synchronization

primitives → constraints between local activation times

Synthesis / Compilation

Process networks (SDF), synchronous reactive formalisms, statecharts

“physical” time Extra functional

Single time (total order)

Timing constraints to be satisfied at execution

Simulation semantics possibly different from synthesis

UML, SystemC

Our choice

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MARTE: Time model and CCSL

MARTE = Modeling and Analysis of Real-Time and Embedded systems OMG UML profile (adopted June 2009) Time subprofile (defined by us)

Rich but well-defined variety of time notions (logical/physical, discrete/dense, …)

Clocks can be explicitly attached to most UML model elements → timed semantics

Clock Constraint Specification Language (CCSL)

Various constraints on clocks (synchronous, asynchronous, mixed)

Precise formal semantics

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Why CCSL?

Polychronous system modeling Specification of sophisticated

synchronizations Notation to describe semantic relations

between timed behaviors (illustrated below)

Means to define formally timed Models of Computations and Communications (MoCCs)

Akin to Tagged Systems (Lee & Sangiovanni-Vincentelli)

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Why CCSL?

Means to define formally timed Models of Computations and Communications (MoCCs) In the sequel, we translate a MoCC as UML

models + CCSL specifications The chosen MoCC is SDF (weighted event

graphs) models

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Synchronous DataFlow

Nodes are called actors Input/Output have a weight

(Number of data samples consumed/produced)

Arcs have a delay

SDF Meta-model

incoming

dest

src

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Synchronous DataFlow

Actor enabling = each incoming arc carries at least weight tokens

Actor execution = atomic consumption/production of tokens by an enabled actor i.e., consume weight tokens on each

incoming arcs and produce weight tokens on each outgoing arc

Delay is an initial token load on an arc.

SDF firing rules:

How can CCSL express this semantics?

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SDF Example

A A BA AC C

BStatic schedule:

Evolutions of the model

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How to model SDF graphs in UML ?

Is that compatible with the UML semantics ?

CCSL makes the semantics explicit … … within the model

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SDF semantics with CCSL (1/2)

SDF Actor A

Token T

Input i

Output o

CCSL Clock A;

Clock write, read; Var delay:int;

Var weight:int;

Var weight:int;

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SDF semantics with CCSL (2/2)

SDF

CCSL

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Example

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TimeSquare

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AOSTE’s Tools

TimeSquare Software environment dedicated to the

Specification of CCSL constraints Resolution of CCSL constraints Simulation and generation of trace model Animation of UML models Exploration of augmented timing diagrams

K-Passa Computation of static schedules for specific MoCCs

Marked Graphs, Synchronous DataFlow, Latency-Insensitive Designs, K-periodical Routed Graphs

Analysis (deadlock freeness, safety) Optimization (latency, throughput, interconnect buffer size) Code generation (stand-alone simulator)

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K-Passa

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Tool download

http://www-sop.inria.fr/aoste/

Thank you All