Post on 13-Jul-2020
transcript
MAX10 - Architecture
Last updated 7/11/20
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FPGA MAX10
These slides review Intel/Altera MAX10 architecture
Upon completion: You should be able to describe the MAX10 architecture and each of the major
subsystems
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FPGA MAX10
• Top Level View
Src: MAX 10 Device Handbook
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FPGA MAX10
• Top Level View• 10M50DAF484C7G
Src: MAX 10 Device Overview
10M 50 DA F 484 C 7 G
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FPGA MAX10
• Top Level View• 10M50DAF484C7G
Src: MAX 10 Device Overview
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FPGA MAX10
• Logic Array• Array of Logic Elements (LEs) – 50K LEs
Src: MAX 10 Device Handbook
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FPGA MAX10
• Logic Elements• 1 LE can have both an asynchronous and synchronous
path
Src: MAX 10 Device Handbook
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FPGA MAX10
• Logic Elements• Look-Up Table (LUT)• Multiplexor
b15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0
Inp
ut
1In
pu
t 2
Inp
ut
3In
pu
t 4
LUT Mask Output
4 3 2 1 OUT
0 0 0 0 b0
0 0 0 1 b1
0 0 1 0 b2
0 0 1 1 b3
0 1 0 0 b4
0 1 0 1 b5
0 1 1 0 b6
0 1 1 1 b7
1 0 0 0 b8
1 0 0 1 b9
1 0 1 0 b10
1 0 1 1 b11
1 1 0 0 b12
1 1 0 1 b13
1 1 1 0 b14
1 1 1 1 b15
Inputs
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FPGA MAX10
• Logic Elements• Look-Up Table (LUT)
(In1 | In2) & (In2 | In3) & !(In4)
4 3 2 1 OUT
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
Inputs
0000000011101100
Inp
ut
1In
pu
t 2
Inp
ut
3In
pu
t 4
Out
0000000011101100
1 1 0 0
1
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FPGA MAX10
• Logic Array• Normal Mode
Src: MAX 10 Device Handbook
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FPGA MAX10
• Logic Array• Arithmetic Mode• 1 LUT can implement an adder
Src: MAX 10 Device Handbook
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FPGA MAX10
• Logic Array• Arithmetic Mode• 3 input LUTs
In 1
In 2
In 3
In 4
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
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FPGA MAX10
• Logic Array Block (LAB)• 16 LEs
• LAB control signals
• LE carry chains
• Register chains
• Local interconnect
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FPGA MAX10
• LAB
Src: MAX 10 Device Handbook
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FPGA MAX10
• Multiple Levels of Interconnect• Local Interconnect
Src: MAX 10 Device Handbook
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FPGA MAX10
• Multiple Levels of Interconnect• Direct Link Interconnect
Src: MAX 10 Device Handbook
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FPGA MAX10
• Multiple Levels of Interconnect• Global Interconnect - direct
Src: MAX 10 Device Handbook
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FPGA MAX10
• Multiple Levels of Interconnect• Global Interconnect - indirect
Src: MAX 10 Device Handbook
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FPGA MAX10
• Multiple Levels of Interconnect• Row/Column Interconnect
Src: MAX 10 Device Handbook
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FPGA MAX10
• Additional Fixed Blocks - Clocks
Src: MAX 10 Device Handbook
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FPGA MAX10
• Additional Fixed Blocks – Clocks• PLL
Src: MAX 10 Device Handbook
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FPGA MAX10
• Additional Fixed Blocks - Clocks• PLL locations
Src: MAX 10 Device Handbook
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FPGA MAX10
• Additional Fixed Blocks - Memory• M9K Block• 8192 RAM bits (9216 including parity)
• 284-MHz performance
• True dual-port memory
• Simple dual-port memory
• Single-port memory
• Byte enable
• Parity bits
• Shift register
• FIFO buffer
• ROM
• Various clock modes
• Address clock enable
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FPGA MAX10
• Additional Fixed Blocks - Multiplier• 144 - 18 x 18 multipliers
• Can be configured as 2 – 9 x 9 multipliers
Src: MAX 10 Device Handbook
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FPGA MAX10
• Additional Fixed Blocks - Multiplier• Configured as 2 – 9 x 9 multipliers
Src: MAX 10 Device Handbook
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FPGA MAX10
• Additional Fixed Blocks - ADC• 12 bit
• 1Mbps
Src: MAX 10 Device Handbook
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FPGA MAX10
• Additional Fixed Blocks - User Flash• 2 user partitions
• 5888Kb total memory
Src: MAX 10 Device Handbook
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FPGA MAX10
• Additional Fixed Blocks - IO
Src: MAX 10 Device Handbook
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FPGA MAX10
• Additional Fixed Blocks - IO
Src: Max 10 Device Handbook
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FPGA MAX10
• Additional Fixed Blocks - IO
Src: Max 10 Device Handbook
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FPGA MAX10
• Dual Power Supply
Src: MAX 10 Device Handbook
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FPGA MAX10
• FPGA – programmable• JTAG Programming Configurations• Load programming information (xx.sof file)
• Directly into the Configuration RAM via the JTAG interface
• Configuration FLASH holds the default program
Src: MAX 10 FPGA Configuration Guide
xx.sof fileSRAM Object File
ConfigurationRAM