Post on 16-Jan-2016
transcript
NAS
Design & Test Design & Test Challenges & Solutions Challenges & Solutions
in Nanometer Erain Nanometer Era
byby
Yervant ZorianYervant Zorian
Vice President & Chief ScientistVice President & Chief Scientist
Virage Logic CorporationVirage Logic Corporation
NAS
AgendaAgenda
• Market RequirementsMarket Requirements
• Technology Trends & ChallengesTechnology Trends & Challenges
• Design & Test SolutionsDesign & Test Solutions
• Continuous Technology Innovation Continuous Technology Innovation
• ConclusionsConclusions
NAS
1947- BINAC
1944 - ENIAC – programming and testing Size- 1 x 2.1 x 33 meters, 140 square meter, contains 19.000 vacuum tubes, 1500 relays, and uses 180 kWh, its volume was 100 m3 and weighed appr. 30.000 kilo
1952 UNIVAC
NAS
Integrated Applications Integrated Applications Drives Cost Reduction/Speeds Market AdoptionDrives Cost Reduction/Speeds Market Adoption
MSM5500 1xEV-DO Commercial Device (2003) MSM6100 1X Commercial Device (2005)
Power Mgmt.
Base Band with integrated co-processorBase Band with integrated co-processorBase BandBase Band
Memory MemoryPower Mgmt.
Smaller geometries allow us to have more features in smaller footprints.
180nm 130nm
NAS
Integrated Applications Integrated Applications Drives Cost Reduction/Speeds Market AdoptionDrives Cost Reduction/Speeds Market Adoption
QSC6030 1x CDMA200 Commercial Device (2006)
Smaller geometries and integration allow us to have more features in smaller footprints.
… Moving to single chip phone!
Memory
QSC6030 Digital Modem & µProc, BBA, RF & PMICQSC6030 Digital Modem & µProc, BBA, RF & PMIC
RF
NAS
How to produce this level of integration?How to produce this level of integration?• The next generation multimedia terminal supports :The next generation multimedia terminal supports :
– high-bandwidth wireless communication ( ~7mbs) ;high-bandwidth wireless communication ( ~7mbs) ;– Multiple modems (Blue tooth, HSUPA, 1x, GSM, WiFi etc), Multiple modems (Blue tooth, HSUPA, 1x, GSM, WiFi etc), – Bi-directional motion video; Bi-directional motion video; – High-quality audio(MPEG) , High-quality audio(MPEG) , – GraphicsGraphics– Low power Low power – Integration of RF/ Memory /Analog Integration of RF/ Memory /Analog – Speech, and pen-based inputSpeech, and pen-based input– Full text and graphics input Full text and graphics input – HD TV on DemandHD TV on Demand– Solar chargerSolar charger– Heads up display / solar insensitive displayHeads up display / solar insensitive display– 100% input mapping accuracy100% input mapping accuracy– Full function word processor / spreadsheets, and editingFull function word processor / spreadsheets, and editing
MemoryMemory
Micro-Micro-ProcessorProcessor
GSM/GPRSGSM/GPRS
DSPDSPGPSGPS
3D Graphics3D Graphics
VideoVideo
AudioAudio
ImagingImaging
CDMACDMA
DSPDSP
NAS
Technology TrendsTechnology Trends• Increased number of cores Increased number of cores
• Megabits of embedded RAMMegabits of embedded RAM
• Increasing timing domains and higer frequenciesIncreasing timing domains and higer frequencies
• More and more power domains and (low) power modesMore and more power domains and (low) power modes
• Zero PPM qualityZero PPM quality
• Exploding data volumesExploding data volumes
• New process material and more layersNew process material and more layers
• Intra / Inter die variationsIntra / Inter die variations
• Gigabit I/OGigabit I/O
NAS
Technology ProductionTechnology Production
• Growth in technology user community continuesGrowth in technology user community continues
• Most complex technologies for childrenMost complex technologies for children
• Technology users versus producersTechnology users versus producers
• Research -> Development -> ManufacturingResearch -> Development -> Manufacturing
• Producers were Vertically Integrated Systems Producers were Vertically Integrated Systems
companies companies – AT&T, DEC, IBM, Philips, Siemens, HitachiAT&T, DEC, IBM, Philips, Siemens, Hitachi
NAS
1. Problem: Production Cost Challenges1. Problem: Production Cost Challenges
• Capital expenditure for new fabs is increasing at exponential paceCapital expenditure for new fabs is increasing at exponential pace
[Source: Samsung]
0.40.4
6 inch6 inch 8 inch8 inch 12 inch 12 inch 18 inch18 inch
50K50Kwpwpmm
5.0↑5.0↑
20K20Kwpmwpm20K20K
wpmwpm
30K30Kwpmwpm
2.5 ∼ 2.92.5 ∼ 2.9
0.7∼1.00.7∼1.0
New Fabs CapExNew Fabs CapEx
($B)($B)
* WPM : Wafer per Month [Source: IBS, 2006]
D/RD/R(nm)(nm)
ProcessDevelopmentCost
ProcessRamp-UpCost
130130 9090 6565 4545 3232
1.61.6
1.11.1
0.80.8
0.60.6
0.40.4
($B)($B)
Process Development Process Development CostCost
Process technology development costs are also rising rapidly
ROI Risk
Design complexity and cost increase rapidly in advanced node SOCs
Architecture
Verification
Physical
Validation
9.29.2
18.018.0
46.246.2
[Source: IBS 2006]
Software
Required Revenue> 10x of Design Cost
Design CostDesign Cost
($M)($M)
130130 9090 6565
NAS © 2009 Virage Logic Corporation – COMPANY CONFIDENTIAL
Semiconductor Industry ChallengesDriving Need for PartnershipsSemiconductor Industry ChallengesDriving Need for Partnerships
• Technology ChallengesTechnology Challenges– Rapidly shrinking life cyclesRapidly shrinking life cycles– Increasing technology complexityIncreasing technology complexity
• Business ChallengesBusiness Challenges– Rising NRE and R&D costsRising NRE and R&D costs– Shrinking end-user/product pricesShrinking end-user/product prices
• Market ChallengesMarket Challenges– Time-To-Market Time-To-Market – Time-To-VolumeTime-To-Volume– CompetitivenessCompetitiveness
65nm
NRE & R&D Costs
Process Technology Node
180nm 130nm 90nm 45nm
End
Use
r/P
rodu
ct P
rices
SoCs
NR
E &
R&
D C
osts
NAS
Complex Multi-Party RelationshipsEach Party has its Motivations and Interests
PhysicalTools
Libraries &Views
Design Kit.
GDS-II
Wafers
IC IC DESIGNDESIGNHOUSEHOUSE
Front EndTools
Protos
IC’s
Qual
DeBug
SiSiFoundryFoundry
ENGENG
SiSiFoundryFoundryManufManuf......
Si Wafers
IP &Views
DesignKit
TestPartsRules & Models
SystemHouse
LibraryVendor
IPIPVendor
BE CADVendor
FE CADVendor
AssemblyContractor
TestContractor
FA/ DeBugFIB/etc..
1. Disaggregation in Technology Production
Process EDA Design
Design Re-spins
Process EDA Design
Design Re-spins
‘is’ in the future
Speci
alizat
ionDe
pth
‘was’ in the past
Speci
alizat
ionDe
pth
‘was’ in the past
Decreasing Overlap Between Principal DisciplinesDisappearing common language
Source : Tality
• Increasing Specialization – Technology complexity
• Designers driven to higher levels of abstraction – distant from process and test
• Process engineers driven to material, optics, plasma sciences
– Increasing gaps between disciplines• Decreasing ability to communicate in a
common language
• Increasing Business Segregation• IDM or Fabless• IP house or chip house• ATE, systems, validation or verification
– Solving the test equation is only getting harder.
Source : TalitySystem level optimization needed
Systems Design
IC Design
NAS 12
Standardized SolutionsStandardized Solutions
Pre-Integrated test and diagnosis IP into physical IP
External access - use of standard interface, such as \IEEE 1500, IEEE 1149.1
16
NAS
CharacterizationCharacterizationCharacterizationCharacterization
Production Production Ramp UpRamp Up
Production Production Ramp UpRamp Up
Volume Volume FabricationFabrication
Volume Volume FabricationFabrication
Test Test Assembly Assembly PackagingPackaging
Test Test Assembly Assembly PackagingPackaging
In-FieldIn-FieldIn-FieldIn-Field
IP DesignIP DesignIP DesignIP Design
Failure Failure AnalysisAnalysisFailure Failure
AnalysisAnalysis
SoC DesignSoC DesignSoC DesignSoC Design
Disaggregated FlowDisaggregated Flow
NAS
Disaggregated IndustryDisaggregated Industry
• Creation new companies vs existing companiesCreation new companies vs existing companies– Spin-off culture vs start-ups culture creationSpin-off culture vs start-ups culture creation
• Rise of Silicon Valley feeding start-upsRise of Silicon Valley feeding start-ups– Stanford University and Hewlett PackardStanford University and Hewlett Packard– Concentration of Venture Capital FirmsConcentration of Venture Capital Firms– Enabling environment – Legal, banking, accountingEnabling environment – Legal, banking, accounting– International contributors (Asian CEOs)International contributors (Asian CEOs)
• New companies originated from New companies originated from – University labs – HP, Google, Yahoo, Oracle, eBAYUniversity labs – HP, Google, Yahoo, Oracle, eBAY– Large industrial corporations – Intel, Nvidia, Cisco, Large industrial corporations – Intel, Nvidia, Cisco,
SUN, LSI Logic, etc. SUN, LSI Logic, etc.
NAS
Alternate Logic Devices
Manufacturing Development Research
Source: Intel
Si Substrate
Metal Gate
High-kTri-Gate
S
G
D
III-V
S
Carbon Nanotube FET
50 nm
35 nm
30 nm
SiGe S/D
Strained Silicon
SiGe S/D
Strained Silicon
Technology Generation
Technology Generation
20 nm
10 nm
5 nm5 nm
5 nm
Nanowire
90 nm 65 nm 45 nm 32 nm
2003 2005 2007 2009 2011+
2. Trend: Miniaturization Continues 2. Trend: Miniaturization Continues 2. Trend: Miniaturization Continues 2. Trend: Miniaturization Continues
NAS
Moore’s Law Moore’s Law Enabling Significant Enabling Significant Product Opportunities Product Opportunities at Same Costat Same Cost
Better system level power/performance by integrating more functionality on a single die enabled by the increased availability of transistors
NAS
Moore‘s Law on Wide Range of Products Moore‘s Law on Wide Range of Products
Multicore designsHighly parallel designs
SOCuP, DSP, GPS, modems, memory
AMD Quadcore Intel Quadcore
IBM Cell
nVidia Quad SLI
Qualcomm 7600 Xilinx Virtex 5
More and more timing domainsMegabits of embedded RAMMore and more power domains and (low)power modesZero PPM qualityExploding data volumesIntra/ Inter die variationsDC to Gigabit I/O
More Mbytes/ sec = measure of goodness
NAS
2. Problem: Defectivity 2. Problem: Defectivity Miniaturization result in
Finer and denser semiconductor fabrication Increased susceptiblity Increased defectivity Lower manufacturing yield and reliability
Observed as Defect density Realistic Faults Timing problems Transient or Soft Errors
NAS © 2009 Virage Logic Corporation
Silicon QualitySilicon Quality• Enhanced Test algorithms with the knowledge of accurate background patterns provide 100% Enhanced Test algorithms with the knowledge of accurate background patterns provide 100%
fault coverage for comprehensive fault typesfault coverage for comprehensive fault types– New faults types appear at advanced process technologiesNew faults types appear at advanced process technologies
• Resistive faultsResistive faults
• Performance faultsPerformance faults• Bridging faultsBridging faults• Parametric variationParametric variation
– Comprehensive modeling of memory topology required to generate dedicated background Comprehensive modeling of memory topology required to generate dedicated background patterns for fault detectionpatterns for fault detection
– Generic algorithms are not as granular resulting in test escapesGeneric algorithms are not as granular resulting in test escapes
Lack of knowledge of complete scrambling information can lead to up to 30% test escapes
NAS 20
Silicon Debug CycleSilicon Debug Cycle• Need to gather failure data using diagnosis IP and Need to gather failure data using diagnosis IP and
analyze obtained data by off-chip fault localization analyze obtained data by off-chip fault localization methodologies, tools and equipmentmethodologies, tools and equipment
• Leverage same infrastructure IP for test, silicon Leverage same infrastructure IP for test, silicon debug and diagnosisdebug and diagnosis
• Integrated Silicon Debug Solution comprised of - Integrated Silicon Debug Solution comprised of - – Analysis and generation of embedded test & Analysis and generation of embedded test &
diagnosis IPdiagnosis IP– Integration of embedded test & diagnosis IPIntegration of embedded test & diagnosis IP– Creation of yield acceleration data baseCreation of yield acceleration data base– Failure data from diagnosis IP analyzed off-chip Failure data from diagnosis IP analyzed off-chip
for fault localizationfor fault localization
NAS 21
Infrastructure IP for Test and DiagnosisInfrastructure IP for Test and Diagnosis
Hierarchical network of I-IP blocks
Standard interface IEEE 1500 standard
interface between I-IP units
STAR Fuse Box
JTAG
TAP
STAR
JPC
STAR Processor n
6IW 1
STARSTARSRAM SRAM
IW 2
STARASAP
6IW 3
STARSTARRF RF
IW 4
STARASAP
STAR Processor 2
6IW 1
STARSTARSRAM SRAM
IW 3
STARASAP
6IW 4
STARSTARRF RF
IW 6
STARASAP
STAR Processor 1
WRAPPER 1
STARSRAM
WRAPPER 2
STAR SRAM
WRAPPER 3
STARSRAM
WRAPPER 4
STARSRAM
IEE
E1
50
0
SFP
NAS 22
Accelerating Silicon Debug CycleAccelerating Silicon Debug Cycle
SiliconDebug
Tester
Bit Map
Coordinate IdentificationDBDB
SoC w/ ET&R
Vector Generation
Std. formant
NAS 23
Reducing Time to DebugReducing Time to Debug
Allow accurate analysis - Allow accurate analysis -
• Identify defective memoryIdentify defective memory
• Logical bit mappingLogical bit mapping
• Physical bit mappingPhysical bit mapping
• Calculating X-Y coordinatesCalculating X-Y coordinates
• Defect ClassificationDefect Classification
• Fault Localization – root cause identificationFault Localization – root cause identification
• Diagnosis – fault classificationDiagnosis – fault classification
NAS 24
Fault Type Diagnosis of Failed Bit i) Single cell faults (SPF1)
Stuck-at faults (SAF) Stuck-open faults (SOF) Transition faults (TF) Data retention faults (DRF) Read destructive fault Deceptive read destructive fault Incorrect read fault
ii) Two cell faults (SPF2) Inversion coupling fault (CFin) Idempotent coupling fault (CFid) State coupling fault (CFst) Disturb coupling fault (CFds) Incorrect read coupling Fault (CFir) Read destructive coupling fault (CFrd) Deceptive read destructive coupling Fault (CFdrd) Transition coupling fault
iii) Address decoder faults (AF)
NAS 25
Fault ClassificationFault Classification
• Based on diagnostic information collected from tester Based on diagnostic information collected from tester response, it will be possible to determine fault types.response, it will be possible to determine fault types.
Example: March FD
(W0); (R0); (R0, W1, W1, R1); (R1, W0, R0, W1); (R1, W1);
(R1); (R1); (R1, W0, W0, R0); (R0, W1, R1, W0); (R0, W0);
(R0); (R0, W1, W1, R1); (R1); (R1, W0, W0, R0); (R0).
NAS 26
Part of Dictionary of MARCH FD
00110000000110001000<1R1/0/1
>
10000100010000000010<0R0/1/
0>
00111000100111101100<1/0/->
11000111011000010011<0/1/->
R
19
R
18
R
17
R
16
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
Each two pair of Fault signatures do not coincideMARCH FD – Full Diagnosis algorithm
Example: SMS detected errors at (2, 3, 5, 6, 7, 8, 11,15, 16, 17) Read operations then the fault is Stuck-At 0 (<1/0/->).
NAS
3. Trend: Embedded Memory in ICs3. Trend: Embedded Memory in ICs
NAS 28
3. Enhancing Yield via Repair3. Enhancing Yield via Repair
0
10
20
30
40
50
60
70
80
90
100
2.69 5.39 10.78 21.56 43.11 64.67 86.22
% Memory on die
Mem
ory
Yie
ld (
%)
Memory yield (without redundancy)
Memory Yield with redundancy
3 5 11 22 43 65 86
1 Mb 2 Mb 4 Mb 8 Mb 16 Mb 24 Mb 32 Mb
Percent of Memory on die
Width of die in mm 12.00
Height of die in mm 12.00Defect density for logic in # per sq. in. 0.4Defect density for memoryin # per sq. in. 0.8
Process technology 32nm3 5 11 22 43 65 86
NAS
Conventional Manuf. Repair
External Test & Repair Method
Store failed bit map externally in a large capture memory
Use external general purpose redundancy allocation software
Blow fuses using external repair equipment
High cost and silicon area
NAS
I-IP for Single Time Repair
External Memory tester eliminated
External bit map storage eliminated
External redundancy analysis software eliminated
High yield achieved because of integrated solution
• Small
Capture Memory
NAS
I-IP for Multi-Time Repair
External repair equipment eliminated
Overall manufacturing cost reduced
Efficiency of repair increased (PVT corner conditions repaired)
Efficient of area & performance improved
NAS 32
Enhancing Yield via RepairEnhancing Yield via Repair
• Type and amount of redundancyType and amount of redundancy
• Fault detection & location algorithmFault detection & location algorithm
• Redundancy allocation algorithmRedundancy allocation algorithm
• Repair MethodologyRepair Methodology
• Reconfiguration mechanismReconfiguration mechanism
NAS
Repair Efficiency depends on
– Knowledge of memory topology
– Knowledge of process defect history
– Having dedicated algorithms
Redundancy and Repair AllocationRedundancy and Repair Allocation
NAS
4. Problem: Resource Limitation Challenge4. Problem: Resource Limitation Challenge
• Cost of production increasedCost of production increased
• Counterpoint: The San Andreas FaultCounterpoint: The San Andreas Fault
NAS
Globalization in Technology ProductionGlobalization in Technology Production
• New locations around the world New locations around the world – Manufacturing, ex: Mexico, Taiwan, ChinaManufacturing, ex: Mexico, Taiwan, China– Development, ex: India, KoreaDevelopment, ex: India, Korea– Research, ex: Armenia, RussiaResearch, ex: Armenia, Russia
• New trends in global technology productionNew trends in global technology production– Distributed corporate sitesDistributed corporate sites– Outsourcing servicesOutsourcing services– New global start-upsNew global start-ups
NAS
Top 20 Semiconductor Technology Companies Top 20 Semiconductor Technology Companies
2007 Rank
2006 Rank Company
2006 Revenue (Millions)
2007 Revenue (Millions)
Percent Change
1 1 Intel 31,542$ 33,973$ 7.7%2 2 Samsung Electronics 19,842$ 20,137$ 1.5%3 4 Toshiba 10,141$ 12,590$ 24.1%4 3 Texas Instruments 12,600$ 12,172$ -3.4%5 5 STMicroelectronics 9,854$ 9,991$ 1.4%6 7 Hynix 7,865$ 9,614$ 22.2%7 6 Renesas technology 7,900$ 8,137$ 3.0%8 14 Sony 5,129$ 8,040$ 56.8%9 10 NXP 5,894$ 6,038$ 2.4%
10 15 Infineon Technologies 5,119$ 5,864$ 14.6%11 8 AMD 7,506$ 5,792$ -22.8%12 16 Qualcomm 4,529$ 5,603$ 23.7%13 11 NEC Electronics 5,601$ 5,555$ -0.8%14 9 Freescale Semiconductor 5,988$ 5,349$ -10.7%15 13 Micron Technology 5,247$ 4,943$ -5.8%16 12 Qimonda 5,413$ 4,186$ -22.7%17 17 Matsushita Electric 4,022$ 3,946$ -1.9%18 19 Elpida Memory 3,527$ 3,836$ 8.8%19 18 Broadcom 3,668$ 3,731$ 1.7%20 20 Sharp Electronics 3,341$ 3,584$ 7.3%
NAS 37
Global SOC DevelopmentGlobal SOC Development- Flat versus hierarchical design solutions
- Pre-optimized hard IP blocks made reusable
DSPPLL
RF RF RFFlash
SRAM
Processor
Mega Bit SRAMLogic
NAS
5. Trend: SOC/SiP Alternatives5. Trend: SOC/SiP Alternatives
• SOC: System on Chip. Integrate combinations of logic,
processor, SRAM, DSP, A/RF, DRAM, NVM
• SiP: Stacked ICs & Packages
1. Non-TSV– bare die stacking: wirebond, flipchip, embedded die substrate– package stacking: PoP, PiP
2. TSV– via first, via middle, via last
• SOP: System on Package. Integrate passives, power
mgmt, thermal structures, antenna switches, MEMS,
etc.
NAS
SOC/SiP Tradeoffs SOC/SiP Tradeoffs PROPRO CONCON
SOCSOC
High performance, low High performance, low power power if tech optimumif tech optimum
Low cost Low cost if simple if simple processprocess
Smaller Bill Of MaterialsSmaller Bill Of Materials
Chip level miniaturizationChip level miniaturization
IPIP instantiation for each instantiation for each tech node & fabtech node & fab
NRE costNRE cost
Development timeDevelopment time
Complex Complex verification & verification & test test
SiPSiP(without (without TSV)TSV)
Optimum technology Optimum technology for for dissimilar functionsdissimilar functions
Flexible Flexible reusereuse of of componentscomponents
Shorter Shorter Time to MarketTime to Market
Low chip-chip Low chip-chip connectivityconnectivity
Lack of EDA toolsLack of EDA tools
KGD/test planningKGD/test planning
Yield liabilityYield liability
SOC and SiP SOC and SiP are complementary are complementary and co-exist in products and co-exist in products
NAS
Evolution in 3D TechnologiesEvolution in 3D Technologies
LimitationsLimitations– Peripheral bonds onlyPeripheral bonds only– Long wire bonds (high inductance, high Long wire bonds (high inductance, high
crosstalk, low speed interconnect)crosstalk, low speed interconnect)
Limited to low-density Limited to low-density interconnects and with interconnects and with specific I/O pad routingspecific I/O pad routing
Current SiP (non-TSV)Current SiP (non-TSV)
Source: ChipPAC
BenefitsBenefits– Area placementArea placement– Excellent electrical characteristicsExcellent electrical characteristics– High densitiesHigh densities
Orders of magnitude Orders of magnitude higher interconnect higher interconnect densities between diesdensities between dies
TSSTSS
NAS
Packaging scenarios for 3D Stacked DRAMPackaging scenarios for 3D Stacked DRAM
PCB
Logic DDR2 -16bit
PCB
Board
SiP
3D TSS(TSVs)
PCB
PCB
3D-ready DDR2 -xbit
Existing DDR2 -16bit
DDR2 -16bit
Using an existing Using an existing DDR2 dieDDR2 die
Wide Interface Wide Interface DDR2 dieDDR2 die
NAS
Thru Silicon Stacking Thru Silicon Stacking Multi-discipline Challenges & GapsMulti-discipline Challenges & Gaps
• Supply Chain and StandardizationSupply Chain and Standardization
• CostCost• DFT/TestDFT/Test
– test strategy and circuitstest strategy and circuits– KGDKGD– failure analysis techniques failure analysis techniques
• Thermal/Mechanical/ReliabilityThermal/Mechanical/Reliability
• EDA tools and methodologiesEDA tools and methodologies
NAS
6. Application-Specific Challenge6. Application-Specific Challenge
• Application-specific disaggregation of semiconductor Application-specific disaggregation of semiconductor
industry – similar to system housesindustry – similar to system houses– Digital home, enterprise, portable, health, etc. Digital home, enterprise, portable, health, etc.
• Application-specific disaggregation of semiconductor Application-specific disaggregation of semiconductor
supply industrysupply industry– EDA suppliersEDA suppliers– IP providersIP providers– FoundriesFoundries
• Test, diagnostics, yield, reliability requirements for Test, diagnostics, yield, reliability requirements for
each application domaineach application domain
NAS
Portable and Hand-held
Communications and Networking
Graphics andComputing
Consumer
Application-Specific SolutionApplication-Specific Solution
• What is the impact on Design & Test TechnologyWhat is the impact on Design & Test Technology
NAS
Application-Specific YieldApplication-Specific Yield
NAS 46
Disruptive TechnologyDisruptive Technology
Imaging, Characterization, Analysis and Modification in Three Dimensions Down to the Sub-Angstrom Level
NanoBiology NanoResearch NanoElectronics
“Energy creation engine”inside a cell at NCI/NIH
Oil Refining Catalyst
Semiconductor Defect Analysis
Data Storage Metrology
Industry and Institute
NAS 47
A Copper atom is 0.125 nm in diameter
A Penny is 0.75” A Penny is 0.75” diameter = 1.9cmdiameter = 1.9cm
Question? How many copper atoms Question? How many copper atoms can be aligned on the diameter of a can be aligned on the diameter of a penny? penny?
Answer.
152 Million
Scaling The NanoScale
NAS 50
Properties Vary at Nanoscale
Properties: Electronic, Magnetic, Photonic, Catalytic, etc.
Atomic &
Molecular
Nanoscale
Micro-macro-bulk
Gold ~1nm = Semiconductor
100nm
Pro
per
ty s
cale
Bulk materialAtomic 1nm
NAS 51
Industries Entering into NanozoneIndustries Entering into Nanozone
time
feat
ure
siz
e
nanozone
Semiconductors
Data storage
Industries….
Pharmaceuticals and Healthcare….Nanobiology Business
NanoIndustry Business
Nanoelectronics Business
100 nanometers
Research is pervasive
NAS
Change and perception –
Popular culture helps to drive consumer perception• Cost Matters - ALWAYS
– Low end phones in 2000 ~ $150, today ~ $22 ( with better size and more features)
• Size Matters – – Smaller is better, bigger is obviously obsolete
• Function and Quality Matter– Bi-directional video with mid to high range digital camera– Lifetime of music on my iPOD – or cell phone– Virtual surround sound with 3D Video and HDTV headsets– GPS– Wearable devices / voice controlled (accurate) input devices
• Time to Market Matters because – When do I get my personal Tricorder? I want it NOW !!
When does science fiction meet science
Cyber gloves Heads up
displays
NAS
ConclusionConclusion
Advanced products for new generations
Technology Miniaturization Continues !Technology Miniaturization Continues !Design & Test Challenges Continue !Design & Test Challenges Continue !
Innovative Solutions Needed !Innovative Solutions Needed !
NAS
Thank You Thank You