Post on 02-Jun-2018
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ASIC Design Electronics & Communication Department (ME)
1Silver Oak College of Engineering & Technology
SILVER OAK COLLEGE OF ENGINEERING & TECHNOLOGY, AHMEDABAD
DEPARTMENT OF ELECTRONICS& COMMUNICATION ENGINEERING
Practical : 1 DATE:
Aim : INTRODUCTION TO VHDL
VHDL is a language for describing digital hardware used by industry worldwide
VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit)Hardware Description Language
Features of VHDL Technology/vendor independent
Portable
Reusable
Three versions of VHDL VHDL-87
VHDL-93 VHDL-01
Port Modes: The Port Mode of the interface describes the direction in which data travels
with respect to the component.
1) In: Data comes in this port and can only be read within the entity. It can appear
only on the right side of a signal or variable assignment.
2) Out: The value of an output port can only be updated within the entity.It cant be read. It can only appear on the left side of a signal assignment.
3) Inout: The value of a bi-directional port can be read and updated within the entity
model. It can appear on both sides of a signal assignment.
4) Buffer: Used for a signal that is an output from an entity. The value of the signalcan be used inside the entity, which means that in an assignment statement
the signal can appear on the left and right sides of the
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Design Entity
Design Entity is the most basic building block of a design.
Entity Declaration
EntityDeclarationdescribes the interface of the component, i.e. inputand outputports.
ENTITY entity_name ISPORT ( port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
.port_name : signal_mode signal_type);
END entity_name;
Entity declaration
Architecture 1
Architecture 2
Architecture 3
Design entity
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Architecture
Describes an implementation of a design entity.
Architecture simplified syntax
ARCHITECTURE architecture_name OF entity_name IS
[ declarations ]
BEGINcode
END architecture_name;
LibraryLibrary is a collection of packages.WORK&STD are default libraries provided by language. They need not to be explicitly
declared.
Package is a collection of commonly used subprograms, data types and constants.
Library declarations - syntax
LIBRARY library_name;
USE library_name.package_name.package_parts;
Fundamental parts of a library
ENTITY nand_gat eISPORT (
a : IN STD_LOGIC;b : IN STD_LOGIC;
z : OUT STD_LOGIC ) ;END nand_gat e;
Entity namePort names Port type
Semicolon
No Semicolon
Port modes (data flow directions)
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Libraries
ieee
std
work
Need to be explicitlydeclared
Visible by default
Specifies multi-level logic system,including STD_LOGIC, andSTD_LOGIC_VECTOR data types
Specifies pre-defined data types(BIT, BOOLEAN, INTEGER, REAL,SIGNED, UNSIGNED, etc.), arithmeticoperations, basic type conversionfunctions, basic text i/o functions, etc.
Current designs after compilation
PACKAGE 1 PACKAGE 2
TYPESCONSTANTSFUNCTIONSPROCEDURESCOMPONENTS
TYPESCONSTANTSFUNCTIONS
PROCEDURESCOMPONENTS
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Data types
1) Bit type demystified
Value Meaning
0 Forcing (Strong driven) 0
1 Forcing (Strong driven) 1
2)std_logic typeDemystified
Value Meaning
U Not Initialized
X Forcing (Strong driven) Unknown
0 Forcing (Strong driven) 0
1 Forcing (Strong driven) 1
Z High Impedance
W Weak (Weakly driven) Unknown
L Weak (Weakly driven) 0.
Models a pull down.
H Weak (Weakly driven) 1.
Models a pull up.
- Don't Care
Naming and LabelingGeneral rules of thumb (according to VHDL-87)
1. All names should start with an alphabet character (a-z or A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -,
etc.)
4. Do not use two or more consecutive underscore characters (__) within a name(e.g., Sel__A is invalid)
5. All names and labels in a given entity and architecture must be unique.
Free Format
VHDL is a free format language .No formatting conventions, such as spacing or
indentation imposed by VHDL compilers. Space and carriage return treated thesame way.
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Example:
if (a=b) then
Or
If (a=b)then
Or
If (a =
b) Then
Are all equivalent
VHDL Design Styles
1) Dataflow Description Describes how data moves through the system and the various processing steps.
Data Flow uses series of concurrent statements to realize logic. Concurrent statements are
evaluated at the same time; thus, order of these statements doesnt matter.
Data Flow is most useful style when series of Boolean equations can represent logic.
2) Structural Description Structural design is the simplest to understand. This style is the closest to schematic
capture and utilizes simple building blocks to compose logic functions.
Components are interconnected in a hierarchical manner. Structural descriptions may connect simple gates or complex, abstract components.
Structural style is useful when expressing a design that is naturally composed of sub-
blocks
Components andinterconnects
Structural
VHDL Design
Styles
Dataflo
Concurrent
statements
Sequential
statements
Behavioral
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3)Behavioral Description
It accurately models what happens on the inputs and outputs of the black box (no matterwhat is inside and how it works).
This style uses Process statements in VHDL.
Component and Instantiation
1) Named association connectivity (recommended)
component XOR2 is
port(
I1 : in STD_LOGIC;I2 : in STD_LOGIC;
Y : out STD_LOGIC
);
end component;
U1: XOR2 port map (I1 => A,
I2 => B,Y => U1_OUT);
2) Positional association connectivity (not recommended)
component XOR2 is
port(I1 : inSTD_LOGIC;
I2 : inSTD_LOGIC;
Y : outSTD_LOGIC);
end component;
U1: XOR2 port map (A, B, U1_OUT);
Process statement
Process is a concurrent statement but the statements inside it are sequential.Process-simplified syntax
process()declarations
begin
sequential statementsend process;
Concurrent statements
1)when statement:
signal_name
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expression3;
2)with statement
with expression select
target statements
when choice2=> statements
when others=> statementsend case;
Test benchDefined: Test bench applies stimuli (drives the inputs) to the Design Under Test
(DUT) and (optionally) verifies expected outputs. The results can be viewed in a waveform window or written to a file.
Since Test benchis written in VHDL, it is not restricted to a single simulation tool
(portability). The sameTest benchcan be easily adapted to test different implementations (i.e.
different architectures) of the same design.
Test bench Block Diagram
Test bench Environment
TB ProcessesGenerating
Stimuli
Design Under Test(DUT)
Stimuli All DUT Inputs
RULE OF THUMB: USUALLY PORTS FROM DUT ENTITIES ARE DECLARED AS SIGNALS
Simulated Ou
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Test bench Anatomy
Entity TB is
--TB entity has no portsEnd TB;
Architecture arch_TB ofTB is
--Local signals and constants
component TestComp --All Design Under Test component declarations
port ( );
end component;
-----------------------------------------------------
for DUT:TestComp useentitywork.TestComp(archName)--Specify entity/arch pair -- (OPTIONAL)
begin
testSequence: Process
--Main test process
Endprocess; DUT:TestComp portmap( --Port map all the DUTs
);
End arch_TB;
Conclusion:
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10Silver Oak College of Engineering & Technology
SILVER OAK COLLEGE OF ENGINEERING & TECHNOLOGY, AHMEDABAD
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Practical : 2 DATE:
Aim: Design all Half Adder using Data Flow Modeling in VHDL.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);end half_adder;
architecture Data_Flow of half_adder is
begin
sum
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Test Beach Code :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;ENTITY tbw IS
END tbw;
ARCHITECTURE Data_Flow OF tbw IS
COMPONENT half_adder
PORT( a : IN std_logic;
b : IN std_logic;
sum : OUT std_logic; carry : OUT std_logic
);
END COMPONENT;
signal a : std_logic := '0';
signal b : std_logic := '0';
signal sum : std_logic;
signal carry : std_logic;BEGIN
uut: half_adder PORT MAP (
a => a,
b => b, sum => sum,
carry => carry
); stim_proc: process
begin
wait for 20 ns;a
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12Silver Oak College of Engineering & Technology
Test Beach Wave Form :
Conclusion:
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13Silver Oak College of Engineering & Technology
SILVER OAK COLLEGE OF ENGINEERING & TECHNOLOGY, AHMEDABAD
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Practical : 3 DATE:
Aim: Design all Full Adder using Data Flow Modeling in VHDL.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adderis
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC; s : out STD_LOGIC);
end fa_d;
architecture Data_Flow of full_adder is
begin
s
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END COMPONENT;
signal a : std_logic := '0';
signal b : std_logic := '0'; signal cin : std_logic := '0';
signal cout : std_logic;
signal s : std_logic;
BEGIN
uut: full_adder
PORT MAP ( a => a,
b => b,
cin => cin, cout => cout,
s => s
);
stim_proc: process begin
wait for 25 ns;
a
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Test Beach Wave Form:
Conclusion:
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16Silver Oak College of Engineering & Technology
SILVER OAK COLLEGE OF ENGINEERING & TECHNOLOGY, AHMEDABAD
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Practical : 4 DATE:
Aim: Design all Digital gates in VHDL.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity all_gates is Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
and_op : out STD_LOGIC;
or_op : out STD_LOGIC;
nor_op : out STD_LOGIC; nand_op : out STD_LOGIC;
xnor_op : out STD_LOGIC;xor_op : out STD_LOGIC);
end all_gates;
architecture Behavioral of all_gates isbegin
and_op
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nand_op : OUT std_logic;
xnor_op : OUT std_logic;
xor_op : OUT std_logic );
END COMPONENT;
--Inputs signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal and_op : std_logic; signal or_op : std_logic;
signal nor_op : std_logic;
signal nand_op : std_logic; signal xnor_op : std_logic;
signal xor_op : std_logic;
BEGIN
uut: all_gates PORT MAP ( a => a,
b => b,
and_op => and_op, or_op => or_op,
nor_op => nor_op,
nand_op => nand_op, xnor_op => xnor_op,
xor_op => xor_op
);
stim_proc: process
begin wait for 25 ns;
a
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Test Beach Wave Form:
Conclusion:
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SILVER OAK COLLEGE OF ENGINEERING & TECHNOLOGY, AHMEDABAD
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Practical : 5 DATE:
Aim: Design a Half Adder using Behavior Modeling in VHDL.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hf_behhh is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC; carry : out STD_LOGIC);
end hf_behhh;
architecture Behavioral of hf_behhh is
begin
process (a,b)
begin
if a = '0' and b = '0' thensum
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Test Beach Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tbw_hf_beh ISEND tbw_hf_beh;
ARCHITECTURE behavior OF tbw_hf_beh IS
COMPONENT hf_behhh
PORT( a : IN std_logic;
b : IN std_logic;
sum : OUT std_logic; carry : OUT std_logic
); END COMPONENT; signal a : std_logic := '0';
signal b : std_logic := '0';
signal sum : std_logic; signal carry : std_logic;
BEGIN
uut: hf_behhh PORT MAP ( a => a,
b => b,
sum => sum, carry => carry
);
stim_proc: process
begin
wait for 40 ns ;
a
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21Silver Oak College of Engineering & Technology
Test Beach Wave Form:
Conclusion:
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SILVER OAK COLLEGE OF ENGINEERING & TECHNOLOGY, AHMEDABAD
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Practical : 6 DATE:
Aim: Design a Full Adder using Behavior Modeling in VHDL.
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fabeh is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fabeh;architecture Behavioral of fabeh is
beginprocess (a)
begin
if a(0)='0' and a(1) = '0' and a(2) = '0' thensum
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end process;
end Behavioral;
Test Beach Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tbw_fabeh IS
END tbw_fabeh;
ARCHITECTURE behavior OF tbw_fabeh IS
COMPONENT fabeh PORT(
a : IN std_logic_vector(2 downto 0); sum : OUT std_logic; carry : OUT std_logic
);
END COMPONENT;
signal a : std_logic_vector(2 downto 0) := (others => '0');
signal sum : std_logic;
signal carry : std_logic;
BEGINuut: fabeh PORT MAP (
a => a,
sum => sum, carry => carry
);
stim_proc: process begin
wait for 40 ns;
a(0)
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Test Beach Wave Form:
Conclusion:
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SILVER OAK COLLEGE OF ENGINEERING & TECHNOLOGY, AHMEDABAD
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Practical : 7 DATE:
Aim: Design a Half Adder using Structural Modeling in VHDL.
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and1 is Port ( m : in STD_LOGIC;
n : in STD_LOGIC;
o : out STD_LOGIC);
end and1;
architecture Behavioral of and1 is
begin
o
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architecture Stuctural of HF_ST is
component xor1port (x,y: in std_logic;
z:out std_logic);
end component;component and1
port (m,n:in std_logic;
o: out std_logic);
end component;
begin
x1: xor1 port map (a,b,s);y1: and1 port map (a,b,c);
end Stuctural;
Test Beach Code:
LIBRARY ieee;USE ieee.std_logic_1164.ALL;
ENTITY tbw_hfs ISEND tbw_hfs;
ARCHITECTURE behavior OF tbw_hfs IS
COMPONENT HF_ST
PORT(
a : IN std_logic; b : IN std_logic;
s : OUT std_logic;
c : OUT std_logic );
END COMPONENT;
signal a : std_logic := '0';
signal b : std_logic := '0';
signal s : std_logic; signal c : std_logic;
BEGIN
uut: HF_ST PORT MAP (
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a => a,
b => b,
s => s, c => c
);
stim_proc: process
begin
wait for 40 ns;a
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SILVER OAK COLLEGE OF ENGINEERING & TECHNOLOGY, AHMEDABAD
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Practical : 8 DATE:
Aim: Design a Full Adder using Structural Modeling in VHDL.
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and1 is Port ( m : in STD_LOGIC;
n : in STD_LOGIC;
o : out STD_LOGIC);
end and1;
architecture Behavioral of and1 is
begin
o
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architecture Stuctural of HF_ST is
component xor1port (x,y: in std_logic;
z:out std_logic);
end component;component and1
port (m,n:in std_logic;
o: out std_logic);
end component;
begin
x1: xor1 port map (a,b,s);y1: and1 port map (a,b,c);
end Stuctural;
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
entity fa_str is Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC; sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fa_str;architecture Behavioral of fa_str is
component HF_ST is
Port ( a : in STD_LOGIC; b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end component;component or1 is
port (p,q: in std_logic;
r: out std_logic);end component;
signal s1,s2,s3 : std_logic;
beginx1 : HF_ST port map (a,b,s1,s3);
x2 : HF_ST port map (c,s1,sum,s2);
x3: or1 port map (s2,s3,carry);
end Behavioral;
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Test Beach Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tbw_fa_st IS
END tbw_fa_st;
ARCHITECTURE behavior OF tbw_fa_st IS
COMPONENT fa_str
PORT(
a : IN std_logic; b : IN std_logic;
c : IN std_logic;
sum : OUT std_logic; carry : OUT std_logic
); END COMPONENT;
signal a : std_logic := '0';
signal b : std_logic := '0'; signal c : std_logic := '0';
signal sum : std_logic;
signal carry : std_logic;
BEGIN
uut: fa_str PORT MAP ( a => a,
b => b,
c => c, sum => sum,
carry => carry
);
stim_proc: process
begin
wait for 20 ns;
a
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Test Beach Wave Form:
Conclusion:
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SILVER OAK COLLEGE OF ENGINEERING & TECHNOLOGY, AHMEDABAD
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Practical : 9 DATE:
Aim: Design a Gated D Flip-Flop (a) Positive edge (b) Negative edge usingVHDL code.
VHDL Code : (a)
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
entity d_ff is
port (q,qb: out std_logic;d,clk: in std_logic);
end d_ff;
architecture Behavioral of d_ff is
begin
process (d,clk)
begin
if ( clk'event and clk = '1') then
q
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begin
if ( clk'event and clk = '0') then
q qb, d => d,
clk => clk );
stim_proc: process
begin clk
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clk
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SILVER OAK COLLEGE OF ENGINEERING & TECHNOLOGY, AHMEDABAD
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Practical : 10 DATE:
Aim: Design a 4x1 Multiplexer using VHDL code (a) CASE statement(b)IF ELSE statement.
VHDL code: (a)
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
entity mux_4x1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC; c : in STD_LOGIC;
d : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); f : out STD_LOGIC);
end mux_4x1;
architecture Behavioral of mux_4x1 is
begin
mjt: process (s,a,b,c,d)
variable temp : std_logic;
begincase s is
when "00" => temp :=a;
when "01" => temp :=b;
when "10" => temp :=c;when "11" => temp :=d;
when others => temp:= 'U';
end case ;f
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b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0);
f : out STD_LOGIC);
end mux_4x1;
architecture Behavioral of mux_4x1 is
beginprocess (s,a,b,c,d)
variable temp : std_logic;
beginif s = "00" then
temp := a ;
elsif s = "01" then
temp := b;elsif s = "10" then
temp := c;
elsetemp := d;
end if ;
f
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signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0'; signal d : std_logic := '0';
signal s : std_logic_vector(1 downto 0) := (others => '0');
signal f : std_logic;
BEGIN
uut: mux_4x1 PORT MAP (
a => a, b => b,
c => c,
d => d, s => s,
f => f
);
stim_proc: process begin
wait for 20 ns ;
a
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Test Beach Wave Form:
Conclusion:
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39Silver Oak College of Engineering & Technology
SILVER OAK COLLEGE OF ENGINEERING & TECHNOLOGY, AHMEDABAD
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Practical : 11 DATE:
Aim: Design 4-bit Counter Using VHDL code (a) Up counter (b) Downcounter.
VHDL code: (a)
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_unsigned.all;
entity upcounterof4bit is
Port ( CLK : in STD_LOGIC; CLR : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (3 downto 0));end upcounterof4bit;
architecture Behavioral of upcounterof4bit isSIGNAL TEMP : STD_LOGIC_VECTOR(3 downto 0);
begin
PROCESS(CLK,CLR)
BEGINIF ( CLR = '1' ) THEN
TEMP
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architecture Behavioral of downcounterof4bit is
SIGNAL TEMP : STD_LOGIC_VECTOR(3 downto 0);
begin
PROCESS(CLK,CLR)
BEGINIF ( CLR = '1' ) THEN
TEMP
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begin
wait for 18 ns;
CLR