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112/09/2006All right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted except
with prior and express written permission of S.A.B.C.A.
Next Generation Microprocessor for Power Systems Control
September 2006M. Ruiz, SABCA, Belgium
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Next Generation Microprocessor for Power Systems Control
Presentation OverviewScopeMicroprocessor architecture overviewSW development toolsNext generation architecture
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Scope
Power systems control is rapidly evolving:Control algorithms become more and more complexReliability, weight and cost become more and more critical
Community, pushed by high progress made in microelectronics, needed a cheap, hard real-time and safe microprocessorThe microprocessor is called BRISC to refer to its architecture:
Bi: µP holds a dual floating-point unitRisc: RISC architecture
Design started in the 90’s at Université Catholique de Louvain, BelgiumLatest release, HBRISC2, is the radiation-hardened release of BRISC (developed in the scope of a GSTP2 program, in collaboration with ESA-ESTEC)
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BRISC Architecture Overview
GSTP2-IMCM goal: Develop and qualify a generic platform allowing control of a wide range of motor and drive electronics for space mechanismsThe core of the platform is the HBRISC2 microprocessorPlatform provides
A customized library, allowing development & simulation within Simulinkenvironment An automatic binary code generation function, thus decreasing software design effortA user-friendly environment for application debugging/fine-tuning/validation
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BRISC Architecture Overview
Microprocessor Key Features:Versatile, standard productRISC machine, uninterruptible:
Fully predictable execution timeEasier SW validation
Saturating floating-point data format (16-bit mantissa, 8-bit exponent)Power systems data require high dynamicRescaling, overflow study,... is avoided
Full application data visibility, at Simulink-levelEasier SW validation
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BRISC Architecture Overview
Microprocessor Key Features:Fast on-chip memory data
Avoid access to (slow) external RAMAutomatic SEU correction (EDAC) of internal and external RAM upsets
Fully transparent for application SW1-bit errors are detected AND correctedN-bit erros are detected and reported
Built-in autonomous and configurable functions required for power system control (PWM, sensors excitation, ADC interface,high-speed reporting…)
Decreases CPU load
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BRISC Architecture Overview: Functional Diagram
HBRISC2HBRISC2
3 /
GLOBAL REGISTERS
RIO
FIXED POINT ARITHMETIC
UNIT
RPAD
Unit SU
ON-CHIP PERIPHERAL INTERFACE
motor PWM
excitation PWM
Serial Fast link
ADC interface
Serial port(SPI)
Program bus
HBRISC2 CORE
softwaretimer
INSTRUCTION REGISTER
ON-CHIP SEU ERROR
DETECTION/ CORRECTION
ON-CHIP MEMORY SEU ERROR
CORRECTION UNIT
INSTRUCTION DECODER
GLOBAL REGISTERS
REGISTER BANK
FLOATING
POINT UNIT
Unit B
GLOBAL REGISTERS
REGISTER BANK
FLOATING
POINT UNIT
Unit A
I/O interface
Peripheral bus
⁄ 2 ⁄ 6 ⁄ 18
46 /
HBRISC2 PERIPHERAL
REGISTERS
SEU DETECTION/
CORRECTIONUNIT
INSTRUCTIONSEQUENCER
BOOT ROM
CRC check
⁄ 2
⁄ 32+7
ADDRESS REGISTER
⁄ 16
Address bus
Prog. outputs
4 /
/ 1
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BRISC Architecture Overview: HBRISC2 ASIC Technology
ATMEL MH1RTRad-Tolerant Latch-up immuneSEU hardened registersGate-array 0.35 µm5V I/O pads3.3 V Core
HBRISC2Matrix: MH1_156EPackage: MQFP-2564 on-chip dual-port RAM
Bank registersSPI interface buffers
Performance:60 MFLOPS30 MIPS
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BRISC Architecture Overview : SW development tools
SimplifiedSIMULINK model
(mdl file)
SIMULINK library
(lib_imcm.mdl)
Macro definition
(macros.lst)
HBrisc2 parameterinitialisation
(initialisations.bc)
Variabledefinition file
(m files)
SYNTHESISER Synthesised
SIMULINK model(mdl file)
Code source(b2c file)
Macro library(bh files) Target
hardware
CompilationHbrass2.exe
Softwarevalidation
testing(Seracq-Win32)
Binary code(bin file)
Generated Code Key Features:Macro-basedStatic register allocationOS-freeFully static and sequential execution
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BRISC Architecture Overview: Applications
Mainly Motor-Control applicationsSpace:
TVC (Thrust Vector Control) for the 4 stages of the VEGA Launcher (SABCA, Belgium)Tip-Tilt Mechanism: mirror fine-pointing application (GSTP3, CSEM, Switzerland)
Military/Civil Aerospace:License sold to ”Dassault Electronique” for M51Several demonstrators developped for A320 primary flight controlF-16 pod air-conditionning: sensorless control
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Towards Next BRISC Generation
Non-intrusive background interface for SW validationFacts:
Validation can not be (safely) performed with instrumentation codeValidation must be made at processor full-speedThe processor can not be interrupted
Need for standardized non-intrusive interface: Nexus?
ASIC technology:Allow a higher integration of peripherals: RAM, EEPROM, ADC, IP,...Need for new ASIC technology sources:
SOI (Silicon-On-Insulator): preliminary meetings are encouragingOther?
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Towards Next BRISC Generation
Towards IP availabilityEasy integration into an FPGA, ASIC, SoC,...Configurable architecture to better suit target application
Standardized SW toolsC compilerSimulink tool-boxIEEE floating data formatSimulatorAutomatic generation of the initialisation file