Post on 11-Jan-2016
transcript
Nick McKeown
CS244 Lecture 7
Valiant Load Balancing
Simple Model of US Backbone
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Designing a Backbone Network
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1. Hard to measure current traffic matrix.- Harder still to estimate future traffic matrices.
1. Hard to know which traffic matrices can be supported.- Harder still under link and node failures.
The Problem
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POPs in big cities
Q: How capacity to provision between two POPs?
The Problem
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Router capacity = NrSwitch capacity = N2r
100% Throughput in a Mesh
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Questions
How would we provision the links if we know the traffic matrix?
What is the cost of not knowing the traffic matrix?
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Valiant Load Balancing
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Outline for Today
1. Basic idea of load-balancing
2. Packet mis-sequencing
3. An optical switch fabric
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If Traffic Is Uniform
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Real Traffic is Not Uniform
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Can we make traffic “sufficiently uniform” to make the problem trivial?
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VLB Switch
Load-balancing stage Forwarding stage
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100% throughput for weakly mixing traffic (Valiant, C.-S. Chang)
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112233
VLB Switch
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VLB Switch
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Intuition: 100% Throughput
Arrivals to second mesh:
Capacity of second mesh:
Second mesh: arrival rate < service rate
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-b RUaUN
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[C.-S. Chang]
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Another way of thinking about it
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External Outputs
Internal Inputs
External Inputs
Load-balancing cyclic shift
Switching cyclic shift
Interesting properties:• 100% throughput, no arbiter (but 2x switching capacity)• No part of the system need operate faster than the line rate
Performance
1. What are the performance tradeoffs between a scheduler and a load-balanced design?
2. How can a load-balanced switch have lower loss than an OQ switch?
3. “I’m surprised that no one came up with the idea earlier”
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What you said
My favorite line in the paper is the following: "If it is possible to build a packet switch with 100% throughput that has no scheduler, no reconfigurable switch fabric, and buffer memories operating without speedup, where does the packet switching actually take place?" The answer of course in the VOQs…”
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Outline
1. Basic idea of load-balancing
2. Packet mis-sequencing
3. An optical switch fabric
What you said
“[I]f packet mis-sequencing is such a performance hit due to the way TCP is designed and how the Internet has reached to a point where a new transport protocol adoption is impractical, I wonder how long we will all have to live with TCP before Internet traffic reaches a point where a whole new layering system must be re-architected (and what might David Clark might have to say about that).”
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Packet Mis-sequencing
1. Does the Internet allow packets to be mis-sequenced?
2. Why do we (or network operators) care?
3. Will the Internet require packets to stay in sequence in the future?
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Packet Reordering
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Bounding Delay Difference Between Middle Ports
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Uniform Frame Spreading
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FOFF (Full Ordered Frames First)
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FOFF (Full Ordered Frames First)
Input Algorithm N FIFO queues corresponding to the N output flows Spread each flow uniformly: if last packet was sent to
middle port k, send next to k+1. Every N time-slots, pick a flow:
- If full frame exists, pick it and spread like UFS - Else if all frames are partial, pick one in round-robin order and send it
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Bounding Reordering
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FOFF
Output properties N FIFO queues corresponding to the N middle
ports Buffer size less than N2 packets If there are N2 packets, one of the head-of-line
packets is in order
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Output
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VLB + FOFF Properties
With quite a lot of work, packet order is maintained
Interestingly, expected packet delay is within a constant of OQ switch (surprising)
Therefore, VLB with FOFF has 100% throughput
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Outline
1. Basic idea of load-balancing
2. Packet mis-sequencing
3. An optical switch fabric
What you said
"They state that their theoretical 100 Tb/s switch should be able to be built in about 3 years, so if they were correct it should have long since have been built. I was unable to find anything about 100 Tb/s optics switches being used, so I’m not sure if it happened or not. There was another paper on the subject in 2010, suggesting that it took more than 3 years for technology to advance sufficiently. If such a switch has been manufactured, did it perform to expectations? If not, what prevented it?”
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From Two Meshes to One Mesh
One linecard
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From Two Meshes to One Mesh
First meshIn Out
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One linecard
Second mesh
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From Two Meshes to One Mesh
Combined meshIn Out
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Many Fabric Options
Options
Space: Full uniform meshTime: Round-robin crossbarWavelength: Static WDM
Any spreadingdevice
C1, C2, …, CN
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N channels each at rate 2R/NOne linecard
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AWGR (Arrayed Waveguide Grating Router) A Passive Optical Component
Wavelength i on input port j goes to output port (i+j-1) mod N
Can shuffle information from different inputs
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Linecard 1
Linecard 2
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Linecard N
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In Out
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Static WDM Switching: Packaging
AWGR
Passive andAlmost Zero
Power
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B, B, B, B
C, C, C, C
D, D, D, D
N WDM channels, each at rate 2R/N
Linecard placement and failureWhat happens if a linecard is missing or fails?
Does this happen in practice?
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