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Parasitic Extraction and Post-Layout Simulation

Author: Chenyuan Zhao

1. In this tutorial, the Parasitic Extraction and Post-Layout Simulation would be introduced.

Once the layout passes the DRC and LVS check, it is time to verify the performance of the

layout. From the top menu, click “Calibre” “Run PEX”.

2. Click “Cancel” when the Load Runset File window pops up.

3. Set the PEX Rules File path as

“/home/PDK/PDK_Cadence/TSMC/TSMC180/TSMC180Install/Calibre/rcx/calibre.rcx”

and set the PEX Run Directory as your working directory.

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4. Make sure the Inputs’ configuration is

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5. Make sure the Outputs’ configuration is in “Transistor Level” and “C+CC”. Also make sure

that “CALIBREVIEW” is picked for “Format” and “LAYOUT” is picked for “Use Names From”

(look at the red box region).

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6. In the PEX Options – if this is not showing in the window go to Setup PEX Options -- make

sure the “include SVRF” session contains these scripts as

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In LVS Options session, make sure to include your “Power nets” and “Ground nets”, in this

tutorial they are “vdd!” and “gnd!”.

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7. After finish all configuration, click “Run PEX”. A setup window will appear. Make sure that the

“Cellmap File” column is filled with

“/home/PDK/PDK_Cadence/TSMC/TSMC180/TSMC180Install/Calibre/rcx/calview.cell

map”. Fill the related place with the path if it is different. Click “OK”.

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Check the pop up wind to make sure there is no errors.

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Until now, you have finished the first part of layout design. We will then discuss about post-

layout simulation.

8. Create new “cellview” test bench as introduced in tutorial test bench creation.

9. The post-layout simulation process is similar to the pre-layout simulation. The only thing you

need to do is change the environment by click “Setup - Environment” in “Analog Design

Environment” which has been used in pre-layout simulation.

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In the popup window, replace the key word “schematic” with “calibre” and then click “OK”.

10. After everything is settle down, you can use the technique that introduced in pre-layout

simulation part to do the post-layout simulation. AC simulation example is provided.

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