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Performance Enhancement of the Tunnel Field EffectTransistor for Future Low Stand-by Power Applications
A Thesis
Submitted For the Degree of
Master of Science (Engineering)
in the Faculty of Engineering
by
Nayan Bhogilal Patel
Centre for Electronics Design and Technology
Indian Institute of Science
BANGALORE 560 012
August 2007
iNayan Bhogilal Patel
August 2007
All rights reserved
TO
My Parents
Mrs. Sushila B. Patel
&
Mr. Bhogilal I. Patel
Acknowledgements
I express my sincere thanks to my adviser Prof. Santanu Mahapatra for giving me an
opportunity to work on a very interesting and challenging topic. He was always easily
approachable and always ready to answer any of my queries. I am also thankful to him for
introducing me to the field of VLSI Device Physics. I am thankful to Prof. Navakanta
Bhat, ECE for his course on VLSI Device and Process Simulation which formed the
background of my work.
I am thankful to Chaitanya Sathe for his help with Linux and LATEXand also for a
lot of enlightening discussions which have only added to my knowledge of semiconductor
physics. I am also thankful to Ramesha for his help with designing the process flow
for the fabrication of the Tunnel FET. Thanks are due to Biswajit for some very good
discussions. I was really lucky to have such good lab mates.
Living at the Indian Institute of Science is an experience in itself and my stay over
here was made even more memorable by my friends Venu, Nehal maam, Guru, Hemant,
Rajdeep, Amrish, Chintan, Pratikbhai, Mehul and Rashmin. Their presence made my
life much more easy and comfortable. I would like to thank all of them.
A big thanks to my parents for their unconditional love, encouragement and support
throughout my student life. They have sacrificed a lot for my education and whatever I
am today is all due to them. I will try my best that the efforts of all those acknowledged
will not go in vain.
i
Publications based on this Thesis
1. Tunnel FET - A Novel Device with Sub-Threshold Swing less than 60 mV/decade
for Future Low Stand-by Power Applications, Appearing in Proc. National Con-
ference on VLSI and Communication Engineering 2007, Kottayam, India
2. A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance
for Low Stand-By Power Applications, Appearing in Proc. VLSI Design And Test
Symposium 2007, Kolkata, India
3. Performance Enhancement of the Tunnel Field Effect Transistor using SiGe Source
Appearing in the Proc. Fourteenth International Workshop on Physics for Semi-
conductor Devices, Dec 2007, IIT Bombay, India
Patent based on this Thesis
1. Indian Patent applied for Silicon Tunnel Field Effect Transistor
ii
Abstract
Continuous downscaling of CMOS technology has led to immense improvements in its
performance. However, the switching characteristics of the present day MOSFET switch
are far from the ideal one. For the Ideal switch the sub-threshold swing is zero and this
leads to zero off-state current. This off-state current is the most crucial parameter for
the low standby power applications (e.g. cellular phone) as it determines the battery life
of the device. The minimum value of the sub-threshold swing of todays MOSFET is
physically limited to 60mV/decade at room temperature due to the drift-diffusion mode
of carrier transport. In fact in ultra-short channel MOSFET the sub-threshold swing is
further deteriorated due to several parasitic effects (e.g., punch through, short channel
effects etc). Therefore for future low standby power application one requires alternative
MOSFET architecture which uses different type of carrier transport mechanism. The aim
of this thesis is to explore the various available options and to come up with a technology
which is CMOS compatible and solves the problem of increased leakage for low standby
power applications. The Tunnel Field Effect Transistor (TFET) with perfect saturation
in the output characteristics, sub-60mV/decade subthreshold swing and extremely high
ION/IOFF ratio has attracted a lot of attention for such applications. However, due to
extremely low IOFF , even though it has a very good ION/IOFF ratio, it fails to meet
the technology requirements of ION . To overcome this problem of low ION , in this
work, we have proposed a new Tunnel FET architecture with SiGe layer at the source
end. The improvement in ION is achieved by modulating the bandgap at the tunneling
junction by varying the Ge mole fraction in the SiGe layer. By the use of 2D device
simulation, we demonstrate that the proposed device is scalable upto channel lengths as
iii
iv
small as 30 nm. Also, the device becomes nearly free from DIBL as the germanium mole
fraction is increased. A CMOS compatible process flow to fabricate the proposed device
is discussed. The compatibility of the process flow with the standard CMOS process
makes the proposed device highly attractive for future low stand-by power applications.
Contents
Acknowledgements i
Publications based on this Thesis ii
Abstract iii
1 Introduction 11.1 The MOSFET Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 I-MOS:The Impact Ionization MOSFET . . . . . . . . . . . . . . . . . . 41.3 TFET:Tunnel Field Effect Transistor . . . . . . . . . . . . . . . . . . . . 5
1.3.1 Planar TFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3.2 Vertical Channel Tunnel FET . . . . . . . . . . . . . . . . . . . . 71.3.3 Ultra thin body SOI TFET . . . . . . . . . . . . . . . . . . . . . 10
1.4 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Double Gate Tunnel FET 142.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2 Device structure and Operation . . . . . . . . . . . . . . . . . . . . . . . 152.3 Simulation Tools and Models . . . . . . . . . . . . . . . . . . . . . . . . 162.4 Simulations and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.5 Floating Body Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.6 Scaling of Double Gate TFET . . . . . . . . . . . . . . . . . . . . . . . . 232.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3 Tunnel FET with SiGe layer at Source 253.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.2 Device Structure and Operation . . . . . . . . . . . . . . . . . . . . . . . 263.3 Simulation Models and Device Parameters . . . . . . . . . . . . . . . . . 283.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.1 The SiGe layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.4.2 Depth of SiGe Layer (Ld) . . . . . . . . . . . . . . . . . . . . . . 333.4.3 Effect of Body bias . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4.4 SCE and DIBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
v
CONTENTS vi
3.4.5 High material as gate dielectric . . . . . . . . . . . . . . . . . . 363.4.6 Effect of Strain on the channel . . . . . . . . . . . . . . . . . . . . 373.4.7 Effect of Strain on on SiGe layer . . . . . . . . . . . . . . . . . . . 383.4.8 Lateral vs. Vertical TFET . . . . . . . . . . . . . . . . . . . . . . 38
3.5 Fabrication of The Proposed Device . . . . . . . . . . . . . . . . . . . . . 393.5.1 Description of Process steps . . . . . . . . . . . . . . . . . . . . . 403.5.2 Impact of Mask Misalignment . . . . . . . . . . . . . . . . . . . . 40
3.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4 Conclusion and Scope of Future work 444.1 Process Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.2 Pass Transistor Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
A Sub-threshold Swing of Tunnel Transistors 47
Bibliography 49
List of Figures
1.1 Comparison of MOSFET with Ideal switch . . . . . . . . . . . . . . . . . 21.2 Effect of MOSFET Scaling on IOFF . . . . . . . . . . . . . . . . . . . . . 31.3 I-MOS: Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4 I-MOS: Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . 51.5 Planar TFET: Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.6 TFET working: Band diagrams . . . . . . . . . . . . . . . . . . . . . . . 71.7 VTFET: Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.8 Effect of SiGe layer on band diagrams . . . . . . . . . . . . . . . . . . . . 91.9 SOI TFET: Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.10 SOI TFET: Band diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Double Gate TFET schematic . . . . . . . . . . . . . . . . . . . . . . . . 152.2 ID vs. VGS and ID vs. VDS characteristics of the DG Tunnel FET . . . . 172.3 Gm*Ro for the double gate TFET . . . . . . . . . . . . . . . . . . . . . . 182.4 VTFET Band diagram near surface region . . . . . . . . . . . . . . . . . 192.5 Point S vs. VGS for DG TFET . . . . . . . . . . . . . . . . . . . . . . . . 202.6 DGTFET Band diagram in bulk region . . . . . . . . . . . . . . . . . . . 202.7 Tunneling Electric field in Bulk and Surface regions vs VDS . . . . . . . . 212.8 Smin and ION/IOFF vs. VDS . . . . . . . . . . . . . . . . . . . . . . . . . 222.9 Smin and ION/IOFF vs. TSi . . . . . . . . . . . . . . . . . . . . . . . . . . 222.10 Scaling the DG TFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.2 Working Band diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.3 Simulated Band Diagrams of the proposed Tunnel FET architecture in
Fig. 3.1 along the cut section (AB) . . . . . . . . . . . . . . . . . . . . 303.4 Simulated Device characteristics for the proposed device . . . . . . . . . 313.5 S and ION vs. x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.6 GBTBT contours at the tunnel junction . . . . . . . . . . . . . . . . . . . 333.7 ION vs. SiGe layer depth (Ld) . . . . . . . . . . . . . . . . . . . . . . . . 343.8 Effect of body bias on device characteristics . . . . . . . . . . . . . . . . 353.9 SCE and DIBL in the proposed device . . . . . . . . . . . . . . . . . . . 363.10 High dielectric with proposed device . . . . . . . . . . . . . . . . . . . 373.11 Effect of x of stained and relaxed SiGe on Bandgap . . . . . . . . . . . . 38
vii
LIST OF FIGURES viii
3.12 Process changes necessary to fabricate the proposed device . . . . . . . . 413.13 Overcoming Mask misalignment . . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 1
Introduction
1.1 The MOSFET Switch
Over the last couple of years, the sales of certain battery powered equipment (like mobile
phones, PDAs, Palmtops etc.) has increased immensely. Today, these devices form a
major market share of the semiconductor industry. Being battery operated, lowering the
power consumption w/o trading off the performance is the primary aim of the manufac-
turers. Since, all these devices mostly operate in the standby mode, of operation, it is
required that they consume very less power when on standby. Therefore, they are also
called Low Standby Power (LSTP) devices.
Ideally, any device should consume zero power when on standby. However, these
devices use the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which
has a non zero off state current (IOFF ), as the switch. The IOFF in any device is directly
dependent on the sub-threshold swing (S) of the device. Lower the value of S, lower is
the off-state current of the device. S is defined as the amount of gate voltage needed
to change the drain current by 1 decade. It indicates how effectively the MOSFET can
be switched OFF by decreasing the gate voltage below VTH . For an ideal switch, the S
is equal to zero and this leads to a zero off-state current(Fig. 1.1). Relentless scaling
of the MOS switch has led to an increase in the IOFF of the device. Fig. 1.2(a) shows
the increase in IOFF due to the reduction in VTH of the device as a result of scaling
1
Chapter 1. Introduction 2
IOFF
IDS
Sub-threshold Regime
VGS
Ideal Switch
MOSFET Switch
Figure 1.1: Transfer characteristics of Ideal and MOSFET switch on semi-log scale
(assuming that S remains constant as we scale down). Fig. 1.2(b) shows that S degrades
as we scale the MOSFET due to the various effects like Punch through, Short Channel
Effect (SCE), and Drain Induced Barrier Lowering (DIBL) in short channel devices. As
a result of this the value of IOFF increases even more than expected.
MOSFETs employ a Drift-Diffusion model for carrier injection. In the Sub-threshold
region (VGS < VTH), the current is dominated by diffusion mechanism. The Drain current
in this region of operation is given by [1],
IDS = effCoxW
L(m 1)
(kT
q
)2eq(VgVt)/mkT (1 eqVds/kT ) (1.1)
taking logarithm and then differentiating w.r.t. VGS and inverting, we get
S = 2.3kT
q
(1 +
CsiCox
+CitCox
)(1.2)
where,
Cit = interface state Capacitance,
Cox = gate oxide capacitance and
Csi = bulk Silicon capacitance
When the gate oxide thickness becomes zero, S approaches approximately 2.3kT/q
Chapter 1. Introduction 3
IOFFH
IOFFL
IDS
VTL VTH VGS
(a) Increase in IOFF due to reduction in VT
IDS
VT
DIBL
SCE
Punch Through
VGS
(b) Increase in IOFF due to degradation of Sas a result of scaling
Figure 1.2: Effect of MOSFET Scaling on IOFF
(60 mV/decade). But due to the presence of non idealities such as interface states, the
practical value is higher than this. Also, as we scale down, the value increases further
due to an increase in doping concentration and Short channel Effect (SCE). This means
that we gradually move away from Ideal switch behavior. Fig.1.1 shows a comparison
between the MOS switch and the ideal switch. The above problem is inherently due to
the Drift-Diffusion mechanism of carrier conduction. Therefore, for future low standby
power applications, one requires alternative MOSFET architecture which uses a different
type of carrier transport mechanism. Various device concepts have been suggested and
researched recently. [3], [4]. Among these, the Tunnel Field Effect Transistor (TFET)
has shown a lot of promise for achieving better scaling without severe short channel
effects [5]. In the following sections, we discuss in detail, the structure and working of all
these devices and justify why TFET is the best possible option. In the chapters following
this one, we further explore the working of TFET by means of 2D computer simulations.
We also identify the short comings of the present day TFET and try and come up with
an alternative to overcome them.
Chapter 1. Introduction 4
1.2 I-MOS:The Impact Ionization MOSFET
The basic device structure of an n-channel I-MOS as proposed by Plummer et al. [6]
is as shown in Fig.1.3. It is a gated p-i-n diode operating in the reverse biased region
and works on the principle of modulation of channel length. For low gate voltages,
the channel length is the entire I region. The electric field in this condition is below
breakdown and consequently, the device is off. The off-state current is limited to the
reverse leakage current of the p-i-n diode. As VGS is increased, an inversion layer forms
under the gate and the effective channel length reduces to L1. Due to reduction in the
length, the electric fields in the region increase, causing impact ionization to occur and
the device breaks down. The breakdown region is lightly doped so as to reduce the fields
required for impact ionization which prevents Band to Band Tunneling (BTBT) related
soft breakdown. Here, the formation of the inversion layer is limited by the normal
60mV/decade limit, but the strong dependency of the impact ionization coefficients
on the electric field and the inherent feedback involved in the avalanche multiplication
process produces a very steep sub-threshold characteristics.
Figure 1.3: Basic Device structure of an N-channel SOI version of the IMOS [6]
Fig.1.4 shows the simulated ID vs. VGS characteristics obtained by [6]. The results
indicate an S of 5mV/decade and near ideal switching characteristics are obtained.
To follow-up the simulation results, a prototype device was also fabricated in silicon
Chapter 1. Introduction 5
Figure 1.4: Simulated ID vs. VG characteristics for an n-channel germanium I-MOS [6]
and it showed an S of 10mV/decade at a drain voltage of 20V. However, the following
problems were faced in the first prototype:
1. The drain current was very low because of large parasitic resistances from long
source-drain extensions.
2. These devices also suffer from hot carrier effects which result in a significant thresh-
old voltage shift. To avoid them, the breakdown region should be kept away from
the surface of the device. This can be done by using a buried channel device.
3. Very high drain voltages are required. This is because Si has a higher band-gap
and a large ratio of the ionization coefficients (n/n > 10) which leads to high
breakdown voltages. Also, the surface ionization coefficients are much lower than
bulk ionization coefficients because of a reduction in mean free path due to interface
scattering.
1.3 TFET:Tunnel Field Effect Transistor
The TFET is also a gated reverse biased p-i-n structure like the I-MOS but it uses the
principle of gate controlled Band to Band Tunneling (BTBT) for operation. A total of
Chapter 1. Introduction 6
three different architectures for the TFET have been proposed till date.
1.3.1 Planar TFET
Fig.1.5 shows the schematic of a planar n-type TFET [4]. To understand its working,
we need to study its band diagram (Fig.1.6). Applying a positive gate-source voltage
produces a layer of electrons under the gate oxide, which pulls the valance band and
the conduction band in the intrinsic (lightly doped) region downwards. This leads to a
narrow barrier at the interface of the p+ doped region and the channel. Now the electrons
can tunnel from the valance band of p+ region to the conduction band of the intrinsic
region and therefore induce a higher ID. Because of the similarity of the characteristics
to a NMOS FET, this operation mode is called NTFET.
Figure 1.5: Basic device structure of the conventional planar N-channel Tunnel FET [4]
A negative gate voltage produces a layer of holes below the oxide and as a result, the
bands in the intrinsic region get pulled up, this time forming a shallow barrier near the
interface of n+ and the intrinsic regions. The electrons tunnel from the valance band
of the intrinsic region to the conduction band of the n+ region. Now the transistor is
in PTFET operation. Note, that the source of both NTFET and PTFET is defined as
the highly doped region which is closer to the tunnel junction. Since, only the tunneling
Chapter 1. Introduction 7
0.2 0.25 0.3 0.35 0.4 0.45 0.52.5
2
1.5
1
0.5
0
0.5
1
1.5
Ener
gy (e
V)
Distance (m)
VGS = 0V
VGS = 2V
e
p+ sourceisiliconn+ drain
EC
EV
VDS = 1.0V
Figure 1.6: Simulated Band diagrams of TFET in conducting and non-conducting regions
region of the TFET is the active region of the TFET, and it is very small, the TFET
can be scaled down to 20nm and below, without using other than standard MOSFET
materials [5].
1.3.2 Vertical Channel Tunnel FET
The VTFET was proposed by Bhuwalka et al. [15] and is a modified version of the
Planar TFET . The schematic of the device is as shown in Fig.1.7
This device consists of a molecular beam epitaxy (MBE) grown, vertical p-i-n struc-
ture. The vertical stack consists of a boron-doped source substrate, a 3 nm, 1 x 1020
cm-3 boron-doped delta layer (p+), 100 nm n-type unintentional-doped (1 x 1016cm3)
channel and a heavily doped n+ drain electrode. A vertical gate stack is grown on the
sidewall. The operating principle is same as planar TFET. Here, a vertical gate controls
the band to band tunneling width, and hence the tunneling current. The so called -
layer is deposited above the intrinsic channel to achieve an abrupt doping profile at the
source. This results in a much better device performance as the tunneling is assisted
by abrupt profiles. However, the performance can be further improved by replacing the
-layer by a highly doped strained SiGe--layer.
Chapter 1. Introduction 8
Figure 1.7: A schematic of the Vertical Channel Tunnel FET [15]
Effect of the SiGe- Layer: The delta layer plays a major role in improving the
electrical characteristics of the VTFET [9].It is seen that the incorporation of pseudo-
morphic strained Si1xGex leads to a significant performance increase. Due to the lower
bandgap of Germanium, the tunneling width decreases. Hence, there is a higher tun-
neling probability for electrons in this region and therefore, higher ION can be achieved.
This also improves the Sub-threshold slope of the device. We can further control the
ION/IOFF ratio by varying the Ge mole fraction (x) in the SiGe layer. Fig. 1.8 shows
the new band diagram after the introduction of the SiGe layer. A reduction in the tun-
neling width () can be clearly seen due to the introduction of a small notch near the p+
intrinsic region junction. It is to be noted here that the increase in current is due to the
reduction in tunneling width () and not due to the reduction in band-gap (Wg). As x is
varied from 0 to 0.5, an improvement in the sub-threshold swing is observed. This is due
Chapter 1. Introduction 9
Figure 1.8: Simulated band diagrams for 100nm n-channel VTFET with p+-SiGe layer(x=0.5) as a function of VGS [26]
to the fact that the Band to Band tunneling Generation rate increases with a reduction
in the bandgap of the material.
According to Kanes model for BTBT, the generation rate is given by [20],
GB2B = AKaneE2W1/2g e
BKaneW3/2g /E (1.3)
where, Akane and Bkane are material dependent constants and E is the electric field at the
tunneling junction of the TFET. It can be clearly seen that the BTBT generation rate
is inversely related to the bandgap (Wg). Thus, the subthreshold swing can be reduced
below the 60mV/decade limitation of the MOSFET by increasing the Germanium mole-
fraction (x) in the SiGe layer [26]
Chapter 1. Introduction 10
1.3.3 Ultra thin body SOI TFET
This TFET architecture was proposed by Zhang et al [3]. The P-type structure of the
transistor is shown in Fig. 1.9 and comprises of a silicon-on-insulator (SOI) structure
in which a lateral p+ n+ junction is formed in an ultra-thin semiconductor body.The gate is aligned to the junction on the p-side so as to facilitate better control of
Figure 1.9: Schematic cross section of the P-type Ultra thin body Silicon on InsulatorTFET proposed in [3]
the p-side electrostatic potential. The p-region is fully depleted for zero gate bias. An
analytic solution for the potential profile using a two dimensional (2-D) Poisson equation
is performed in [3]. Ignoring the statistical dopant fluctuations (which become important
as we scale down), the potential (x, y) is given by, for 0=x=tSi and L=y=L+W
d2(x, y)
dx2+d2(x, y)
dy2=qNasi
(1.4)
where, NA is the acceptor concentration on the p-side, Si is the Si dielectric constant
tSi is the thickness of the dielectric layer and L is the gate length
The n-side is un-modulated by the gate and therefore can be treated as a one dimen-
sional (1-D) problem with the potential given by [3]
for 0=x=tSi and L=y=L+W
d2(x, y)
dy2= qNa
si(1.5)
where, ND is the doping concentration on the n-side, and W is the depletion length on
Chapter 1. Introduction 11
the n-side
Equations 1.4 and 1.5 have been solved using the following 4 boundary conditions:
1. Constant potential on the surface between the semiconductor and the gate oxide;
2. Zero electric field in the x direction on the surface between semiconductor and
buried oxide;
3. Continuous potential and electric field at the p-n junction; and
4. 0.3-eV schottky barrier at the drain contact.
Energy bands shown in 1.10 were computed from the solutions of the above equations.
The transistor operation can be understood from the band diagrams.
(a) (b)
Figure 1.10: Energy Band Diagrams at x=0 (in 1.9) with (a) zero and (b) negative gatevoltages [3]
The transistor off state is shown in Fig. 1.10(a); for a VGS of zero, the p side is
depleted and the interband tunneling probability is low. When a negative gate voltage
is applied, the valance band on the p-side is raised above the Fermi level on the n-side
turning the interband tunneling and the transistor ON Fig. 1.10(b). In this transistor
Chapter 1. Introduction 12
geometry, the gate screens the drain field enabling current saturation and isolation. The
analytic model was verified using the Synopsis device simulator ISE TCAD. 2D device
simulations of the transistor showed a subthreshold swing less than 60mV/decade for
low gate voltages.
1.4 Comparison
Comparison of TFET and IMOSDEVICE ADVANTAGES DISADVANTAGESI:MOS 1. Very low IOFF .
2. Very fast Switching Speed (pS).3. S as low as 5mV/decade can beobtained.4. Easy to fabricate complementarydevices.
1. Output Voltage swing is not rail torail.2. IDS is low because of parasiticresistances fromlong source drain ext.regions.3. Hot carrier effects resulted in VTshifts.4. High VDS is required (n/p > 10)
TFET 1. Very low IOFF (fA).2. S is not limited to 60mV/decade.3. IOFF and VT are independent ofchannel length and scaling.
1. Because of low IOFF , the con-ventional TFET fails to meet thetechnology requirements for ION andVT .2. The VTFET overcomes these prob-lems but fabrication and packagingis not compatible with the standardCMOS process.
1.5 Conclusions
In this chapter, we have examined the problems faced by the MOSFET as it enters the
nano-scale regime. Here, we propose to deal with the challenge of increased leakage and
Sub-threshold swing of the MOSFET. Due to the drift diffusion mode of carrier trans-
port, the sub-threshold swing in the MOSFET is limited theoretically to 60mV/decade
at room temperature. The Tunnel FET with perfect saturation and in the output char-
acteristics and exponentially increasing IDS versus VGS, has shown a lot of promise for
Chapter 1. Introduction 13
sub-100nm analog and digital applications. However, the Silicon Tunnel FET, though it
can be scaled to sub-20nm regime, because of very low IOFF , fails to meet the technol-
ogy requirements in terms of ION and VT . The main challenges in this field lie in the
proper understanding of the carrier transport of the TFET and try and improve its drive
strength so that it can be used for future Low Standby Power applications.
Chapter 2
Double Gate Tunnel FET
2.1 Introduction
As discussed in the previous chapter, the switching characteristics of the MOSFET switch
have degraded considerably over the years. This has posed a major hurdle in its appli-
cation to Low Stand by power applications if the scaling were to continue.
The Tunnel Field Effect Transistor (TFET) [4] with perfect saturation in the output
characteristics and exponentially increasing IDS versus VGS has shown a lot of promise
for achieving better scaling without severe short channel effects [11]. In the following
sections, we discuss in detail, the structure and working of TFET and how it can offer
an alternative for future LSTP applications.
Off all the variants of TFET, the Vertical channel TFET (VTFET) discussed in
section 1.3.2 with pseudomorphic p+-SiGe layer has been the most widely discussed
one in the literature. It has shown some very good electrical properties. However, its
fabrication, which involves complex processes such as Molecular Beam Epitaxy (MBE)
is a very costly and time consuming process.
Thus, it is desirable to have a structure which can be fabricated with the existing
process consisting of standard CMOS fabrication steps. In this work, we study by means
of 2D- computer simulations, a planar Double gate structure of Tunnel FET whose
fabrication can be easily integrated with the standard CMOS technology.
14
Chapter 2. Double Gate Tunnel FET 15
2.2 Device structure and Operation
The device being studied is the lateral Double gate TFET. Just as the conventional
TFET, it is a gated reverse biased p+ i n+ structure which uses the principle ofgate controlled Band to Band tunneling for its operation. The schematic of the device is
shown in Fig. 2.1. To operate the device, the source is grounded, a positive voltage (1V)
is applied to the drain and a voltage is swept across the gate terminals. The operating
principle of the device is exactly the same as that of the conventional TFET and can be
explained using the band diagrams in Fig. 1.6. In the absence of the gate voltage, the
tunneling barrier width is much higher than 10nm (the approximate minimum required
for tunneling to take place in silicon). However, on application of positive gate voltage
(n-type behavior), the bands in the intrinsic region get pulled downwards and a tunneling
junction is created at the junction of the p+source and the intrinsic channel. Zenertunneling of electrons takes place from the valance band of the source to the conduction
band of the channel and the device turns on.
VDS
VGS
VGS
LCH=100nm
n+ drain i-channel p+ source
Tsi
Figure 2.1: Schematic of the DG Tunnel FET structure being investigated (Tox = 2nm)
Chapter 2. Double Gate Tunnel FET 16
2.3 Simulation Tools and Models
2D Device simulations are performed using Medici. Field dependent Kanes model [20]
for band to band tunneling available in Medici [21] was used to model the band to band
tunneling generation and recombination rate. Kanes model has been shown to give a
good match for band to band tunneling in silicon based tunnel transistors at both high
and low temperatures [9]. Since the source and drain regions are heavily doped and
tunneling is a strong function of bandgap, the bandgap narrowing model (BGN) is also
included in simulations. Also, due to high values of doping involved, the Boltzmann
approximation cannot be used to model the device. Hence, Fermi Dirac statistics are
used to improve the accuracy of the simulation at the cost of computational efficiency.
For the simulations, a fixed oxide thickness, tox=2nm is chosen. The n+ drain is doped
2x1019cm3, the p+ source is doped 1x1020cm3 and the substrate is doped 1x1016 p-type,
corresponding to the substrate doping in the standard CMOS process.
2.4 Simulations and Analysis
The transfer characteristics of the Double Gate Tunnel FET are shown in Fig. 2.2(a).
Unlike the MOSFET, there is no clear boundary between sub-threshold and saturation
regions. The output characteristics of the device are shown in Fig. 2.2(b).
As compared to the power dependence on VGS in the MOSFET, the behavior seen
here is of a much higher order. Also, gm and Ro were evaluated for IDS versus VGS at
various Drain bias. It was found that, the gm value was in the range of 109 to 107 from
sub-threshold to inversion region respectively. Ro was also evaluated from the IDS versus
VDS curves for three different VGS (1.0V, 1.2V and 1.4V) near the operating potential of
the device and was found to be of the order of 1011 for higher VDS. It was found thatthe Gm*Ro product is quite small (27) for lower values of VDS but is in the order of104 as we increase the VDS to the operating voltages. This is significantly higher when
compared to the present day MOSFET which has the Gm*Ro value in the range of 40 to
50. The variation of the Gm*Ro product with VDS and VGS for the double gate TFET
Chapter 2. Double Gate Tunnel FET 17
0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80V(Gate) (V)
-16
-14
-12
-10
-8
log(
I(Dra
in)) (
A/um
)
Vds = 0.1V Vds = 0.4V Vds = 1.0V
(a) Transfer Characteristics of the DG TFET for various values of drainvoltages
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00V(Drain) (V)
0.00
1.00
2.00
3.00
4.00
5.00
I(Dra
in) (A
/um) *
10-10
Vgs = 1.3V Vgs = 1.2V Vgs = 1.4V
L = 100nmTsi = 100nm
(b) Output Characteristics of the DG TFET
Figure 2.2: ID vs. VGS and ID vs. VDS characteristics of the DG Tunnel FET
Chapter 2. Double Gate Tunnel FET 18
can be seen in the Fig. 2.3. This feature can make the device highly suitable for analog
applications such as amplifiers and current mirrors.
0 0.5 1 1.5101
102
103
104
105
VDS (V)
Gm
Ro Pr
oduc
t
VGS =1VVGS=1.2VVGS=1.4V
Figure 2.3: The Gm*Ro versus VDS for various VGS near the operating point.
According to Kanes model [20] of BTBT, the relation for Band to Band Tunneling
current is given by Equ. 1.3. Using this relation, an expression (Equ. 2.1) for the Sub-
threshold Swing (S) of Tunnel transistors has been derived in [26]. A detailed derivation
of the equation can be seen in the appendix.
S =DVGS
2
2DVGS +BkaneWg3/2
(2.1)
This derivation is based on the following two assumptions:
1. The tunneling width () , which is gate controlled, is independent of the drain
bias, this can be seen from the band diagrams in Fig. 2.4.
2. The tunneling electric field (E) is also fairly independent of the drain bias and
can be approximated by a relation E = DVGS2, where D is a constant determined
by various device parameters such as Doping concentration (N), drain bias (VDS),
oxide thickness (tox) and channel length (L).
From Equ. 2.1, it is seen that the S of tunnel FET is a strong function of the gate
voltage (VGS). hence, the value of S is very low for lower gate voltages (sub-threshold
Chapter 2. Double Gate Tunnel FET 19
Figure 2.4: Simulated band diagrams of VTFET (near the surface region) with increasingVDS at fixed VGS=0. The tunnel barrier is nearly independent of VDS [26]
region) but degrades considerably for higher gate voltages (saturation region). Fig. 2.5
shows the variation of S as a function of the gate voltage for the double gate tunnel FET.
However, it is observed that the the assumptions made to derive Equ. 2.1 are true
only in the surface region (the region very close to the oxide channel interface) of the
device where the bands bend under the effect of the gate workfunction. In the bulk
region, since the intrinsic channel if fully depleted, the bands in the channel are straight
lines (Fig. 2.6) as compared to the curved bands in case of surface region. Therefore, as
clearly seen in Fig. 2.6, the tunneling width () in the bulk region reduces considerably
with an increase in drain bias.
It is also observed (Fig. 2.7) that the tunneling electric field (E) is fairly constant
with respect to VDS in the surface region but increases linearly with the drain bias in the
bulk region. Since the effect of gate is negligible in the deep seated region of the device,
this region is responsible only for the off-state current (IOFF ) of the device. Thus, the
reduction in and an increase in E with an increase in the drain bias should lead to
an increase in the IOFF of the device. As a result of that, the ION/IOFF ratio should
Chapter 2. Double Gate Tunnel FET 20
0 0.5 1 1.50
50
100
150
200
250
VGS
S.S.
(mV/
deca
de) L=100nm
TSi=100nm
Subthresholdregion
Figure 2.5: Point Sub-threshold swing (S) of DG Tunnel FET as a function of the gatevoltage. (VDS=1V). S degrades considerably as the device moves from sub-threshold tosaturation region
Figure 2.6: Simulated band diagrams of DGTFET (in the bulk region) with increasingVDS at fixed VGS=0. Tunneling barrier reduces significantly due to increase in VDS
Chapter 2. Double Gate Tunnel FET 21
0 0.5 1 1.5 20.1
0.12
0.14
0.16
0.18
E.BU
LKM
AX (M
V/cm
)
0 0.5 1 1.5 21
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
VDS (V)
E.SURFACEM
AX (MV/cm)
EBULKESURFACE
Figure 2.7: Simulated maximum electric field Emax, across the tunnel junction as afunction of VDS in the bulk and surface regions of the device. the field is independent ofVDS at the surface but increases linearly with drain bias in the bulk region.
degrade at higher VDS
We also need to note that Equ. 2.1 does not take into account the variation of
and E with respect to VDS in the bulk region. Hence, the value of S predicted by this
equation will not be very accurate. Also, one should keep in mind that this (deviation)
happens only at higher drain voltages. The obtained values of S agree very well with
expected values at low drain bias. Fig. 2.8 shows the variation in the minimum point
sub-threshold swing (Smin) and ION to IOFF ratio with VDS for a fixed device. For
very low drain voltages (below 0.4V), ION of the device is very low and as a result,
the ION/IOFF ratio is not very good. The device shows excellent parameters for VDS
between 0.4 and 1.2V. However, as we increase the drain bias above this value, both
these parameters degrade drastically.
From the analysis above, we can conclude that significant reduction in IOFF of the
device can be achieved without affecting the ION if the thickness (TSi) of the device is
reduced.
The above conclusion of was verified using 2D device simulations in Medici. The
thickness of the double gate structure in Fig. 2.1 was varied and the results noted down.
It was found that ION/IOFF ratio and the sub-threshold swing improved considerably
Chapter 2. Double Gate Tunnel FET 22
0 0.5 1 1.5 2105
1010
1015
I ON/
I OFF
0 0.5 1 1.5 20
20
40
60
80
100
120
VDS (V)
SM
IN (mV/decade)
ION / IOFFSMIN
L=100nmT
si=100nm
Figure 2.8: Simulated ION to IOFF ratio and minimum point sub-threshold swing as afunction of VDS. As predicted, both the values degrade a lot at higher drain bias
0 20 40 60 80 100108
109
1010
1011
1012
1013
I ON/
I OFF
0 20 40 60 80 1000
20
40
60
80
100
120
Tsi (nm)
SM
IN (mV/decade)
ION / IOFFSMINVDS = 1V
L = 100nm
Figure 2.9: Simulated ION to IOFF ratio and minimum point sub-threshold swing as afunction of TSi. As expected, both the parameters improve when the body thickness isreduced
Chapter 2. Double Gate Tunnel FET 23
for the thin body device when compared to the thicker structure. Fig. 2.9 shows the
improvement in device behavior with reduction in TSi. The ION/IOFF is seen to degrade
for TSi less than 10nm. This is because for very thin structures, the on-current (at
VGS=1.5V) starts to drop (due to the reduction in cross sectional area). Hence, there is
a maximum in the ION/IOFF vs TSi curve at TSi 10nm.
2.5 Floating Body Effect
Unlike the conventional transistor, where there is a high field at the reverse biased drain
substrate junction, in TFET, the high field region is the tunneling junction which is
formed near the source channel junction. Also, the barrier between the p-type channel
and the p+ source is negligible (compared to the p-n+ barrier in case of a MOSFET).
Because of these reasons, any charge that is generated, gets flushed out through the
source straight away. Thus, there are no floating body effects in the double gate Tunnel
Field Effect transistor.
2.6 Scaling of Double Gate TFET
As we have seen, the active region of the TFET is only the tunneling junction between
the source and the intrinsic region of the structure. as a result, the device performance
is nearly independent of channel length. this was verified using 2D device simulations.
It was found that the main device parameters (namely the sub-threshold swing and
ION/IOFF ratio) were found to remain unchanged upto a channel length of 30nm. How-
ever, the parameters degraded below this value of the channel length. This is because
the gate length is too less and as a result, the gate is not able to bend the bands enough
for conduction to take place. Fig. 2.10 shows variation in log10(IDS) vs VGS curves with
channel length.
Chapter 2. Double Gate Tunnel FET 24
0.00 0.50 1.00 1.50 2.00 2.50 3.00V(Gate) (V)
-15
-10
-5
log(
I(Dra
in)) (
A/um
)
L = 20nm L = 30nm L = 50nm L = 100nm
Vds = 1.0V
Figure 2.10: Simulated ID vs VGS characteristics of the DG Tunnel FET with differentchannel lengths. The characteristics start deviating from normal when the Length is20nm or lower
2.7 Conclusion
In this work, the Double Gate TFET was explored using 2D device simulations. Due to
the tunneling mechanism involved in its carrier transport, unlike the MOSFET, TFET
does not have any physical lower limit to the sub-threshold swing. Also, due to the
reverse biased structure, the leakage current is extremely low. Both these properties
make the TFET highly suitable for Low-Standby Power applications. It is observed that
the bulk of the device plays a major role in degrading the ION/IOFF ratio and the S of
the device. Using simulations, it is verified that both these parameters can be improved
by reducing the thickness (and hence the amount of bulk region) of the device. It is also
seen that the TFET performance is nearly independent of the channel length and the
device (in its present form) can be easily scaled upto 30nm channel lengths.
Chapter 3
Tunnel FET with SiGe layer at
Source
3.1 Introduction
As we have seen in the earlier chapters, due to extremely low IOFF and excellent switch-
ing characteristics, the Tunnel Field Effect Transistor (TFET) has attracted a lot of
attention for Low Stand-by Power (LSTP) applications. However, in spite of excellent
sub-threshold swing and high ION/IOFF ratio, the very low ION is the main issue with
this device.
Previously reported Tunnel FET designs either suffer from low ION [14] (due to the
reverse biased pin structure and high bandgap of silicon) or involve complex fabrication
process steps [15].
Recently, ON current improvement has been reported using HK gate dielectric [27].
However, it does not take into account the mobility degradation related to High- ma-
terial, gate dielectric breakdown due to high field across the very thin high- material
and fabrication issues involved.
In this work, a new classical MOSFET alike Tunnel FET architecture is proposed,
which offers sub-60mV/decade sub-threshold swing with a significant improvement in
ION . The enhancement in ION is achieved by introducing a thin SiGe layer on top
25
Chapter 3. Tunnel FET with SiGe layer at Source 26
of the Silicon Source. With the help of TCAD simulations, it is demonstrated that the
proposed device is naturally immune to short channel effect (SCE) and can be fabricated
with standard CMOS process steps. It is observed that the body bias does not affect the
drain current but the body current gets affected. Another original finding is that the
introduction of SiGe layer makes the device immune to Drain induced Barrier lowering
(DIBL) effect and the ION increases exponentially with Ge mole fraction. It is noted that
if proposed architecture is coupled with high- material (as proposed in [27]) additional
boost in drive current can be achieved with a thicker gate dielectric.
3.2 Device Structure and Operation
The device being investigated is a lateral n-type Tunnel FET with a SiGe layer on the
top of the source. The Tunnel FET is a gated reverse biased p+ i n+ structurewhich uses the principle of gate controlled band to band tunneling for its operation. The
proposed device is shown in Fig. 3.1
DRAIN
GATE
n+ Si p+ Si
Ptype Si Substrate
A
SOURCE
strained SiGe Layer (depth=Ld)
BXj=40nm
Figure 3.1: Schematic of the proposed n-type TFET structure with SiGe layer at Source.For all simulations, tox = 2nm, drain doping(n+) = 5 x 10
19 and source doping(p+) = 1x 1020 was used. Germanium mole fraction (x) was varied from 0.0 to 0.5 in steps of 0.1
To operate the device, the p+ source is grounded, a positive voltage (1V) is applied
to the n+ drain and a voltage is swept across the gate. The simulated band diagrams
are shown in Fig. 3.2. In the absence of a gate voltage (non-conducting region), the
tunneling barrier height is much higher than 10nm (the approximate minimum required
Chapter 3. Tunnel FET with SiGe layer at Source 27
for tunneling to take place in silicon). However, on application of positive gate voltage,
the bands in the intrinsic (lowly doped) region are pulled downwards and a tunneling
junction is created at the junction of the p+- source and the intrinsic channel. Due to the
reduction in tunneling width and electric fields produced, zener tunneling of electrons
takes place from the valance band of the source to the conduction band of the channel
and the device turns ON. One should note that this behavior is exactly same as the
NMOS in the CMOS technology. Hence, this can be called as an n-type tunnel FET.
0.2 0.25 0.3 0.35 0.4 0.45 0.52.5
2
1.5
1
0.5
0
0.5
1
1.5
Ener
gy (e
V)
Distance (m)
VGS = 0V
VGS = 2V
e
p+ sourcep channeln+ drain
EC
EVVDS =1.0V
Figure 3.2: Simulated band diagrams (along the cut section AB in Fig. 3.1) of the n-type TFET in non-conducting and conducting regions. The large reverse biased barrierinsures extremely low IOFF
For a Tunnel FET, the ON current is proportional to the electron/hole transmission
probability T(E) in the Band to Band tunneling mechanism, which is given by [24]:
T (E) = exp
( 4
2mEg
3/2
3|e|~(Eg +)Siox
toxtSi
) (3.1)
where, m is the carrier effective mass, e is the electron charge, Eg is the bandgap,
is the energy range over which tunneling can take place, and tox,tSi,ox and Si are the
oxide and silicon film thickness and di-electric constants, respectively.This equation shows
Chapter 3. Tunnel FET with SiGe layer at Source 28
that decreasing oxide thickness (tox) [26], increasing oxide dielectric constant (ox),and
reducing bandgap (Eg), will enhance the performance of the device. Boucart and Ionescu
[27] have proposed the use of High- materials as the gate dielectric (high ox in Eq. 3.1)
in order to increase ON current (ION). In this work, ION enhancement has been done
by modulating the bandgap (Eg) by using a strained SiGe layer at the source end and
varying its germanium mole fraction (x). As the electron/hole effective mass m does
not change too much with mole fraction (x), its impact on ION could be ignored.
The device performance is sensitive to the doping concentration of source and abrupt-
ness of doping profile at source-channel interface [14]. The doping of source, substrate
and drain regions chosen to optimize ION respectively are 1 x 1020 , 1 x 1016 and 5 x 1019
cm3 . Device performance is very sensitive to Gate work function as reported in [26],
but we have used n+ Polysilicon compatible to CMOS process flow for gate material. A
constant oxide thickness (tox = 2nm) and channel length (L = 100nm) is chosen for all
simulations.
3.3 Simulation Models and Device Parameters
2D Device and process simulations were performed in Medici[21] and Tsuprem4[22] re-
spectively. Field dependent Kanes model[20] available in Medici is used to model the
band to band tunneling generation and recombination rate. Kanes model has been
shown to give a good match for band to band tunneling in silicon based tunnel transis-
tors at both high and low temperatures[9]. Since the source region is heavily doped, and
tunneling is a strong function of bandgap, the bandgap narrowing model (BGN) is also
included in the simulations. Fermi Dirac statistics, although they are computationally
less efficient, are used instead of Boltzmann approximations for the same reason.
The BTBT model in Medici is configured in such a way that it uses the average
tunneling field while solving the pre-exponential and the path integral field while solving
the exponential in the tunneling rate. Also a recursive refinement procedure is used that
further improves the accuracy of the simulations. Also, non local tunneling is enabled
Chapter 3. Tunnel FET with SiGe layer at Source 29
which causes the electrons to be generated at the end of the tunneling path as implied
by the tunneling physics.
A small aside on how the device characteristics, namely the subthreshold swing, VTH
and the ION , are calculated. Unlike the MOSFET, where there is a clear transition from
the sub-threshold to the saturation region when plotted on the semilog scale, in TFET
the slope (of log10ID) is an exponential function of VGS. The slope is very steep for
lower VGS but becomes less and less steeper as the gate voltage increases. Therefore, the
threshold voltage cannot be extracted using the standard MOSFET techniques. Hence,
as discussed in [25] VTH is calculated by a constant current method at IV T= 107A/m.
The average subthreshold swing is extracted by taking the average between the gate
voltage at which the ID begins to increase and the threshold voltage. This method has
been explained in detail earlier by [26] and [27] and is considered to be a consistent way
to define S for TFETs. ION is calculated at VGS = VDS = 1.2V as per the voltages
specified by ITRS for LSTP applications at the 65 nm node.
All results obtained fromMEDICI are also verified using ATLAS [29], version 5.12.1.R,
using the nonlocal Hurkx band-to-band tunneling model [30]. It is found that the simu-
lations show exactly same trend with slightly lower IOFF in the case of ATLAS. However,
in this work, we report results which are obtained from MEDICI.
3.4 Results and Discussion
3.4.1 The SiGe layer
As discussed earlier, a SiGe layer is introduced at the top of the source in the conventional
Tunnel FET to achieve an improvement in the ON state current. Fig. 3.3(a) shows the
effect of varying the Germanium molefraction in the equilibrium band diagrams of the
proposed device. As expected, the Bandgap at the source end reduces as we increase
the Ge molefraction (x). This results in a reduction in the tunneling bandgap and
consequently an increase in the Transmission probability in Equ. 3.1 which in turn,
increases the BTBT current. Fig. 3.3(b) shows how the bands vary under the effect
Chapter 3. Tunnel FET with SiGe layer at Source 30
0.25 0.3 0.35 0.4 0.451.5
1
0.5
0
0.5
1
1.5
Distance (m)
Ener
gy (e
V)x=0.0x=0.2x=0.5Fermi level
(a) Equilibrium Band diagrams of the proposed TFET structure for variousvalues of Ge mole fraction (x)
0.25 0.3 0.35 0.4 0.453
2
1
0
1
Distance (m)
Ener
gy (e
V)
VDS=0VVDS=1.5V
x=0.5VVGS= 0V
(b) Effect of Drain voltage on the device band diagrams. It is seen that thetunneling width remains nearly independent of the applied drain bias. Thusinsuring high immunity to DIBL
Figure 3.3: Simulated Band Diagrams of the proposed Tunnel FET architecture in Fig.3.1 along the cut section (AB)
Chapter 3. Tunnel FET with SiGe layer at Source 31
0 0.5 1 1.5 2
109
106
103
100
103
VGS(V)
I D(A
/m
)
VDS=1.0VVDS=0.1V
x=0.0x=0.2
x=0.5x=0.3
(a) Simulated transfer characteristics of the device for various values of Gemole fraction (x) for linear and saturation VDS .
0 0.5 1 1.5 2
1
2
3
4
5
6
7
VDS (V)
I D (A
/m
)
VGS=1.2VVGS=1.3VVGS=1.4V
x = 0.1
(b) Output characteristics of the TFET with SiGe layer at the Source end.
Figure 3.4: Simulated Device characteristics for the proposed device
Chapter 3. Tunnel FET with SiGe layer at Source 32
of Drain bias. As can be seen there is negligible change in the tunneling bandgap with
increase in VDS. This means that the device should be immune to Drain Induced Barrier
Lowering (DIBL).
The Transfer and Output characteristics of the proposed device are shown in the Fig.
3.4. As expected, in Fig. 3.4(a) we observe that, the over all drain current and specially
the ON current increases as we increase the germanium mole fraction. Fig. 3.4(b) shows
the output characteristics of the device. Due to the reverse biased p-i-n structure, the
output impedance of the device is very high. This is also seen in the IDS vs. VDS curves
where the drain current current is almost constant in the saturation region.
In accordance with Equ.3.1, we observe in Fig.3.5 that, the increase in ION is ex-
ponentially dependent on the reduction in Eg (which reduces linearly with increase in
germanium mole fraction (x)). Also, this increase in ION leads to a reduction in the
average subthreshold swing of the device since now the threshold voltage falls in the
steeper region of the curve. An ION of 580A/m, IOFF of 1.04fA/m and an average
S of 13mV/decade are achieved for x=0.7 with VDD=1.2V
0 0.1 0.2 0.3 0.4 0.5 0.60
20
40
60
80
100
120
Subt
hres
hold
Sw
ing
(mV/
dec.)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.70
100
200
300
400
500
600I O
N(A
/m
)
Ge Mole Fraction (x)
S.S.ION
VDS=1.2VVGS=1.2VLD=20nm
Figure 3.5: The avg. sub-threshold swing (S) and ION vs. x. ION increases exponentiallywith x. However, the IOFF remains in the order of fA (IOFF= 1.04fA/m at x = 0.7)
Chapter 3. Tunnel FET with SiGe layer at Source 33
Figure 3.6: A zoomed view of the tunneling junction of the TFET. 2D simulations showthat the band to band generation is limited to the top 20nm layer of the device (whenit is biased in the operating region)
3.4.2 Depth of SiGe Layer (Ld)
The conventional TFET is a surface tunneling device and the active region of the de-
vice is situated right at the surface near the channel-source junction. From 2D device
simulations, it is observed that the band to band generation rate is maximum at the
surface and has some practical value only in the top 20nm layer of the device (Fig. 3.6).
Therefore, it is believed that increase in ION can be achieved by reducing bandgap only
in this 20nm region right below the surface. This fact is verified in Fig. 3.7 where we
observe that the ION of the device increases as we increase the depth of SiGe (Ld) layer to
20nm but does not increase further as we increase Ld beyond this value. Any additional
increase in the SiGe layer depth only causes an increase in the IOFF of the device. It is
also observed in Fig. 3.7 that the effect of Ld becomes more prominent as the value of
the mole fraction (x) is increased.
3.4.3 Effect of Body bias
Since the investigated device is a p+-pn+ structure, unlike the MOSFET, there is ap+-p junction between the source and the body. As a result of this, there could be a
Chapter 3. Tunnel FET with SiGe layer at Source 34
0 5 10 15 20 25 300
100
200
300
400
500
600
Depth of SiGe Ld(nm)
I ON(
A/
m)
x=0.1x=0.3x=0.5x=0.7
Figure 3.7: ION as a function of the depth of SiGe layer (Ld). ION increases with anincrease in Ld up to a depth of 20nm. increasing Ld beyond this value does not help inincreasing ION as it falls beyond the active region of the device
direct path (short circuit) between these two terminals depending on body bias. Hence,
application of a body bias does not affect the ID-VGS characteristics of the device. On
the contrary, it adds up a large leakage current (of the order of A) component from the
bulk to the source (Fig. 3.8). It is observed that this current component is more in case
of negative body voltage as the p-p+ junction is forward biased in that case.
3.4.4 SCE and DIBL
The active region of the TFET is only a very small region near the surface at the channel
source interface. This, along with the large reverse biased barrier, makes the TFET a
highly scalable device. It has been shown that the device can be scaled up to channel
lengths as small as 30nm without affecting its performance. Fig. 3.9 shows the effect
of channel length and drain bias on the threshold voltage (VTH) of the device. VTH
values, which are quite high for x=0, agree well with ITRS requirements [23] for higher
values of x. Also, it is observed that there is virtually no DIBL for higher values of x
Chapter 3. Tunnel FET with SiGe layer at Source 35
0 0.5 1 1.5 2
1200
1000
800
600
400
200
0
I BUL
K (A
/m
)
0 0.5 1 1.5 2
106
102
102
VGS (V)
ID (A/
m)
VBS= 0.8V
VBS= 0.5V
VBS= 0.3V
VBS= 0.1V
(a) Effect of negative body bias
0 0.5 1 1.5 2
8
10
12
14
16
VGS (V)
I BUL
K (A
/m
)
0 0.5 1 1.5 2
106
102
102
ID (A/
m)
VBS=0.1V
VBS=0.3V
VBS=0.5V
VBS=0.8V
(b) Effect of positive body bias
Figure 3.8: Effect of Body bias on device performance. The ID-VGS characteristicsremain un-altered but the bulk current increases linearly with increase in bulk terminalpotential.
Chapter 3. Tunnel FET with SiGe layer at Source 36
(above x=0.3). This is because, the barrier height (which is directly proportional to the
tunneling bandgap) is a much stronger function of x than VDS. Therefore, as we increase
the mole fraction, the lowering of bandgap by x dominates the lowering of bandgap by
VDS.
0 50 100 150 2000
0.5
1
1.5
Channel Length (nm)
Thre
shol
d Vo
ltage
(V)
VDS=0.1VVDS=1.0V
x=0.0
x=0.3
Figure 3.9: SCE and DIBL in the proposed device. A reduction in VTH (as a result ofreduction in barrier height) is seen with an increase in x. DIBL also disappears with anincrease in x
3.4.5 High material as gate dielectric
In [27], the use of High materials to improve the ION of the device has been reported.
The thickness of the dielectric material needed to achieve this improvement in ION is very
small (3nm). It may not be practical to use such thin HK dielectric as their breakdown
voltages are much smaller compared to SiO2. However, if the same technology is used
with the proposed TFET design, it is possible to achieve very good ION even for a
thicker, more realistic physical dielectric thickness (5nm). Fig. 3.10 shows the transfer
characteristics comparing the two devices with different dielectric constants (HfO2 and
SiO2) for two different values of germanium mole fractions. It is seen that a very high
Chapter 3. Tunnel FET with SiGe layer at Source 37
ION (nearly 1mA/m) can be achieved if both the techniques are combined.
0 0.4 0.8 1.2 1.6 2
109
106
103
100
103
VGS (V)
I D (A
/m
)
HfO2,x=0.0HfO2,x=0.3SiO2,x=0.0SiO2,x=0.3
VDS=1.0V
Figure 3.10: Combination of High (=29) along with the SiGe layer at the sourceend helps in achieving much better ION and sub-threshold swing for realistic physicalthickness. Tdielectric = 5nm in this case. IOFF= 19.79pA/m for High K dielectric withx = 0.3
3.4.6 Effect of Strain on the channel
The reasons behind adding the SiGe layer only to the source region are twofold. First, the
active region of the device is located only at the source-channel junction and the drain
voltage does not play any role in BTBT tunneling. Second, adding SiGe to the drain
also would add strain to the channel from both sides. This strain in the channel may
increase/reduce the carrier mobility. Therefore, it is very difficult to predict the effect of
stress and requires further investigation. In fact the proposed device will operate with
same efficiency if we use fully Silicon-Germanide source instead of SiGe layer on the top
of a Si Source. However, we propose SiGe layer source in order to minimize the effect of
stress on the silicon channel. The effect of strain on the Si channel is not considered in
this work due to non availability of proper models in the simulator.
Chapter 3. Tunnel FET with SiGe layer at Source 38
0.3 0.4 0.5 0.6 0.70.5
0.6
0.7
0.8
0.9
Ge Mole fraction (x)
Ban
d G
ap (e
V)
Strained SiGeRelaxed SiGe
Figure 3.11: Band gap of strained SiGe and Relaxed SiGe for different values of Ge molefraction. Strain tends to reduce the band gap and thus helps in improving ION
3.4.7 Effect of Strain on on SiGe layer
The effect of strain on SiGe bandgap is shown in Fig. 3.11. The band gap values are
extracted from 2D simulations in Medici. It is observed that strain tends to reduce the
band gap of the SiGe layer. This further helps in improving the ION of the device. Thus,
it is desirable to have a strained SiGe layer at the source.To obtain 20nm or more thick
layer of strained SiGe over Si with Ge mole fraction x=0.7 is a challenging technology
problem (it can be obtained by growing over relaxed SiGe) [31]-[32].However, the same
ION can be obtained with lower Ge mole fraction by decreasing tox (compromising with
gate leakage).
3.4.8 Lateral vs. Vertical TFET
The concept of using the SiGe layer in the proposed device is the same as in the Vertical
channel TFET proposed in [15] (i.e. to improve the ION of the device). However, there
are a few differences in the two structures which cause the effect of the SiGe layer to
Chapter 3. Tunnel FET with SiGe layer at Source 39
be slightly different for the device proposed here. The main difference between the
structures is that the VTFET proposed in [15] is very much like a vertical form of the
double gate TFET in chapter 2 with the thin SiGe layer spread all across the channel.
Thus, there is a reduction in the bandgap all across the junction of source and channel.
As we had seen in the 2nd chapter, the bulk region plays a major role in determining
the off state current of the device. Thus, since the SiGe layer is placed all across the
channel, the off state current too goes up significantly with an increase in the germanium
mole fraction. As a result, additional techniques such as gate work function modulation
are needed to reduce the off state current [26]. In the lateral device proposed over here,
the bandgap reduction occurs only at the tunneling junction and thus only results in
an increase in the ION without affecting the IOFF by much. Thus, there is no need of
additional changes in the gate material.
3.5 Fabrication of The Proposed Device
A process flow compatible with standard CMOS process to fabricate the proposed Tunnel
FET with SiGe layer was designed using 2D Process simulations in Tsuprem4 [22]. The
device can be fabricated with slight modifications in the standard CMOS process flow
after Gate stack formation. The following main changes are needed for fabricating the
proposed device:
1. A new set of masks is needed to incorporate a n+ drain and a p+ source in the
same device. (unlike the conventional NMOS where we had n+ in both source and
drain regions.)
2. To get the SiGe layer at the source, additional steps of isotropic etching of Si and
epitaxial deposition of SiGe are needed.
Chapter 3. Tunnel FET with SiGe layer at Source 40
3.5.1 Description of Process steps
Fig. 3.12 shows the device in various stages of process simulation. Here we show only
those steps which are different from the standard CMOS steps. Fig. 3.12(a) shows
the photoresist mask necessary to dope the n+ drain and gate regions. This doping
is achieved by Ion implantation of Arsenic followed by annealing. An active doping of
approx. 5 x 1020 cm3 has been achieved. After the gate and drain doping, the another
mask is prepared which covers these two regions and with the help of this mask, silicon in
the source region is etched away (Fig. 3.12(b)). This is followed by epitaxial deposition
of Boron doped p+ silicon. As shown in Fig. 3.12(c), this deposition is only partial and
does not form the full source. The rest of the source (the SiGe layer) is deposited using
epitaxy of Boron doped silicon with germanium (Fig. 3.12(d). The epitaxy process helps
in achieving abrupt doping profile at the source end which has been shown to achieve
better ION for the silicon TFET [28].
3.5.2 Impact of Mask Misalignment
As we have seen, a set of two complimentary masks is required to fabricate the tunnel
FET with SiGe layer. During these photo steps, it is inevitable to have an overlay
error. The effect of mask alignment on the conventional Tunnel FET performance has
already been studied by T. Nirschl et al for the 130nm technology [33]. Here, the authors
consider the ION to IOFF ratio as the performance benchmark for the device. In this
study, the authors have reported that, the mask misalignment improves the performance
of the TFET when there is a positive overlap (i.e. the photoresist mask covering initially
covering only the source is shifted slightly towards the drain side and now partially covers
the Gate). However, the performance degrades when there is a negative overlap (referred
as underlap from here onwards) (i.e. the photo-resist is shifted away from the drain and
does not fully cover the source). For the proposed device, an underlap would be even
more depreciating in terms of its performance as it would mean that there is no SiGe at
the tunneling junction.
Chapter 3. Tunnel FET with SiGe layer at Source 41
(a) Drain and Gate doping mask used for Ion im-plantation
(b) Mask used for etching the Source. The maskleaves some part of the gate partially open to avoidGate to Source underlap due to process variations.Xj=40nm
(c) Partial deposition of p+ Source (upto 20nm)using epitaxy with Boron as impurity
(d) Deposition of p+ SiGe layer on top of the p+
source using epitaxy with Boron as impurity
Figure 3.12: Modifications needed in the standard CMOS process flow to fabricate theproposed Tunnel FET structure
Chapter 3. Tunnel FET with SiGe layer at Source 42
According to the 2006 ITRS update [23], a variation of 10nm is expected in thepresent day lithography techniques. This much underlap is enough to degrade the per-
formance of the tunnel FET with SiGe layer and limit its ON current to lower than
or equal to the conventional TFET. Therefore, it is advisable to start with an initial
positive overlap of 10nm so as to avoid an underlap. (Fig. 3.13)
Figure 3.13: The Photoresist mask covering the p+ source is made to overlap the gateby 10nm in the beginning so as to cancel out any chance of an underlap being formeddue to mask overlay
This would mean that there would be a worst case positive overlap of 20nm (assum-ing a 10nm variation of the mask in the other direction. This would result in a structure
in which a part of the gate is p+ SiGe and causing a shift in the net work function of the
gate. The net work function calculated by averaging the work functions of each of the
regions shows a good match with actual data [33]. The effect of Gate work function has
been discussed in [26] and shows that an increase in gate function would result in a slight
reduction in the ON state current but an improved average sub-threshold swing of the
device and much more improvement in IOFF . Hand calculations show that the net in-
crease in work function for a 100nm long gate is about 0.044eV (from 4.17eV to 4.214eV)
and simulations show that there isnt any noticeable change in the device characteristics.
3.6 Conclusion
A novel Silicon Tunnel FET architecture with SiGe layer at source is proposed and
analyzed using 2D device simulations. The proposed device is nearly free of SCE and
Chapter 3. Tunnel FET with SiGe layer at Source 43
DIBL and can be scaled upto channel lengths of 30nm. The proposed device shows orders
of improvement in ON current over the conventional TFET with the added advantage of
compatibility with CMOS fabrication steps. A process technique to fabricate the device
is also designed using 2D process simulations.
Chapter 4
Conclusion and Scope of Future
work
In this work, we have discussed the shortcomings of the present day MOSFET as a
switching device and how it adversely affects the Low Stand-by Power applications such
as mobile phones, PDAs etc. These shortcomings of the MOSFET are essentially due
to the drift diffusion mode of carrier conduction which limits its sub-threshold swing to
a minimum of 60mV/decade at the room temperature. The only way to overcome this
physical limit is to change the mode of carrier conduction of the device.
Among the available alternatives, the Tunnel Field Effect Transistor (TFET), which
is based on the principle of gate controlled interband tunelling, appears to be the most
promising device. We have seen that there is no theoretical lower limit of the sub-
threshold swing for TFET and also due to the reverse biased p-i-n structure, it has very
low IOFF and is naturally immune to the Short Channel Effect (SCE). However, in spite
of excellent sub-threshold characteristics and very low IOFF , the device fails to meet the
technology requirements of ION and that is the main issue with this device.
2D device simulations are used to gain some insight into the device behavior. It
is seen that the active area of the device is a very small area near the gate oxide at
the channel source interface and the bulk region contributes only to the IOFF . To
overcome the problem of low ION , we have proposed a novel TFET architecture (with
44
Chapter 4. Conclusion and Scope of Future work 45
a strained SiGe layer at the source) which can be fabricated with slight modifications in
the standard CMOS process flow and shows orders of improvement in the ON current
of the device. It is found that the proposed device is scalable up to channel lengths as
small as 30 nm without affecting its performance. Also, the effect of DIBL reduces as
we increase the Ge molefraction (x) and in fact, it nearly reduces to zero for x 0.3.Since, TFET is a surface conduction device, the depth of strained SiGe layer needed to
achieve the improvement in ION is very less ( 20nm). It is also seen that the body biashas very little impact on the device performance and the VT is purely dependent on the
oxide thickness, doping at source and the gate workfunction. In the end, to fabricate
the proposed device, a process flow compatible with the standard CMOS process steps
is also designed using 2D process simulations.
Working on this thesis has exposed a couple of other issues about the Tunnel FET
which need to be addressed before it can actually be used in commercial circuits.
4.1 Process Challenges
As discussed earlier in Chapter 3, the fabrication of the proposed Tunnel FET with a Ge
rich strained SiGe layer of 20 nm thickness is a challenging proposition for the process
engineer. Growing a strained SiGe layer over a relaxed SiGe layer is an alternative but
that makes the process much more complex and time consuming. Also, Boron is used as
the impurity for the p+ source and it has a very high diffusivity in silicon. Because of this
boron diffusion, the source region extends to some distance under the gate. However,
the SiGe layer which is deposited epitaxially does not form an overlap with the gate. As
a result of this, the tunneling junction is formed slightly away from the Si-SiGe interface
and consequently, the advantage of using the SiGe layer is lost. Thus, the key process
challenges are to deposit a 20nm thick SiGe layer and to avoid/minimise the Borondiffusion at the source.
Chapter 4. Conclusion and Scope of Future work 46
4.2 Pass Transistor Behavior
The Tunnel FET being a gated p-i-n diode is not a symmetrical structure like the con-
ventional MOSFET. Therefore, its performance as a pass transistor is a questionable as
the diode will always conduct in the other direction (irrespective of the potential at the
gate terminal). A pass transistor is a major building block when it comes to CMOS
circuits. Hence, if the Tunnel FET has to replace the conventional MOSFET, this is an
issue which needs to be resolved.
Appendix A
Sub-threshold Swing of Tunnel
Transistors
According to Kanes model [20] of band to band (B2B) tunneling, the B2B generation
rate is given by
GB2B = AKaneE2Wg
1/2eBKaneWg3/2/E (A.1)
where Akane and Bkane are material dependent constants, E is the electric eld at the
tunneling junction.
It is found that, at high values of VGS , E is nearly independent of VDS.
Therefore, we can say that E = DVGS,
where, D is a function of drain bias (VDS), channel doping (N), oxide thickness (tox )
and channel length (L).
D = f(VDS, N, tox, L) (A.2)
Since, IDSGB2B,
IDS = AKane(DVGS)2Wg
1/2eBKaneWg3/2/(DVGS) (A.3)
47
Appendix A. Sub-threshold Swing of Tunnel Transistors 48
Taking logarithm on both sides, we get
ln(IDS) = lnAKaneD
2(VGS)2
(Wg(1/2) BKane(Wg)
3/2
DVGS(A.4)
Differentiating both sides w.r.t. VGS ,
d(ln(IDS))
dVGS=
2DVGS +BKane(Wg)3/2
D(VGS)2(A.5)
S =dVGS
d(ln(IDS))=
D(VGS)2
2DVGS +BKane(Wg)3/2(A.6)
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