Power Management - AndroBenchcsl.skku.edu/uploads/ICE3028S13/16-power.pdfDevice Power States...

transcript

Jin-Soo Kim (jinsookim@skku.edu)

Computer Systems Laboratory

Sungkyunkwan University

http://csl.skku.edu

Power Management

ICE3028: Embedded Systems Design (Spring 2013) – Jin-Soo Kim (jinsookim@skku.edu) 2

Why Low-Power?

▪ Battery life

▪ Thermal issues (cooling, reliability)

▪ Environment

Power Basics (1)

▪ CMOS Power management fundamentals

𝐸 = 𝐶𝑉𝑑𝑑2𝑓𝑐 + 𝐼𝑠𝑐𝑉𝑑𝑑 + 𝐼𝑙𝑘𝑔𝑉𝑑𝑑 𝑑𝑡

Total Energy Consumption

Capacitive Power Dissipation (dynamic) – most dominant

Leakage Power Dissipation (static)

Short-circuit Power Dissipation (dynamic)

Power Basics (2)

To minimize 𝐼𝑠𝑤𝑖𝑡𝑐ℎ

To minimize 𝐼𝑙𝑘𝑔

• Reduce voltage • Reduce frequency • Clock gating • Reduce switched capacitance

• Reduce voltage • Power gating • Less leaky transistors

To minimize 𝐼𝑠𝑐

• Reduce voltage • Reduce frequency • Clock gating • Transistors with

shorter rise/fall time

Power Reduction Strategies

▪ Circuit-level

• Transistor technology that reduces power draw

▪ Architectural-level

• Hardware optimizations to make code execute more efficiently

▪ Software

• Compilers – optimize for more efficient code

• OS – dynamic voltage/frequency scaling

Example

▪ CompuLab’s fit-PC2

• Intel 1.6GHz Atom Z530 CPU + US15W chipset

• 1GB DRAM, 60GB HDD

• Six USB ports, Gbit Ethernet, Wi-Fi, …

• 115x101x27 mm

Example: Observations

▪ Gap b/w advertised vs. measured results

▪ Large constant power consumption

• 66%~81% of total system power consumption

• Less benefit of dynamic power management

▪ Substantial power consumption in non-CPU and non-chipset components

• Combined TDP (Thermal Design Power) for Intel Z530 and its US15W chipset is 5W

Power Managed SoC Example

Source: ARM

ARM big.LITTLE (1)

▪ Cortex-A7

• In-order, dual-issue processor

• 8 ~ 10 pipeline stages

• Low performance, but power efficient

ARM big.LITTLE (2)

▪ Cortex-A15

• Out-of-order, triple-issue processor

• 15 ~ 24 pipeline stages

• High performance, high energy consumption

ARM big.LITTLE (3)

ARM big.LITTLE (4)

▪ Cortex-A7 vs. Cortex-A15

ARM big.LITTLE (5)

▪ Advanced Configuration & Power Interface

▪ First released in 1996 by Compaq/HP, Intel, Microsoft, Phoenix, and Toshiba

▪ A standard interface for computer system power and configuration management

▪ Decisions managed through the OS

ACPI Power State Transition

Global System States

▪ G-states:

State Name Description

G0 Working Normal operating mode. The performance state of CPUs (Px) and power state of devices (Dx) can be managed.

G1 Sleeping No applications executed. Several sleep states (Sx) available.

G2 Soft Off Power-off state

G3 Mechanical Off Power-off with electrical disconnection

Sleep States

▪ S-states:

State Description

S0 Full On: Processor operating. Individual devices may be shut down or be placed into lower power states to save power.

S1 Lowest waking latency. All system context is maintained by hardware.

S2 CPU and cache state is lost. The OS is responsible for storing and restoring them.

S3 Suspend-to-Ram: Power down more internal units. Some I/O paths are unavailable. DRAM state is still maintained.

S4 Suspend-to-Disk: “Hibernate mode” All system states are stored to nonvolatile storage.

S5 Soft Off: Same as G2 state. No system context is stored.

Device Power States

▪ D-states:

State Description

D0 Fully powered-up, fully operational state.

D1 Initial sleep state for a device. Capable of waking itself or the entire system in response to an external event.

D2 Operate at a lower power, requiring a greater waking latency. More likely to lose its device context. Still capable of waking itself or the rest of the system.

D3hot Save a device-specific state so that it can be awakened without a complete reboot.

D3cold Complete power down of the device.

Processor Power States

▪ C-states: a sub-state of the S0 state

• Offer reduced power consumption while the system is fully on

State Description

C0 The processor executes instructions and operates normally.

C1 The sleep state where the transition latency is negligible.

C2 (optional)

Lower-power sleep state. The OS must consider the transition latency.

C3 (optional)

Great power reduction at the cost of an increased transition latency. Processor caches do not emit coherence traffic.

C4..Cn (optional)

Additional power states.

C-states Example

Processor Performance States

▪ P-states: a sub-state of the C0 state

• Offer reduced power consumption while the processor is executing code

• Useful for non-critical workloads, longer battery life, or waiting for user inputs

State Description

P0 The maximum performance, maximum power consumption state

P1 The next-highest-performing processor performance state and is expected to have the second-greatest power consumption.

P2..Pn Optional (up to a maximum of 16 distinct states)

C-states vs. P-states

Linux/Android Power Management

CPUfreq (1)

▪ The generic infrastructure to handle processors with P-state capability

CPUfreq (2)

▪ Governors decide how and when to change operating points

Governor Description

Performance Sets the CPU statically to the highest frequency

Powersave Sets the CPU statically to the lowest frequency

Userspace Allows any userspace program running with “root” to set the CPU to a specific frequency

Ondemand Changes the CPU frequency depending on CPU utilization

CPUfreq Example

▪ On Samsung Galaxy S II

$ cat /sys/power/cpufreq_table 1200000 1000000 800000 500000 200000 $ cat /sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state 1200000 787609 1000000 44696 800000 3122770 500000 652736 200000 26890016 $ cat /sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans 171342 $ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_driver exynos_cpufreq

CPUidle (1)

▪ A generic infrastructure that puts idle CPUs into low-power states (C-states)

CPUidle (2)

▪ Governors decide what state to go for:

Governor Description

ladder

Takes a step-wise approach to selecting an idle state. Mostly applicable to ACPI platform Not work very well with tickless kernels

menu Picks the deepest possible idle state straight away. Considers the expected sleep time, latency requirements, previous C-state residency, etc.

Tickless Idle

▪ Eliminates the periodic timer tick when the CPU is idle.

▪ This allows the CPU to remain in power saving states for a longer period of time, reducing the overall system power consumption

▪ Benefits of tickless idle will be lost if the CPU is frequently awakened by unnecessary timer events.

PowerTOP

▪ Show how well your system is using the various hardware power-saving features

▪ Show you the culprit software components that are preventing optimal usage of your hardware power savings

▪ Help Linux developers test their application and achieve optimal behavior

▪ Provide you with tuning suggestions to achieve low power consumption

PowerTop Example

Android Wake Locks

▪ Components make requests to keep the power on through “wake locks”

▪ Forces the device to remain on

▪ Can lead to greatly poor battery life if not properly used

Power Management - AndroBenchcsl.skku.edu/uploads/ICE3028S13/16-power.pdfDevice Power States...

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