Post on 12-Jan-2016
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transcript
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Serial Powering of Silicon Strip Detectors at SLHC
Marc Weber, Giulio Villani, M. Tyndel (RAL)with Anu Tuonnonnen and Robert Apsimon
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Powering schemesIndependent powering
PS PS PS PSPS
PS PSPS
PSPS
Could this scheme be better?
Power in Power out
PS
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How to power a SLHC tracker ?Many unknowns, but power will be a major challenge and affects cooling, material budget, packaging and more
Focus of this talk is on silicon strip sensors. There is earlier powering stuff for ATLAS pixels by Bonn university group
KnownSCT: up to 160 m long cables, cable resistance up to ~ 3.5 ΩSCT: power efficiency 50%, 25 kW module power; 50 kW total
Estimate (assuming lower voltages, similar current and cable resistance)
SLHC: power efficiency 20%, if 50 kW modules power 400 kW total
This is a power station not a tracker !
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Why independent powering fails at SLHC ?
1. Don’t get 5 or 10 times more cables in
2. Power efficiency is too low (50% SCT 20% SLHC)
3. Material budget: 0.2% or R.L. per layer (barrel normal incidence) 1% or 2% SLHC
4. Packaging constraints
Each reason by itself is
probably sufficient for a
No-No
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Serial powering and parallel power bus with DC-DC conversion
Note: Parallel powering without DC-DC conversion is problematic due to low power efficiency and large IR drops
Alternatives to IP
M1 M2 M3
M1 M2 M3
M1 M2 M3
IP
PP with DC-DC conversion
SP
Analog and digital voltage
Constant current for both analog and
digital power
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Four elements
Current source
Shunt regulator and power device (digital power)
Linear regulator (analog power)
AC or opto-coupling of signals
How does SP work?
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Regulators
8V
4V
4V
0V
Chain of modules at different voltages
Chips on a module are connected in parallel (as usual)
analog ground, digital ground and HV ground are tight together for each module (as usual) floating HV supplies
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AC LVDS coupling
All but one module are on different potential than DAQ
LVDS buffers are at the potential of the receiving unit (DAQ power for data; module power for
clock/control)
Opto-decoupling is an alternative
Simplified AC coupling diagram
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Power efficiency ratio (SP/IP) Vs # of modules
1
1.5
2
2.5
3
3.5
4
4.5
5
1 6 11 16 21 26
# of modules (n)
(1+
x)/(
1+x/
n)
x = 4.5 (SLHC)
x = 1.14 (LHC)
Reduce number of cables by factor 2x2n/2=2n (even more if counting sense wires)
Huge increase of power
efficiency over IP as Vdd goes
down: [1+x]/[1 + x/n]
x = cable IR/Vdd
material reduction
cost savings (cables and PS)
Same benefits for DC-DC conversion
Advantages of serial powering
M1 M2 M3 M1 M2 M3
~1+x
SLHC
Vdd=1V
“SCT”
Vdd=4V
Combining analog and digital cables
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“ Only a physicist can be crazy enough to try this!”
Noisy; oscillations; interference between modules
probably not main difficulty
Risky; can lose all modules due to single-point failure
Much less risky than one might think
Loss of control over individual modules
important constraint that can be addressed to some extent
Grounding and shielding of densely packaged extended system
is part of stave R&D
Perceived disadvantages of SP
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Serial powering of six ATLAS SCT modules
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Serial powering interface board with regulator and AC coupling
Commercial components; connectors
SCT modules are untouched; standard SCT PS is not used
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Schematic of Shunt regulator
Simple but effective design
Will be integrated in custom RDIC or dedicated ASIC in the future
(ATLAS pixel chip contains active circuitry already)
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SP interface board in more detail
Shunt regulator and power transistor; analog regulator 3 x AC LVDS coupling (clock/control/data)
LVDS buffer circuitries
Shunt regulator circuitry Linear regulator circuitry
D
A
Q
M
O
D
U
L
E
Large area prototype for small board (see Carl’s talk)
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We can make this much smaller 2+2 layer PCB; 38 x 9 mm2 (this is a PCB for cost reasons)
Further shrinkage if SP integrated into hybrid and if most circuits elements integrated into readout ICs
Estimated extra hybrid floor area due to SP: ~10%
Hybrid
SSPPCB
ABCD3TV2
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Hybrid noise with and without SP boardDistribution of ENC for IP and SP for hybrid 19
0
10
20
30
40
50
60
70
80
90
500 550 600 650 700 750 800
ENC
# o
f ch
ann
els
IP
SP
This is “serial powering” of one hybrid (4-chip LBNL hybrid)
Bare hybrid measurements are most sensitive
SP noise performance is excellent regulators work fine
LBNL IPRAL SP
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Noise performance of 6 SCT modules
<ENC> Vs module number for IP and SP with 6 modules
1420
1440
1460
1480
1500
1520
1540
1560
1580
1600
755 663 159 628 662 006
Module #
<E
NC
> IP
SP
Precise measurements; noise performance of SP is excellent
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A closer look at the same data
ENC against channel number for IP and SP for module 663
0
500
1000
1500
2000
2500
0 200 400 600 800 1000 1200 1400
Channel #
EN
C IP
SP
Gain against channel number for IP and SP for module 663
0
10
20
30
40
50
60
70
0 200 400 600 800 1000 1200 1400
Channel #
Gai
n IP
SP
Combining two data streams (link0 and link1) saves space don’t read out chip 7
SP and IP noise and gain are very similar
The same is true for the other 5 modules (not shown)
Channel Channel
ENC Gain
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Noise distribution of one of the 6 SCT modules
Distribution of ENC for IP and SP for module 662
0
20
40
60
80
100
120
140
1000 1100 1200 1300 1400 1500 1600 1700 1800
ENC
# o
f ch
ann
els
IP
SP
Noise performance of SP is excellent
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Noise injectionPrinciple: superimpose a current modulation of 15 mA to 1.6 A current;
scan through a frequency range from Hz to 40 MHz;
measure module noise
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Noise injection: SP with 6 SCT modulesENC against frequency of injected noise
1350
1400
1450
1500
1550
1600
1650
1 100 10000 1000000 100000000
Frequency (Hz)
EN
C
Module 662
Module 006
Module 159
Module 663
Module 755
Module 628
No significant increase in noise
Note that coupling of noise between modules through power line is not possible conservation of charge/current!
Frequency [Hz]
<ENC>
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Is serial powering to risky?
Risk of module loss due to single-point failures for IP and SP
Over current protection through shunt regulator design
Protection by operating SR in parallel
Risk = (# of power connections) x (probability of a failure) x (# of modules lost per failure)
I am sure there are other ways to define risk, but this is instructive
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Risk comparison: IP vs SPDistribution Board
Module 1
Module 2
Module n
Digital PS 1
Digital PS 2
Digital PS n
Analog PS 1
Analog PS 2
Analog PS n
Independent Powering
Wirebonds
CablesType 1
CablesType 2
Connections (analog + digital)
4n + 4n
4n + 4n
4n + 4n
Probability of a failure
aIP bIP cIP
Lost modules 1 1 1
Distribution Board
Module 1 Module 2
Power supply
Module n
SP: one broken connection loses n modules
however, much less cables less connections
Serial Powering
Wirebonds
CablesType 1
CablesType 2
connections (analog + digital)
2 (n+1)
4 4
Probability of a failure
aSP bSP cSP
Lost modules
n n n
IP
SP
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Risk comparison Risk ratio against number of modules in SP chain
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35
# of modules
Ris
k ra
tio
(S
P/I
P)
Case 1
Case 2
Case 3
Case 4
Risk due to breaking bonds/connections is larger for SP, but less than one might think
Risk increases ~ number of modules/4 Build in increased redundancy
Risk ratio (SP/IP)
IPIPIP
SPSPSP
cba
cbna
4
221
# of modules
Make your own choices for values of
a,b, and c
Mine are here …
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Architecture choices: single vs. multi- SR arrangement
Single SR and LR for 2 chips 2 parallel SR and LR for 2 chips
Remember, in SP you have to fight opens! (in PP, shorts)
Parallel SR and LR arrangement is safer (SR and LR are part of RDIC)
Failure of one power transistor does not kill all modules
Can also use register to set voltages on chip
RDIC RDICRDIC RDIC
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Overcurrent protectionPower transistor is weakest point of SR regulator
It has to stand full current in case of a module open risk of burn out
Protect against this by automatically reducing SR voltage in case of overcurrent condition
Simplified diagram for illustration of overcurrent protection
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AC LVDS couplingWe use two different schematics
Command/data signal: feed-back resistor between input and output of LVDS buffer (value should be high enough to allow for multi-drop configurations)
Clock: LVDS buffer input is pulled to buffer ground ( non-standard common mode level)
Clock
Command
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AC LVDS couplingTested AC LVDS coupling with dedicated test circuits for large range of duty cycles and frequencies ; this is work in progress
This works just fine in practice; conventional wisdom is that you should not do it this way
(no DC balanced protocol; no 0V common-mode)
We will find out why it works…
120 MHz
1 MHz
1 MHz 40 MHz
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Future R&D program on powering schemes
Goal: be ready for implementation of advanced SP and DC-DC conversion PP systems in a realistic module assembly in ~ 3 years
Can distinguish three phases:
Generic studies (as presented here and in Carl’s talk) to identify crucial features and challenges “easy”, affordable, “fun”
Develop radiation-hard custom electronics (ABC_Next chip); build and test systems with large number of modules significant effort, serious engineering
Implemention of power distribution schemes on advanced supermodule prototypes “service”, crucial to establish supermodule electrical performance
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What we have learnt so far Noise performance is excellent; expect SP systems to be less noisy than alternatives; IR drops don’t matter for one
Risk of failure is bigger than for IP but much smaller than naively expected; SP/IP risk ~ n/4; can use fraction of space gains to buy robustness; protect power transistor
Power efficiency is hugely improved (depending on x=IR/V); 20% (IP) -> 80% (SP) can save >100 kW of cable losses easily; power consumption of SP circuitry is small, dominated by excess current in power transistor
Need to emphasize voltage adjustment and feed-back from individual modules (slow control)
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Outlook
It unusual to gain such significant factors in a technology as mature as silicon detectors
SP is challenging but I believe we can make it work
If you are sceptical about these concepts, remember that we need to innovate. Without new powering schemes, we will
simply not get any SLHC tracking detectors
Last, but not least:
this not only of interest for SLHC. ILC tracker or non-silicon detectors might benefit as well
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Appendix
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Same board used with bare hybrid
HybridS P P C B
DAQ support card
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A closer look using a single hybrid<ENC> against frequency of injected noise for hybrid 24
614
615
616
617
618
619
620
621
1 10 100 1000 10000 100000 1000000 10000000 1E+08
Frequency (Hz)
<E
NC
>
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No more cables please
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First simulation results
Vout
Iin
Comp Vcout
Comparator Vin+
Comparator Vin-
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A look at material issues
naively extrapolating from an SCT to an SLHC layer assuming 5 times more channels, we get (one layer, barrel, normal impact):
Material budget will explode at SLHC without innovations in powering, packaging, and cooling
Component R.L. for SCT
Scaling factor*
R.L. for
SLHC
Cable 0.2 % x 5 1 %
Hybrid 0.3 % x 5 1.5 %
Sensor 0.6 % x 1 0.6 %
Cooling; CF cylinders; module baseboard; etc.
0.4; 0.3;
0.2 %
x 3; x 1; x 1
1.7 %
Total 2 % 5 %
Silicon fraction 30 % 12 %
too big !
*crude estimate; no innovation
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A look at material issues
services in ATLAS SLHC tracker would still run in gap between barrel and end cap detectors
in current SCT, particles cross (0.1 to 0.45%) x √2 of R.L. of cables in gap alone (dep. on polar angle)
a 5 or 10-fold increase of these numbers is prohibitive
DiscsBarrelInteraction point
Cables Generic ATLAS SLHC
Tracker Configuration
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Let’s look at 4 different powering set-ups for a stave with n modules
1. Each module is independently powered (IP scheme)
2. Power busses on stave serve modules in parallel (PP)
3. Parallel, but with DC-DC conversion (DCP) …
4. Modules are chained in series (SP)
Definitions: Module current and voltage: I, V Cable resistance (including return): R
power consumed by stave with n modules is always: n I V power wasted in the cable varies with powering scheme
Power efficiency
M1 M2 M3
M1 M2 M3
M1 M2 M3
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Power efficiency
Ignoring effects of regulators and other complications, get easy dependencies
Efficiency decreases with increasing R, I and decreasing V
Significant advantage for serial powering and DC-DC, even for small numbers of modules n and small gain g
Istave Vdrop Vstave Pcable PstaveEfficiency: Pstave/Ptotal
IP n I I R V n I2R n I V 1/[1 + IR/V]
PP n I n I R V n2 I2R n I V 1/[1 + nIR/V]
SP I I R nV I2R n I V 1/[1 + IR/nV]
DCP (n/g) I
(n/g) I R
gV (n/g)2
I2R
n I V 1/[1 + nIR/g2V]