PowerPoint Presentation - DAC Presentation kit · 2008. 10. 7. · Temporal Logic Model Checking...

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Model CheckingModel Checking

My 27 year quest to overcome the My 27 year quest to overcome the state explosion problemstate explosion problem

Edmund Clarke Edmund Clarke

Computer Science Department Computer Science Department

Carnegie Mellon UniversityCarnegie Mellon University

Intel Pentium FDIV BugIntel Pentium FDIV Bug

Try 4195835 – 4195835 / 3145727 * 3145727. Try 4195835 – 4195835 / 3145727 * 3145727. – In 94’ Pentium, it doesn’t return 0, but 256.In 94’ Pentium, it doesn’t return 0, but 256.

Intel uses the SRT algorithm for floating point division. Intel uses the SRT algorithm for floating point division. Five entries in the lookup table are missing. Five entries in the lookup table are missing.

Cost: $500 millionCost: $500 million Xudong Zhao’s Thesis on Word Level Model CheckingXudong Zhao’s Thesis on Word Level Model Checking

Recent Rumor: New AMD TLB Recent Rumor: New AMD TLB Bug??Bug??

AMD Family 10h revision B2 processors suffer from an issue in AMD Family 10h revision B2 processors suffer from an issue in the processor TLBthe processor TLB ( (Translation Translation LLookaside ookaside BBufferuffer).).

Launch date of these pLaunch date of these processorsrocessors was delayed in September, 2007. was delayed in September, 2007.

AMD doesn’t have official announcement yet, but you can google AMD doesn’t have official announcement yet, but you can google “AMD B“AMD Barcelona bugarcelona bug” for plenty of discussion.” for plenty of discussion.

Temporal Logic Model Temporal Logic Model CheckingChecking

Model checking is an Model checking is an automatic verification techniqueautomatic verification technique for finite state concurrent systems.for finite state concurrent systems.

Developed independently by Developed independently by Clarke and EmersonClarke and Emerson and and by by Queille and SifakisQueille and Sifakis in early 1980’s.in early 1980’s.

SpecificationsSpecifications are written in are written in propositional temporal propositional temporal logiclogic..

Verification procedure is an Verification procedure is an exhaustive search of the exhaustive search of the state spacestate space of the design. of the design.

Advantages of Model Advantages of Model CheckingChecking

No proofs!!!No proofs!!!

Fast (compared to other rigorous methods such as Fast (compared to other rigorous methods such as theorem proving)theorem proving)

Diagnostic counterexamplesDiagnostic counterexamples

No problem with partial specificationsNo problem with partial specifications

Logics can easily express many concurrency propertiesLogics can easily express many concurrency properties

Main DisadvantageMain Disadvantage

State Explosion ProblemState Explosion Problem::

2-bit counter

0,0 0,1 1,11,0

n-bit counter has 2n states

Main Disadvantage Contd.Main Disadvantage Contd.

|| n states,m threads

2,a 1,b

2,b3,a 1,c

3,b 2,c3,c

nm states

Main Disadvantage Contd.Main Disadvantage Contd.

State Explosion ProblemState Explosion Problem::

Unavoidable in worst case, but steady progress over the past 27years using clever algorithms, data structures, and engineering

Determines Patterns on Infinite Traces Determines Patterns on Infinite Traces

Atomic PropositionsAtomic Propositions

Boolean OperationsBoolean Operations

Temporal operatorsTemporal operators

aa “a is true now”“a is true now”X aX a “a is true in the ne“a is true in the neXXt state”t state”FaFa “a will be true in the “a will be true in the FFuture”uture”GaGa “a will be “a will be GGlobally true in the future”lobally true in the future”a U ba U b “a will hold true “a will hold true UUntil b becomes true”ntil b becomes true”

LTL - Linear Time LogicLTL - Linear Time Logic

aa “a is true now”“a is true now”X aX a “a is true in the neXt state”“a is true in the neXt state”FaFa “a will be true in the “a will be true in the FFuture”uture”GaGa “a will be “a will be GGlobally true in the future”lobally true in the future”a U ba U b “a will hold true “a will hold true UUntil b becomes true”ntil b becomes true”

aa “a is true now”“a is true now”X aX a “a is true in the ne“a is true in the neXXt state”t state”FaFa “a will be true in the Future”“a will be true in the Future”GaGa “a will be “a will be GGlobally true in the future”lobally true in the future”a U ba U b “a will hold true “a will hold true UUntil b becomes true”ntil b becomes true”

aa “a is true now“a is true now””X aX a “a is true in the ne“a is true in the neXXt state”t state”FaFa “a will be true in the “a will be true in the FFuture”uture”GaGa “a will be Globally true in the future”“a will be Globally true in the future”a U ba U b “a will hold true “a will hold true UUntil b becomes true”ntil b becomes true”

a a a a a

aa “a is true now”“a is true now”X aX a “a is true in the ne“a is true in the neXXt state”t state”FaFa “a will be true in the “a will be true in the FFuture”uture”GaGa “a will be “a will be GGlobally true in the future”lobally true in the future”a U ba U b “a will hold true Until b becomes true”“a will hold true Until b becomes true”

a a a a b

Branching TimeBranching Time

CTL: Computation Tree LogicCTL: Computation Tree Logic

EF g “g will possibly become true”

AF g “g will necessarily become true”

AG g “g is an invariant”

EG g “g is a potential invariant”

CTL uses the temporal operatorsCTL uses the temporal operators

AX, AG, AF, AUAX, AG, AF, AU

EX, EG, EF, EUEX, EG, EF, EU

CTL*CTL* allows complex nestings such as allows complex nestings such as

AXX, AGX, EXF, ...AXX, AGX, EXF, ...

CTL: linear model checking algorithm !CTL: linear model checking algorithm !

Model Checking ProblemModel Checking Problem

Let Let MM be a be a state-transition graphstate-transition graph..

Let Let ƒƒ be the be the specificationspecification in temporal logic. in temporal logic.

Find all states Find all states ss of of MM such that such that M, s |= ƒM, s |= ƒ..

• CTL Model Checking: CE 81; CES 83/86; QS 81/82.CTL Model Checking: CE 81; CES 83/86; QS 81/82.• LTL Model Checking: LP 85.LTL Model Checking: LP 85.• Automata Theoretic LTL Model Checking: VW 86.Automata Theoretic LTL Model Checking: VW 86.• CTL* Model Checking: EL 85.CTL* Model Checking: EL 85.

State-transition graphdescribes system evolvingover time.

Model of computationModel of computation

~ Start~ Close~ Heat~ Error

Start~ Close~ HeatError

~ StartClose~ Heat~ Error

~ StartCloseHeat~ Error

StartCloseHeat~ Error

StartClose~ Heat~ Error

StartClose~ HeatError

Microwave Oven Example

Temporal Logic and Model Temporal Logic and Model CheckingChecking

• The oven doesn’t The oven doesn’t heat upheat up until the until the door is closeddoor is closed..

• NotNot heat_upheat_up holds holds untiluntil door_closeddoor_closed

• ((~~ heat_upheat_up)) UU door_closeddoor_closed

Transition System(Automaton, Kripke structure)

Hardware Description(VERILOG, VHDL, SMV)

Informal Specification

Temporal Logic Formula(CTL, LTL, etc.)

compilation

manualalgorithmic

verification

Model CheckingModel Checking

Hardware Example: IEEE Hardware Example: IEEE FuturebusFuturebus++

In 1992 we used Model Checking to verify the In 1992 we used Model Checking to verify the IEEE IEEE Future+ cache coherence protocolFuture+ cache coherence protocol..

Found a number of Found a number of previously undetected errorspreviously undetected errors in the in the design.design.

First time that formal methods were used to find First time that formal methods were used to find errors in an errors in an IEEE standardIEEE standard..

Development of the protocol began in Development of the protocol began in 19881988, but , but previous attempts to validate it were informal.previous attempts to validate it were informal.

Symbolic Model CheckingSymbolic Model Checking

Burch, Clarke, McMillan, Dill, and Hwang 90;Burch, Clarke, McMillan, Dill, and Hwang 90;

Ken McMillan’s thesis 92Ken McMillan’s thesis 92

The Partial Order ReductionThe Partial Order Reduction

Valmari 90Valmari 90

Godefroid 90 Godefroid 90

Peled 94Peled 94

Four Big Breakthroughs on Four Big Breakthroughs on State Space Explosion State Space Explosion Problem! Problem!

Four Big Breakthroughs on State Four Big Breakthroughs on State Space Explosion Problem (Cont.)Space Explosion Problem (Cont.)

BoundedBounded Model CheckingModel Checking– Biere, Cimatti, Clarke, Zhu 99Biere, Cimatti, Clarke, Zhu 99– Using Fast SAT solversUsing Fast SAT solvers– Can handle thousands Can handle thousands of state elementsof state elements

Can the given property fail in k-steps?

I(V0) Æ T(V0,V1) Æ … Æ T(Vk-1,Vk) Æ (: P(V0) Ç…Ç: P(Vk))

k-stepsProperty fails in some stepInitial state

BMC in practice: Circuit with 9510 latches, 9499 inputsBMC formula has 4 £ 106 variables, 1.2 £ 107 clausesShortest bug of length 37 found in 69 seconds

Four Big Breakthroughs on Four Big Breakthroughs on State Space Explosion Problem State Space Explosion Problem (Cont.)(Cont.) Localization ReductionLocalization Reduction

– Bob Kurshan 1994Bob Kurshan 1994

Counterexample Guided Abstraction Refinement (CEGAR)Counterexample Guided Abstraction Refinement (CEGAR)– Clarke, Grumberg, Jha, Lu, Veith 2000Clarke, Grumberg, Jha, Lu, Veith 2000

– Used in most software model checkersUsed in most software model checkers

From Hardware to Software:From Hardware to Software:

Natural Question: Is it possible to model check Natural Question: Is it possible to model check software?software?

According to According to Wired NewsWired News on Nov 10, 2005: on Nov 10, 2005:

“ “When Bill Gates announced that the technology When Bill Gates announced that the technology was under development at the 2002 Windows was under development at the 2002 Windows Engineering Conference, he called it the holy Engineering Conference, he called it the holy grail of computer sciencegrail of computer science””

Grand Challenge:Grand Challenge:Model Check Software !Model Check Software !

What makes Software Model CheckingSoftware Model Checking different ?

What Makes Software Model What Makes Software Model Checking Different ?Checking Different ?

Large/unbounded base types: Large/unbounded base types: int, float, stringint, float, string User-defined types/classesUser-defined types/classes Pointers/aliasing + unbounded #’s of heap-allocated cellsPointers/aliasing + unbounded #’s of heap-allocated cells Procedure calls/recursion/calls through pointers/dynamic method Procedure calls/recursion/calls through pointers/dynamic method

lookup/overloadinglookup/overloading Concurrency + unbounded #’s of threadsConcurrency + unbounded #’s of threads

What Makes Software Model What Makes Software Model Checking Different ?Checking Different ?

Templates/generics/include filesTemplates/generics/include files Interrupts/exceptions/callbacksInterrupts/exceptions/callbacks Use of secondary storage: files, databasesUse of secondary storage: files, databases Absent source code for: libraries, system calls, mobile codeAbsent source code for: libraries, system calls, mobile code Esoteric features: continuations, self-modifying codeEsoteric features: continuations, self-modifying code Size (e.g., MS Word = 1.4 MLOC)Size (e.g., MS Word = 1.4 MLOC)

What Does It Mean to Model Check What Does It Mean to Model Check Software?Software?

1.1. Combine static analysis and model checkingCombine static analysis and model checking UseUse static analysisstatic analysis to extract ato extract a model Kmodel K from a boolean from a boolean

abstraction of the program. abstraction of the program.

Then check that f is true in K (K Then check that f is true in K (K ²² f), where f is the f), where f is the specification of the program.specification of the program.

• SLAM (Microsoft)SLAM (Microsoft)• Bandera (Kansas State) Bandera (Kansas State) • MAGIC, SATABS (CMU) MAGIC, SATABS (CMU) • BLAST (Berkeley)BLAST (Berkeley)• F-Soft (NEC)F-Soft (NEC)

1.1. Simulate program along all paths in Simulate program along all paths in computation treecomputation tree

²² Java PathFinder (NASA Ames) Java PathFinder (NASA Ames)²² Source code + backtracking (e.g., Verisoft) Source code + backtracking (e.g., Verisoft) ²² Source code + symbolic execution + backtracking Source code + symbolic execution + backtracking

(e.g., MS/Intrinsa Prefix)(e.g., MS/Intrinsa Prefix)

• Use finite-state machine to look for patterns Use finite-state machine to look for patterns

in control-flow graph in control-flow graph [Engler][Engler]

1.1. Design with Finite-State Software Models Design with Finite-State Software Models Finite state software models can act as “missing link” Finite state software models can act as “missing link” between transition graphs and complex software.between transition graphs and complex software.

²² StatechartsStatecharts

²² EsterelEsterel

• Use Bounded Model Checking and SAT Use Bounded Model Checking and SAT [Kroening][Kroening]

²² Problem: How to compute set of reachable states? Problem: How to compute set of reachable states? Fixpoint computation is too expensive.Fixpoint computation is too expensive.

²² Restrict search to states that are reachable from initial Restrict search to states that are reachable from initial state within state within fixed numberfixed number n of transitions n of transitions

²² Implemented by Implemented by unwindingunwinding program and using program and using SAT solver SAT solver

Key techniques for Software Model Key techniques for Software Model CheckingChecking

Counterexample Guided Abstraction RefinementCounterexample Guided Abstraction Refinement

- Kurshan, Yuan Lu, Clarke et al JACM, Ball et al- Kurshan, Yuan Lu, Clarke et al JACM, Ball et al

- Uses - Uses counterexamplescounterexamples to refine abstraction to refine abstraction

Predicate AbstractionPredicate Abstraction

- Graf and Saidi, Ball et al, Chaki et al, Kroening- Graf and Saidi, Ball et al, Chaki et al, Kroening

- Keeps track of- Keeps track of certain predicates on datacertain predicates on data

-- Captures relationship between variablesCaptures relationship between variables

Transition System

Informal Specification

Safety Property:bad state unreachable:

satisfied

Initial State

CounterexamplesCounterexamples

Program

Transition System

ProgramInformal Specification

Initial State

Safety Property:bad state unreachable

Counterexample

Transition System

ProgramInformal Specification

Initial State

Safety Property:bad state unreachable

Counterexample

Existential AbstractionExistential Abstraction

Given an abstraction function α : S → Sα, the concrete states are grouped and mapped into abstract states :

α α α Preservation Theorem ?

Preservation TheoremPreservation Theorem

• Theorem (Clarke, Grumberg, Long)Theorem (Clarke, Grumberg, Long) If property holds on If property holds on abstract modelabstract model, it holds on , it holds on concrete modelconcrete model

• Technical conditionsTechnical conditions Property is universal i.e., no existential quantifiersProperty is universal i.e., no existential quantifiers Atomic formulas respect abstraction mapping Atomic formulas respect abstraction mapping

• Converse implication is not valid !Converse implication is not valid !

Spurious BehaviorSpurious Behavior

AGAF red“Every path necessarily leadsback to red.”

Spurious Counterexample:<go><go><go><go> ...

“red”

“go”

Artifact of the abstraction !

How to define Abstraction How to define Abstraction Functions?Functions?

Abstraction too fineAbstraction too fine➨➨ State ExplosionState Explosion

Abstraction too coarseAbstraction too coarse➨➨ Information LossInformation Loss

AutomaticAutomatic Abstraction MethodologyAbstraction Methodology

Automatic AbstractionAutomatic Abstraction

MOriginal Model

Refinement

Mα Initial AbstractionSpurious

Spuriouscounterexample

Validation orCounterexample Correct !

CEGAR CEGAR CCounterounterEExample-xample-GGuided uided AAbstraction bstraction RRefinementefinement

CProgram

InitialInitialAbstractionAbstraction

Simulator

No errorNo erroror bug foundor bug found

PropertyPropertyholdsholds

SimulationSimulationsucessfulsucessful

Bug foundBug found

Abstraction refinementAbstraction refinement Refinement

ModelChecker

VerificationVerification

Spurious counterexampleSpurious counterexample

CounterexampleCounterexample

Abstract Model

Software Example: Device Driver Software Example: Device Driver CodeCode

Also according to Also according to Wired NewsWired News::

“ “Microsoft has developed a tool called Static Device Microsoft has developed a tool called Static Device Verifier or SDV, that uses ‘Verifier or SDV, that uses ‘Model CheckingModel Checking’ to ’ to analyze the source code for Windows drivers and analyze the source code for Windows drivers and see if the code that the programmer wrote matches a see if the code that the programmer wrote matches a mathematical model of what a Windows device driver mathematical model of what a Windows device driver should do. If the driver doesn’t match the model, the should do. If the driver doesn’t match the model, the SDV warns that the driver might contain a bug.”SDV warns that the driver might contain a bug.”

Back to Hardware!Back to Hardware!

Ease of design

increases

Gate level (netlists)

Register Level

…………

System

Behavioral

Formal verification support

Register Level Verilog:

module counter_cell(clk, carry_in, carry_out);input clk;input carry_in;output carry_out;reg value;assign carry_out = value & carry_in;initial value = 0;

always @(posedge clk) begin// value = (value + carry_in) % 2; case(value) 0: value = carry_in; 1: if (carry_in ==0) value = 1; else value = 0; endcaseendendmodule

Gate Level (netlist):

.model counter_cell

.inputs carry_in

.outputs carry_out

.names value carry_in _n2

.def 01 1 1.names _n2 carry_out$raw_n1- =_n2.names value$raw_n30.names _n60.names value _n6 _n7.def 00 1 11 0 1.r value$raw_n3 value0 01 1….. (120 lines)

Lack of verification supportLack of verification support

Register Level

…………

System

Behavioral

use techniquesfrom software verification

Must be automaticand scalable!!

Model Checking at the Register Model Checking at the Register LevelLevel

Register Level

…………

System

Behavioral

Model check

Abstraction-Refinement loop Abstraction-Refinement loop (CEGAR)(CEGAR)

CProgram

InitialInitialAbstractionAbstraction

Simulator

No errorNo erroror bug foundor bug found

PropertyPropertyholdsholds

SimulationSimulationsucessfulsucessful

Bug foundBug found

Abstraction refinementAbstraction refinement Refinement

ModelChecker

VerificationVerification

Spurious counterexampleSpurious counterexample

CounterexampleCounterexample

Abstract Model

BenchmarksBenchmarks

Ethernet MAC from opencores.orgEthernet MAC from opencores.org 5000 lines of RTL Verilog5000 lines of RTL Verilog

Checked three properties:

3. Transmit module simulates state machine on left. (ETH0)

4. Checks transitions out of state BackOff (ETH1)

5. Checks transitions out of state Jam (ETH2)

IPG Preamble

Data0BackOff Jam

FCS PAD

Transmit Module In Ethernet MAC(self-loop on each state not shown)

Experimental ResultsExperimental Results

11194161359ETH2

5193127359ETH1

552144359ETH0

#Iters#PredsTime (sec)

LatchesBenchmark

Challenges for the FutureChallenges for the Future

Exploiting the Power of Exploiting the Power of SATSAT, Satisfiability Modulo Theories (, Satisfiability Modulo Theories (SMTSMT))

Compositional Model Checking Compositional Model Checking of both Hardware and Softwareof both Hardware and Software

Software Model CheckingSoftware Model Checking, Model Checking and , Model Checking and Static AnalysisStatic Analysis

Verification of Embedded SystemsVerification of Embedded Systems (Timed and Hybrid Automata) (Timed and Hybrid Automata)

Model Checking and Theorem ProvingModel Checking and Theorem Proving (PVS, STEP, SyMP, Maude) (PVS, STEP, SyMP, Maude)

ProbabilisticProbabilistic and and Statistical Statistical Model CheckingModel Checking

InterpretingInterpreting Counterexamples Counterexamples

Scaling upScaling up even more!! even more!!

My goal:My goal:Verification of Safety-Critical Embedded Verification of Safety-Critical Embedded

SystemsSystems

Do you trust your car?Do you trust your car?

Embedded Systems are as important in Europe as Computer Security is in the U.S.!

Students, Post-docs, and Students, Post-docs, and VisitorsVisitorsPh.D. Students:Ph.D. Students:

Sergey BerezinSergey Berezin Michael BrowneMichael Browne Jerry BurchJerry Burch Sergio CamposSergio Campos Sagar ChakiSagar Chaki Pankaj ChauhanPankaj Chauhan David DillDavid Dill Allen EmersonAllen Emerson Alex GroceAlex Groce Anubhav GuptaAnubhav Gupta Vicki Hartonas-GarmhausenVicki Hartonas-Garmhausen Himanshu JainHimanshu Jain Sumit JhaSumit Jha William KlieberWilliam Klieber David LongDavid Long Yuan LuYuan Lu Dong WangDong Wang Will MarreroWill Marrero Ken McMillanKen McMillan Marius MineaMarius Minea Bud MishraBud Mishra Christos NikolaouChristos Nikolaou Nishant SinhaNishant Sinha Prasad SistlaPrasad Sistla Muralidhar TalupurMuralidhar Talupur Xudong ZhaoXudong Zhao

Post-docs: Constantinos Bartzis Armin Biere Lei Bu David Deharbe Alexandre Donze Azadeh Farzan Ansgar Fehnker Wolfgang Heinle Tamir Heyman James Kapinski Daniel Kroening Axel Legay Daniel Milam Alaexandar Nanevski Joel Ouaknine Karsten Schmidt Subash Shankar Ofer Strichman Prasanna Thati Micheal Theobald Tayssir Touili Helmut Veith Silke Wagner Karen Yorav Haifeng Zhu Yunshan Zhu

Visitors: Y. Chen Y. Feng T. Filkorn M. Fujita P. Granger O. Grumberg H. Hamaguchi H. Hiraishi S. Kimura S. Krischner G.H. Kwon X. Li A. Platzer R. Raimi H. Schlingloff S. Shanker Y.Q. Sun T. Tang F. Tiplea Y. Tsay J.P. Vidal B. Wang F. Wang P. Williams W. Windsteiger Kwang Yi T. Yoneda

Questions?Questions?

PowerPoint Presentation - DAC Presentation kit · 2008. 10. 7. · Temporal Logic Model Checking...

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