1

2

Present computers Future computers

Digital, binary

Solid state based (semiconductors)

Localized/distributed

Stored energy dependent

Quantum/classical

3

Present computers Future computers

Digital, binary

Solid state based (semiconductors)

Localized/distributed

Stored energy dependent

Quantum/classical

4

Present computers Future computers

Digital, binary

Solid state based (semiconductors)

Localized/distributed

Stored energy dependent

Digital

•  Binary 0,1 •  Decimal 0,1,2,3,4,5,6,7,8,9 •  Exadecimal 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F •  …non positional systems

5

The binary system has two main advantages..

Digital

•  Binary 0,1 •  Decimal 0,1,2,3,4,5,6,7,8,9 •  Exadecimal 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F •  …non positional systems

6

1)  Boolean logic transistors implementation 2)  Noise tolerant

Noise tolerance

•  Binary systems: two states, two thresholds •  Relevant parameters: σ, b 7

Noise intensity σ Threshold value

Switch failure !!!

8

New trends in computer architectures

–  Tendency to scale CMOS based devices toward the nm region. –  Low energy dissipation scenario ---> low voltages

After Aygun, K.; Hill, M. J.; Eilert, K.; Radhakrishnan, K.; Levin, A. Power Delivery for High-Performance Microprocessors. Intel Technology Journal. (November 2005).

The role of noise in computation devices has become increasingly relevant. As a consequence: the noise immunity has become the objective of significant research efforts

9

Noise can affect the functioning of computing devices in a number of different ways.

We focus here on the functioning of the very basic computing elements: the LOGIC GATES

NOT OR AND

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Such devices, characterized by well defined input-output relationships can be asembled into combinatorial and/or sequential networks in order to perform the computational tasks.

1)  Static signals in complex networks 2)  Functioning of logic gates

Noise can affect the system performance by affecting:

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The state switching dynamics is crucial to all logic gates.

To fix our ideas let’s focus on the NOT gate:

If Vin > 0.5V (Input state = 1) then Vout = 0 V (Output state = 0) If Vin < 0.5V (Input state = 0) then Vout = 5 V (Output state = 1)

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Switch event model on the NOT gate, without noise

Input signal switch time Propagation delay time tp-to

Logic state

Logic state

input

output

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Switch event model on the NOT gate, with noise

14

Input signal switch time Propagation delay time tp-to

Logic state

Logic state

The delayed switching error is produced when the NOT gate, expected to be in the LOW state is found instead still in the HIGH state due to a delayed switch.

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bit-flip condition

Logic state

Logic state

The bit-flip error is produced when, after a switch event (HIGH to LOW) is occurred at a certain time t0 a new unwanted switch can occur in the opposite direction (LOW to HIGH).

16

17

a)  At t = t0 there is no switch b) No switch occurs for a while

The error probability decreases with time. If we fix an acceptable error ε, then it exist a time tw such that:

thus

1

18

19

A bit-flip error occurs when after a switch at time t=t0 , due to the presence of noise the input signal (still iu) reaches the lower switching threshold bd.

This happens when:

Unfortunately, if we wait too long a new error mechanism comes into play

After that

The re-crossing time t is a random variable whose MFPT T2

20

Thus the probability that a crossings of bd occurs is the error probability P2 and is given by

The error probability increases with time. If we fix an acceptable error ε, then it exist a time th such that:

thus

P2 < ε when t < th

2

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3

Pe = P1 + P2

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Conclusions

1

t > tw (ε,σ,τ)

2

t < th (ε,σ,τ)

3

tw (ε,σ,τ) < t < th (ε,σ,τ)

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Biblio:

- Noise limited computational speed, L. Gammaitoni , Applied Physics Letters, 11/2007, Volume 91, p.3, (2007)

Papers on: http://nipslab.fisica.unipg.it/biblio