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transcript
Process Controlbased on Product Performance
SEMI Technology Symposium 2009
Copyright © Keirex Technology Inc., 2008-2009
SEMI Technology Symposium 2009December 3, 2009Makuhari, Japan
Nobuo FudanukiKeirex Technology Inc.
www.keirex.com
Abstract
Modeling to link process parameters withproduct power and timing characteristics isdiscussed. Such a model would allow you toobtain optimal process parameters tomaximize production yield while satisfyingproduct performance requirements, and APC
Copyright © Keirex Technology Inc., 2008-2009
product performance requirements, and APCusing such a model would enable you tocontrol the process based on the final productperformance.
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What's APC in Semiconductor Process?
APC (Advanced Process Control) is a system toimprove process performance (CD, OL, etc.) byfeedback or feedforward operations. (by SEAJ)
Recent semiconductor manufacturing equipmentmay provide with data sampling apparatus forthis purpose.
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Feedforward operations in the current APC aim toadjust the shift of device parameters (Vt, Idr) fromthe process target based on the measurement.
This system reduces process variation.
Product performance is guaranteed by the designconsidering the process control or specification limit.
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APC and Performance Guarantee
Target mean of Final distribution of Vt is
Accumulation
Vt Vt
Estimated mean after
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Feedforward operations inthe current APC aim toadjust the shift of deviceparameters (Vt, Idr) fromthe process target basedon the measurement.
Product performance isguaranteed by the designconsidering the processcontrol limit such as worstcase of Vt at ±3~6σ of itsdistribution.
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Target mean ofprocess control
Final distribution of Vt iscontrolled around the target
Estimated mean afterCD measurement
What Matters?
What's happening is: Production team pays extra cost to apply APC for
achieving the pre-defined specification limit. Design team pays extra cost to design a product
for guaranteeing the product is functional all overthe range within the pre-defined specification limit.
It is getting extremely difficult to design aproduct functional all over the range within the
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product functional all over the range within thepre-defined specification limit, and
Both production and design are locally optimizedindividually.
It's worth revisit the meaning of the specificationlimit, or product performance guarantee system?
Ever Increasing Process Variation Local random variation and the sources
20
30
40 gate length (L)
wire (w, h, )
/mean
(%)
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20
30
40 gate length (L)
wire (w, h, )
/mean
(%)
50
20
30
40 gate length (L)
wire (w, h, )
/mean
(%)
50
Getting simply worse
Local Stress LER(Line Edge Roughness)
Layout dependent
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These are physical and difficult to control Impact in lower productivity, lower yield and higher
power consumption
Technology node (nm)
0
10
20
250 180 130 90 65
3/m
ean
Vth
Tox
[出典:ITRS、2005年]
Technology node (nm)
0
10
20
250 180 130 90 65
3/m
ean
Vth
Tox
Technology node (nm)
0
10
20
250 180 130 90 65
3/m
ean
Vth
Tox
[出典:ITRS、2005年]
90% cause of local random var.
[Drawn based on the Nikkei Microdevices, Jul 2007 issue]
Discrete DopantNon-uniformity ofpotential due tosurface roughness
Advanced device
[Refered from ITRS 2005]
Local and Global Variation
Total variation
TraditionalSlow
Corner
TraditionalFast
Corner
Global variation
Controllable byDFM
Total variationincluding
both local and global
Variation measured=
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Issue is ever increasing local variation.
Local variationat global mean+3σ,at global mean andat global mean-3σ
[STARC Forum 2006, STARC homepage, Jul 2006]
Local narrowdistribution
around global shiftof mean
Systematic shift
Random OCV
+
Worst-Case and Statistical Design Viewpoint Statistical Design eliminates pessimism.
Traditional method(Deterministic)
Assuming all thedevices performsat the worst case.
Statistical methosAssuming some of
Distribution of slacks
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Statistical design appears to improve the performance. Contributes to reduce design turn around by quicker
timing closure. Performance is not improved really, however!
Assuming some ofthe devices
performs poorlyin accordance withthe distribution.Slower Faster
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Different Motivations
Design team insists in using SSTA (StatisticalStatic Timing Analysis) for eliminating pessimism.
Relaxation of worst case corner conditions mayprovide quick and easy timing closure
Production team is concerned about yield.
Statistical design methodology makes designclosure easier but performance is not improved.
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closure easier but performance is not improved.
Yield loss by eliminating pessimism may not beacceptable.
The issue here is the balance between the riskand the added value of using the statistical model.
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So, What's Good about Statistical Design?
Only few companies officially accept "sign-off"using SSTA (Statistical Static Timing Analysis).
Still problems in compatibility with existing"Golden" flow, and performance of statisticaldesign tools.
Silicon works anyway, even with hard effort toclose the design, relaxing the worst case
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close the design, relaxing the worst caseconditions in many ways.
Value of statistical design is not yet known.
Finally statistical design is not yet trusted.
One of the issues is the accuracy of the model sothat the production team accepts and trust it.
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Full Chip Statistical Performance Model Chip level variation model proposed by Anova
Solutions, Inc. accurately models chip level timingand leakage. Using response surface over variation of device parameters,
supply voltage, operating temperature, substrate bias, etc.
High-speed and scalable
Supports statistical design analysis
Core technology is how to create such a model easily.
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Core technology is how to create such a model easily.
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Model
Lg
Vtp
Vtn
TOX…
VDD
VSUB
Temperature
Chip level timing
Chip level leakage
Stochastic Analysis Process – SAP
Transform distribution ofinput parameters toGaussian
Fit to a response surfaceusing orthogonalpolynomials withtransformed parametersTarget
Fitting
Results
Reversetransform
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transformed parameters Reduce sampling points
Weighting to enhanceaccuracy
High-speed and scalableMonte Carlo simulation
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Targetsystem
Sampling points
Parametertransform
Unified Variation Models Covers fromDevice Level to Full Chip Level
Unifie
dVaria
tion
Models
Chip Design
Timing & LeakageLibrary
Character-ization
SSTA& CA
Higher level abstractionas performance closelycoupled with lower levelprocess and devicecharacteristics
Accurately evaluate chiplevel performance
Copyright © Keirex Technology Inc., 2008-2009
Unifie
dVaria
tion
Models Process Device
TEGData
Analysis
Anova's unique modelingSAP (Stochastic Analysis Process)
Fitting to process anddevice characteristics
Considering globalprocess variation andoperating conditions liketemperature, Vdd, etc.
characteristics
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Cell Model Evaluation Result
Monte Carlosampling of modelvs. SPICEsimulation at 300Kpoints over uniformdistribution of:
Lg, Vth
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Lg, Vth
VDD, VSUB, Temp 7 x 7 slew/load
values Relative error:
mean = -0.2%, 3 sigma = 3.4%
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Delay vs (Vdd, Temp)
• Condition:– inverter– Arc: Fr– Slew = 275ps– Load = 4fF
– Vdd in range:[0.8, 1.4]
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[0.8, 1.4]– temperature in range:
[-40, 125]
• Accuracy:– Max absolute error
1.7ps– Max relative error 1.6%
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Leakage vs (dLg, dVtp)
• Condition:– inverter– Arc: Rf– Vdd = 0.9– Temp = 125
– dLg range:[-3.6nm, 3.6nm]
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[-3.6nm, 3.6nm]– dVtp range:
[-0.06, 0.06]
• Accuracy:– Max absolute error
1.6ps– Max relative error 5.7%
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Chip Level Timing Model Evaluation Result
Prediction of theworst case timingusing nominalcondition model. x-axis
Simulation usingthe foundry cornerSPICE parameters.
y-axis
65nmprocess
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y-axis Prediction using
Anova modelbased on thefoundry nominalSPICE parameters.
Accuracy Max relative error
is less than 5%.
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45nmprocess
Monte Carlo Simulation of Chip Level Timing
SetupTimeSlack
FF
SF
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Indicates timing distribution and yield in production.
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Hold Time Slack
SS
FS
Timing and Leakage Correlation
FFCorner
Copyright © Keirex Technology Inc., 2008-200919
SSCorner
What-If Analysis Simulate the distribution of timing performance and
power consumption when changing the process oroperation conditions. Process conditions (Vth、Lg)
Vth: -3 ~ 3σ Lg: 0 ~ 6σ (≈10nm)
Supply voltage Vdd: 0.9v ~ 1.2v
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Vdd: 0.9v ~ 1.2v Substrate bias
Vsbn: Vss+0.85v ~ Vss+1.55v Vsbp: Vss-0.55v ~ Vss+0.2v
Combination of the above
Example: Explore the conditions to minimize leakagecurrent. Predict distribution of timing performance and power
consumption in production.
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What-If Analysis Example:Simulate Power Consumption
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65nm, 1.6M cells, Temp=125C, Nominal Vdd=1.05V
Application to Process Control Exploration of optimal process conditions for a
design Performance optimization Parametric yield optimization
Yield and performance estimation at producttransfer to the other fab Smooth transfer from prototyping to production
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Smooth transfer from prototyping to production Multiple fabs
Yield enhancement linking with APC Individual process control considering the design
characteristics Determine feedback and/or feedforward
adjustment considering the designcharacteristics
APC based on Device Performance
Lithograph EtchingIon
Implant
CDMeasure
CDMeasure
ρsMeasure
Nextstep
Previousstep
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Feedforward and Fedback
Timing Distr Timing Distr Timing Distr
ProcessControl
ProcessControl
ProcessControl
Performance Guaranteethrough Process Control
Adjust the meanof then deviceperformance tothe design target
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Target mean of deviceperformance at design
Predicted mean ofdevice performance
Delay
Utilization of Mask Inspection Data
Dimension
Offset
Mask inspection data can bedirectly fed forward to adjustCD by control of waferposition, scanning speed, etc.
Current flow
MaskDrawing
MaskInspection
Lithograph
Etching,Ion Impl,Anneal,
etc.
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Defect
Mask inspection data maybe fed back to adjust thedimension or offset whenmaking replica or double-patterning mask.
Chip leveltiming model
Device characteristics is predictable takingdimension error and offset error assystematic variation source, and can beused to determine the feedforward controlof scanning speed, impurity density, etc.
ChipDesign
Proposed flow
MaskRepair
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PC based on both Equipment Libraryand Device Performance
ProductMaskConditions
・・・
Measured CDand offset
(attached with mask)
AdjustedScanner
#1Scanner
#2Scanner
#n
TestMask
Chip
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Scannercharacteristics
library
CD variation(µ, σ)
CD variation(µ, σ)
CD variation(µ, σ)
Adjustedexposureconditions
#1 #2 #n
Scanner#x
Chipdesign
Conclusions
Next generation APC needs to focus both onproduction and design concurrently.
Accurate design model to link the productperformance with variation of the process ordevice parameters would enable you to build anovel PC mechanism.
Copyright © Keirex Technology Inc., 2008-2009
novel PC mechanism.
Such a powerful modeling technique isavailable.
Library of equipment characteristics would allowyou to line-by-line or equipment-by-equipmentcontrol under the model based PC system.
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Thank you for your attention.
Copyright © Keirex Technology, Inc., 2008-2009
Keirex Technology Inc.
www.keirex.com