Quaternary Galois field adder based all-optical multivalued logic circuits

transcript

Quaternary Galois field adder based all-opticalmultivalued logic circuits

Tanay Chattopadhyay,1,2 Chinmoy Taraphdar,3 and Jitendra Nath Roy1,*1Department of Physics, College of Engineering and Management, Kolaghat,

P.O. KTPP Township, Purba Midnapur, 721171 West Bengal, India3Department of Physics, Bankura Christian College, Bankura, 722101 West Bengal, India

2tanay2222@rediffmail.com

*Corresponding author: jnroys@yahoo.co.in

Received 1 December 2008; revised 6 June 2009; accepted 9 June 2009;posted 10 June 2009 (Doc. ID 104725); published 9 July 2009

Galois field (GF) algebraic expressions have been found to be promising choices for reversible andquantum implementation of multivalued logic. For the first time to our knowledge, we developed GF(4) adder multivalued (four valued) logic circuits in an all-optical domain. The principle and possibilitiesof an all-optical GF(4) adder circuit are described. The theoretical model is presented and verifiedthrough numerical simulation. The quaternary inverter, successor, clockwise cycle, and counterclockwisecycle gates are proposed with the help of the all-optical GF(4) adder circuit. In this scheme differentquaternary logical states are represented by different polarized light. A terahertz optical asymmetricdemultiplexer interferometric switch plays an important role in this scheme. © 2009 Optical Societyof America

OCIS codes: 200.4660, 200.1130, 200.3760, 060.4510, 060.7140, 230.5440.

1. Introduction

The development of different multivalued logic(MVL) systems has received considerable interestall over the world [1]. Ternary (three-valued) andquaternary (four-valued) logic can be mentioned inthis regard. Galois field (GF) is a fundamental alge-braic structure in the theory of algebras. It hasproved high efficiency in various applications of logicsynthesis among others. Quaternary GF logic is animportant special case of multivalued GF logic sinceit is the smallest nonprime field that allows four-valued input–output functions to be realized inbinary circuits without the need to utilize any donot cares (i.e., no redundant unused encoding), whichis in contrast with the ternary case, for example. Thiscan be achieved by using two two-valued variables toencode a single four-valued variable without any do

not cares; an issue that is implemented in the univer-sal logic module (ULM) realization of four-valuedinput–output functions. Much effort has beenexpended in the field of electronic and quantum com-puting to incorporate MVL in information processing[2–6], but little effort has been devoted to the reali-zation of MVL with optics. In our recently publishedpapers we proposed and described some all-opticalcircuits for MVL and information processing systems[7–9]. Here we develop a theoretical model of a GF(4)adder circuit in an all-optical domain. This all-opticalGF(4) adder circuit is designed by use of a terahertzoptical asymmetric demultiplexer (TOAD) binaryXOR (BXOR) gate reported in [10]. The GF(4) adderquaternary inverter (3 − x), successor [ðxþ 1Þmod4],clockwise cycle [ðxþ bÞmod4], and counterclockwisecycle [ðx − bÞmod4] in an all-optical domain are alsoproposed. Here x is the input and x, b ∈ f0; 1; 2; 3g.These are the basic quaternary logic gates, and thenecessary truth table is given in Table 5. Clockwiseand counterclockwise cycles are equivalent to the

1 August 2009 / Vol. 48, No. 22 / APPLIED OPTICS E35

modulo-4 adder and subtractor, respectively. Forquaternary data processing in optics, the quaternarylogic states {0, 1, 2, 3} can be represented by fourdiscrete polarized states of light as outlined below:

0=no light,1=vertically polarized light (↕),2=horizontally polarized light (•),3=partially/mixed polarized light (⇕).

The principle of operations and theoretical modelof polarization encoded all-optical GF(4) adder cir-cuit with the help of BXOR is presented in Section 2.The computer simulation result that confirms the de-scribed methods is given in Section 3. The all-opticalquaternary inverter, successor, clockwise cycle, andcounterclockwise cycle gate using GF(4) addercircuits are proposed in Section 4.

2. Design of the All-Optical GF (4) Adder Circuit

Quaternary Galois field (QGF) or GF(4) is an alge-braic structure that consists of the set of elementsf0; 1; 2; 3g [11–13]. Mathematically it can be writtenas A

B, where

denotes the GF(4) addition opera-tion. GF(4) addition is defined in Table 1. In generalthe attractive properties of the GF circuits are due tothe fact that the GF operations exhibit the cyclicgroup property. This characteristic is useful in de-tecting faults, for example, because any singlechange in the inputs of the gate will cause a changein the output (s). Cyclic group property can be ex-plained from the QGF operators shown in Table 1.It should be noted that in any row and column ofthe addition table, the elements are different, whichis cyclic, and the elements have a different order ineach row and column. In binary, for example, the GF(2) addition operator XOR has the cyclic group prop-erty. In our all-optical GF(4) circuit we used theTOAD base binary XOR (BXOR) gate.

A. Binary XOR with the TOAD Base Optical Tree

The TOAD gate has an important role in opticalcommunication and information processing [14–21]. The TOAD consists of a loop mirror with an ad-ditional intraloop 2 × 2 (ideally 50:50) coupler. Theloop contains a control pulse (CP), which is verticallypolarized light, and a nonlinear element (NLE) thatis offset from the loop’s midpoint by a distance Δx asshown in Fig. 1. In our earlier paper we reported onthe TOAD base optical tree architecture (OTA) fortwo input binary XOR operations [10]. Tree architec-ture is a multiplying system of a single straight pathinto several distributed branches and sub-branch

paths. This structure is explained in Fig. 2 (upper leftcorner). Here light beams MN emitting from a pointM break into two parts, NO and NP. These twobeams break again into four parts, i.e., NO to OQ,OR, and NP to PS and PT. The schematic diagramfor two input BXOR with the TOAD OTA is shown inFig. 2. Here TOAD switches S1, S2, and S3 are placedat positions N, O, and P, respectively. A horizontallypolarized pulsed light source (HPLS) is placed at po-sitionM, which can be directed to any line by suitablebranch selection using two control inputs A and B.This BXOR circuit has an important role in the designof an all-optical GF(4) adder circuit.

B. Operating Principle of the GF (4) Adder Using BXOR

The all-optical GF(4) adder circuit that uses the BXORdevice is shown in Fig. 3. The results of numericalsimulation are given in Fig. 4. In Fig. 3, X and Yare the quaternary inputs that can take any one ofthe four quaternary logic states. They fall on polar-izing beam splitters PBS1 and PBS2 as shown inFig. 3. When vertically polarized or s-polarized light(↕) from X is incident on PBS1, it travels along X1. If

Table 1. Truth Table of the Quaternary Galois Field Addition[GFð4Þþ]

X\Y 0 1 2 3

0 0 1 2 31 1 0 3 22 2 3 0 13 3 2 1 0

Fig. 1. TOAD-based optical switch.

Fig. 2. (Color online) All-optical circuit for binary XOR with theTOAD optical tree. BS, beam splitter; HPLS, horizontally polar-ized pulsed light source; M, position of HPLS; ðN;O;PÞ are thenodes of the tree, where the TOAD switches are placed.

E36 APPLIED OPTICS / Vol. 48, No. 22 / 1 August 2009

horizontally polarized or p-polarized light (•) is inci-dent on PBS1, it travels straight along X2. The elec-tric field vector of p-polarized and s-polarized lightcan be represented as ~E∥ ¼ xEx cosðωt − k0 þ δxÞand ~E⊥ ¼ yEy cosðωt − k0 þ δyÞ, respectively, whereω is the angular optical frequency; Ex and Ey arethe electric field amplitudes along x and y, respec-tively; k0 is the free space wavenumber; and δxand δy are the absolute phases. When light consistingof vertical and horizontal polarization (⇕) is incidenton PBS1, one component, i.e., the vertically polarizedlight (↕) goes along X1 and the other component, i.e.,the horizontally polarized light (•) goes straightalong X2. Vertically polarized light (↕) from PBS1is connected with BXOR, i.e., BXOR2, through anerbium-doped fiber amplifier (EDFA). It acts asone of the input signals (A2) to BXOR2. The horizon-tally polarized light (•) from PBS1 is passed througha polarization converter (PC), which is preferably aλ=2 plate with a 45∘ azimuth angle of optic axis thatconverts vertically polarized light (↕) into horizontal(•) polarized light and vice versa and is connectedwith BXOR1 through an EDFA, and acts as one ofthe input signals (A1) to BXOR1. When polarizedlight from Y is incident on PBS2, the necessary con-nections are made the same way as stated above andare shown in Fig. 3. Light that travels along Y1 actsas another input signal (B2) to BXOR2. Light throughthe Y2 path acts as another input signal (B1) toBXOR1. Hence the output of BXOR1 and BXOR2 isequivalent to logical operations ðA1⊕B1Þ andðA2⊕B2Þ, respectively. Output of BXOR2 is sentthrough a PC and is connected to the output ofBXOR1 through a polarization beam combiner(BC) to get the final quaternary output at O. ThePBS can also be used as a BC [22], which can actuallybe used as an encoder unit [23]. Here the GF(4) is apolarization-based device, so all the connections arebased on polarization-maintaining (PM) fiber. Let usexplain the operation in detail.

Case 1: when X ¼ 0, Y ¼ p (p ¼ 0; 1; 2; 3): In thiscase as X is zero, so one input of both the XOR gate iszero (A1 ¼ 0 and A2 ¼ 0).

• Now, if Y ¼ 0, then all the inputs of BXOR1 andBXOR1 are zero. Hence no light emerges throughoutput O. Hence the output is zero.

• Now, if Y ¼ 1ð↕Þ, then the vertically polarizedlight pulse (↕) is incident on PBS2 and travels alongY1. No light emerges from Y2. Hence, B1 ¼ 0 andB2 ¼ 1. So, the output of BXOR1 is zero and the out-put of BXOR2 is a horizontally polarized light pulse(•). As it passes through the PC before its final out-put, the final output is a vertically polarized lightpulse (↕), i.e., 1.

• Now, if Y ¼ 2ð•Þ, the horizontally polarizedlight pulse (•) is incident on PBS2 and comes outalong Y2. No light emerges from Y1. Hence, B1 re-ceives a vertically polarized light pulse (↕) andB2 ¼ 0. So, the output of BXOR1 is a horizontally po-larized light pulse (•). Hence, the final output is ahorizontally polarized light pulse (•), i.e., 2.

• When Y ¼ 3, the input light that consists ofvertical and horizontal polarization components isincident upon PBS2. Hence, the vertically polarizedlight pulse (↕) comes out along Y1 and the horizon-tally polarized light pulse (•) comes out along Y2.Output of BXOR2 receives a horizontally polarizedlight pulse (•) and becomes a vertically polarizedlight pulse (↕) after passing through the PC. The out-put of BXOR1 is also a horizontally polarized lightpulse (•). Hence the final output is O ¼ 3 (⇕), i.e.,mixed polarized light.

The above discussion shows that, if X ¼ 0, the out-put takes the same logical state as that of input Y .Similarly, it can be shown that output O takes thesame logical state as that of input X when Y ¼ 0.This proves the first row and first column of the truthtable of the GF(4) adder.

Other Cases:Depending on the logic states of inputs X and Y ,

the different paths of the all-optical GF(4) addercircuit receives different types of polarized light.Accordingly, we get the final output, as is shown inTable 2. The results (the different polarized lightstate) shown in Table 2 prove the different rowsand columns of the truth table (Table 1) of the GF(4) adder.

1. Theoretical Background:

The quaternary input, X and Y , are Gaussian innature. Their power can be written as

PX ;YðtÞ ¼Xn;m

�ajE0

cpj2σ ffiffiffiπp exp

�−ðt − nξÞ2

σ2�y

þ bjE0

cpj2σ ffiffiffiπp exp

�−ðt −mξÞ2

σ2�x

�; ð1Þ

Fig. 3. (Color online) All-optical GF (4) adder circuit: ▹: EDFA,BC, beam combiner; PC, polarization controller; BXOR, binaryXOR gate.

where y and x represent vertically polarized andhorizontally polarized light, respectively; E0

cp is theenergy of the input pulse; σ is the full width athalf-maximum (FWHM); and ξ is the bit period.For pulse train {01230123…}, n ¼ 1 for 2,3,6,7,10,11… and m ¼ 2 for 3,6,7,10,11…. Also, a and bare 1 or 0 depending on the logical state of Xand Y . Because at 0 ps no light (NL) pulseexists, at ξ ps, a vertically polarized light pulseðm ¼ 1;a ¼ 1; b ¼ 0Þ, at 2ξps, a horizontally polar-ized light pulse ðm ¼ 2;a ¼ 0; b ¼ 1Þ, at 3ξps, amixed polarized light pulse (m ¼ 3, a ¼ b ¼ 1 andso both components exist at the same time) shouldbe created and so on. For logical state 0 (a ¼ b ¼ 0)the Jones vector of the input is

Jinput ¼�00

for logical state 1ða ¼ 1; b ¼ 0Þ,

Jinput ¼�

0Eyeiδy

for logical state 2 ða ¼ 0; b ¼ 1Þ,

Jinput ¼�Exeiδx

and for logical state 3 a ¼ b ¼ 1,

Jinput ¼�Exeiδx

Eyeiδy

where δx;y represents the phases of each component.The Jones matrix of a PBS is Mi ¼ Rð−αÞ·Pð0Þ · RðαÞ, where i ¼ x and y such that

Mx ¼�0 00 1

My ¼�1 00 0

The Jones matrix of the PC (λ=2 plate with azimuthangle θ with the optical axis) is

Mλ=2ðθÞ ¼�cos 2θ sin 2θsin 2θ − cos2θ

So the power at A1 and A2 or B1 and B2 can bewritten as

PA1 ¼ PB1 ¼ jMλ=2ðθÞ ·My · Jinputj2 ¼ jExj2;PA2 ¼ PB2 ¼ jMx · Jinputj2 ¼ jEyj2:

Here we choose θ ¼ 45∘ such that vertically polar-ized light (↕) is converted to horizontal (•) polarizedlight and vice versa when it passes through the PC.

For X ¼ Y ¼ 0, Ex ¼ Ey ¼ 0, hence PA1 ¼ PA2 ¼PB1 ¼ PB2 ¼ 0. For X ¼ Y ¼ 1, Ex ¼ 0, hence PA1 ¼PB1 ¼ 0 and PA2 ¼ PB2 ¼ jEyj2. For X ¼ Y ¼ 2,Ey ¼ 0, hence PA1 ¼ PB1 ¼ jExj2 and PA2 ¼ PB2 ¼ 0.And for X ¼ Y ¼ 3, Ex ≠ 0 and Ey ≠ 0 so, PA1 ¼ PB1 ¼jExj2 and PA2 ¼ PB2 ¼ jEyj2. These are the control sig-nals of the BXOR with the TOAD OTA as shown inFigs. 2 and 3. The output power at port 1 and port2 of S1 in the OTA (shown in Fig. 2) can be expressedas [15–17,21]

½Pport1ðtÞ�S1 ¼ PVPLSðtÞ4

�GcwðtÞ þGccwðtÞ

− 2ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiGcwðtÞ ·GccwðtÞ

pcosðΔφÞ

�; ð3Þ

½Pport2ðtÞ�S1 ¼ PVPLSðtÞ4

þ 2ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiGcwðtÞ ·GccwðtÞ

pcosðΔφÞ

�; ð4Þ

where Δφ ¼ ðφcw − φccwÞ is the phase difference be-tween clockwise (cw) and counterclockwise (ccw)pulses. GcwðtÞ and GccwðtÞ are the power gainand Δφ ¼ − α

2 ln�

GcwGccw

, where α is the linewidth

enhancement factor (here we consider d2 ¼ k2 ¼

Table 2. Different State of Light Present in Different Paths in an All-Optical GF(4) Adder Circuit

Quaternary Input State of Light Present in Different Paths Final Output

X Y X1 X2 Y1 Y2 A1 A2 B1 B2 BXOR1 BXOR2 O

1(VPL) 1(VPL) VPL NL VPL NL NL VPL NL VPL NL NL 0(NL)1(VPL) 2(HPL) VPL NL NL HPL NL VPL VPL NL HPL HPL 3(MPL)1(VPL) 3(MPL) VPL NL VPL HPL NL VPL VPL VPL HPL NL 2(HPL)2(HPL) 1(VPL) NL HPL VPL NL VPL NL NL VPL HPL HPL 3(MPL)2(HPL) 2(HPL) NL HPL NL HPL VPL NL VPL NL NL NL 0(NL)2(HPL) 3(MPL) NL HPL VPL HPL VPL NL VPL VPL NL HPL 1(VPL)3(MPL) 1(VPL) VPL HPL VPL NL VPL VPL NL VPL HPL NL 2(HPL)3(MPL) 2(HPL) VPL HPL NL HPL VPL VPL VPL NL NL HPL 1(VPL)3(MPL) 3(MPL) VPL HPL VPL HPL VPL VPL VPL VPL NL NL 0(NL)aNote: VPL, vertically polarized light (↕); HPL, horizontally polarized light (•); MPL, mixed polarized light (⇕); NL, no light.

1=2 as the ideal 3dB 50:50 coupler). In the absence ofa control signal, the CP is off, the data signal (incom-ing signal) enters the fiber loop, passes through thesemiconductor optical amplifier (SOA) at differenttimes as they counterpropagate around the loop,and experiences nearly the same unsaturated ampli-fier gain of the SOA (NLE), and recombine at theinput coupler, i.e, Gccw ≈ Gcw. Then Δφ ≈ 0. Hence,Pport1ðtÞ ≈ 0 and Pport2ðtÞ ≈ PVPLSðtÞ ·Gcw, whichshows that data are reflected back toward the source.When a CP is injected into the loop (CP is on), it

saturates the SOA at time ts and changes its indexof refraction. The gain of the SOA decreases rapidlyas [15]

GðtÞ ¼ 1

�1 − 1

�exp

�−

EcpðtÞEsat

� ; ð5Þ

where Esat is the saturation energy of the SOA, G0 isthe unsaturated single-pass amplifier gain, and

EcpðtÞ ¼Zt

−∞

Pcpðt0Þdt0 ð6Þ

is the energy fraction contained in the leading edge ofthe pulse until moment t0 ≤ t. By definition, Ecpðt →∞Þ ¼ Ec ¼ total energy of the CP. After a while, thegain recovers due to carrier injection and can be ob-tained from the gain recovery formula [15]

GðtÞ ¼ G0

�GðtsÞG0

�exp½−ðt−tsÞ=τe�

; t ≥ ts; ð7Þ

where τe is the gain recovery time. When the periodicpulse train is inserted into the SOA, there is no timeto recover the gain toG0, but there is recovery time tothe lower Gl [24,25]. Hence Eq. (5) takes the form

GðtÞ ¼ f1 − ð1 − 1=GlÞ exp½−EcpðtÞ=Esat�g−1: ð8Þ

Here we consider Gaussian pulse

PcpðtÞ ¼Ec

σ ffiffiffiπp exp�−t2

σ2�

as the control signal and σ is related to the FWHMby TFWHM ≅ 1:665σ. Then we can write

EcpðtÞ ¼Ec

�1þ erf

�tσ

��; ð9Þ

where erf ð:Þ is the error function. The SOA satura-tion time is ts ≈ TFWHM, then 99% of the pulse trans-mits through the SOA. Then from Eq. (8) we obtain

Gf ¼ GðtsÞ ¼Gl

Gl − ðGl − 1Þ expð−Ec=EsatÞ: ð10Þ

Now, after time ξ (bit period), the SOA gain doesnot reach G0 but does reach Gl. So,

Gl ¼ GðξÞ ¼ G0

�expf−ðξ−TFWHMÞ=τeg

: ð11Þ

For the next pulse, gain starts to reduce again andthe same process is repeated. The gain variation ofthe SOA of switches S1, S2, and S3 of OTA-1 andOTA-2 is plotted with time as shown in Fig. 5. Asa result, the two counterpropagating data signalswill experience differential gain saturation profiles,i.e., Gccw ≠ Gcw. We can define the gain ratio as

�fexp½−ðtþT−tsÞ=τe�−exp½−ðt−tsÞ=τe�g; ð12Þ

where T is the eccentricity of the loop. Thereforewhen two counterpropagating data signals recom-bine at the input coupler, Δφ ≈ −π and the data willexit from output port 1. For this case the output canbe expressed as Pport1ðtÞ ≠ 0 and Pport2ðtÞ ≈ 0. Thetemporal duration of the switching window (τwin)that depends on the offset position of the SOA inthe loop (Δx) is given by 2Δx=cfiber, where cfiber isthe velocity of light inside the optical fiber. More spe-cifically, eccentricity of the loop must be less thanhalf of the clock period (ξ), otherwise the two counter-propagating halves of the clock pulse being processedwill not experience the gain dynamics caused bytheir synchronized control pulses but instead byothers resulting in incomplete switching. TFWHM ofthe CP must be as short as possible and ideally lessthan the switching window so that, when the ccwpulse is inserted into the SOA, the cw pulse has al-ready passed through and the SOA gain has startedto recover after saturation by the CP; otherwise thetwo clock components would overlap inside the SOA,perceiving that its nonlinear properties are only par-tially altered, thus obstructing the creation of the re-quired differential phase shift [24–27]. For a lowswitching window, T should be small. When oneset of data transmits through the switching window,the next set of data cannot pass until the gain recov-ery of the SOA takes place. Moreover, the asymmetrymust be less than the SOA gain recovery time, i.e.,TFWHM < T < ξ=2 and T < τe. A bandpass filter (F)can be used at the output to reject the CP and to passthe incoming pulse. Now, for the case of S2 and S3 inOTA BXOR, the power at different ports can beexpressed as

½Pport2ðtÞ�S2 ¼ ½Pport1ðtÞ�S14

þ 2ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiGcwðtÞGccwðtÞ

pcosðΔφÞ

�; ð13Þ

½Pport1ðtÞ�S3 ¼ ½Pport2ðtÞ�S14

− 2ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiGcwðtÞGccwðtÞ

pcosðΔφÞ

�: ð14Þ

Hence, the power at final output port O can beexpressed as

PO ¼ ½ðPport2ðtÞÞS2 þ ðPport1ðtÞÞS3�BXOR−1x

þ ½ðPport2ðtÞÞS2 þ ðPport1ðtÞÞS3�BXOR−2y: ð15Þ

3. Results and Discussion

Computer simulation (in MATHCAD 7.0) for an out-put waveform is done by taking the 10.53 Gbits/sdata rate and using the parameter for the multiplequantum well (MQW) semiconductor laser array(SLA) [15] (shown in Table 3). Figure 4 shows the out-put bit pattern 0123103223013210 with its corre-sponding input, i.e., A ¼ 0000111122223333 andB ¼ 0123012301230123; the threshold level isalso shown.We select the output contrast ratio (CR) as the op-

timization criteria, which indicates the opening ofthe eye diagram and is defined as the ratio of mini-mum output peak power for HIGH (1, 2, or 3) say

(PHMin) to maximum output peak power for ZERO

(0) say (P0Max) in decibels [28], i.e.,

CRðdBÞ ¼ 10 log�PHMin

�: ð16Þ

The specific minimum (PHMin) should be greater than

the threshold value as shown in Fig. 4. The depen-dence of the output CR on the control pulse energy(Ec) is shown in Fig. 6 [here T (eccentricity of theloop) ¼45ps is kept constant]. This graph showsthat the CR becomes maximum (∼8:59dB) atECP ∼ 700 fJ. Figure 7 shows the output CR withT (eccentricity of the loop) [here, Ec ∼ 700 fJ is keptconstant]. Here we see that the CR increases rapidly

Table 3. Parameters Used in the Simulation

Parameters Symbol Value

Injection current of SOA I 300mAUnsaturated single-pass amplifier gain G0 29:6dBLinewidth enhancement factor of the SOA α 4Gain recovery time τe 95psSaturation energy of the SOA Esat 2084 fJEccentricity of the loop of the TOAD T 45psControl pulse energy Ecp 0:336EsatFWHM of the control pulse σ 2psIncoming pulse energy Ein 0:003Esat

Fig. 4. (Color online) Simulated waveform for input (X and Y) and output (O).

at first and then decreases after T ∼ 45ps. We alsoplot (σ) (which is related to the FWHM of the CP)versus CR in Fig. 8 [here, Ec ∼ 700 fJ and T ¼ 45psis kept constant].Quality factor Q of this circuit (Fig. 3) can be

expressed as [29]

Q ¼ P1 − P0

σ1 þ σ0: ð17Þ

Here P1ðP0Þ and σ1ðσ0Þ are, respectively, the averagepower and standard deviation of the GF(4) additionoutputs at a high state (0 state). Also, the bit errorrate (BER) is obtained from

BER ¼ 12erfc

�Qffiffiffi2

p�; ð18Þ

where erfc is the complementary error function. Wealso plot the BER versus different CP energy (Ec),which is shown in Fig. 9.

The design of an all-optical GF(4) adder circuit ispresented. Some important issues and the useful-ness of this scheme are discussed as follows.

a. The model presented is simple and all-opticalin nature. To experimentally achieve results from theproposed scheme, some design issues must be consid-ered. Polarization properties of fiber, polarization-dependent loss (PDL), and degree of polarization(DOP) are to be taken into account. In high-speeddata communication (50 Gbytes/s or Tbytes/s) ran-dom change in polarization over a short period oftime can produce power fluctuation at the output.So PDL degrades the optical signal-to-noise ratio(OSNR) and also degrades the extinction ratio. APDL of 3dB could cause a 1dB power penalty [30].Optical depolarizers can be used to reduce the polar-ization-induced noise in optical sensing and mea-surement systems [22,31]. They are also effectiveto suppress polarization hole burning (PHB) inEDFA, which seriously degrades the performanceof long-distance optical fiber communication sys-tems. Again, random birefringence in optical fibers

Fig. 6. (Color online) Variation of CR with CP energy (Ec).Fig. 7. (Color online) Variation of CR with eccentricity of loop (T)of the TOAD.

Fig. 5. (Color online) Gain variation of SOA (in decibels) of TOAD S1, S2, and S3 in OTA-1 and OTA-2.

induces an unpredictable rotation of the sate of polar-ization (SOP), which can be adjusted by use of a po-larization controller and PM fiber. Intrinsic crosstalk between two polarization states and imperfec-tion of polarized tracking after transmission linkcan cause polarization mode dispersion (PMD). Thismight cause a delay between both principal states ofpolarization. The effects of PMD are expected to besimilar to those of other approaches that have beenstudied in the literature [32].b. In our simulation the control pulse energy is

700 fJ as it satisfies the following criteria.

i. It might maintain a distortion-free outputpulse. Tang and Shore have experimentally shownthat the CP of energy 0:7pJ and width 1ps canproduce an output pulse that is almost free fromdistortion [33].ii. This also gives a higher CR as well as a higher

BER that is ideally required in communicationsystems.c. The simulation results demonstrate that,

although the performance of our proposed model isadequate to perform an all-optical multivalued logic

operation, the extension of the operation of thisscheme to perform faster operation (40 Gbits/s) inmodern light-wave systems is limited by the techni-cal characteristics of active modules, e.g., lasersources, SOAs, EDFAs. The required values of thecritical parameters are 3ps FWHM, CPs, and SOAgain recovery time of less than 100ps. With these va-lues, the switching energy is in the range from 20 to25 fJ, the CR is higher than 10:1, and the averagepower of an EDFA is less than 0:9mW [34]. SOA gainrecovery time is one of the important parameters forhigh-speed photonic logic operation. As a conse-quence, major improvement in performance of con-ventional bulk SOAs is required, which can beachieved by deploying successfully tested gain recov-ery reduction techniques. An alternative solution tomeet the higher speed requirements is to exploit thenovel technology of quantum dot SOAs and to takeadvantage of its attractive operational featuresand ultrafast gain dynamics to perform ultrahigh-speed all-optical signal processing.

d. For a strong power control pulse the character-istics of the SOA change due to the effect of carrierheating and spectral hole burning as well as two-photon absorption (TPA). The absorption of energyfrom the pulse results in the creation of free carriersat very high energy (∼1pJ) in the conduction band.This leads the higher carrier temperature, which inturn decreases the gain experienced by the pulse. Itis also shown that the effect of TPA is enhanced con-siderably as the pulse width of 0:2ps. Tang and Shorehave experimentally shown that the CP of 0:7pJ en-ergy and 1 ps width can produce an output pulse thatis almost free from distortion [33].

e. The core building logical unit of the proposedall-optical GF(4) adder circuit is the BXOR gate imple-mented with the TOAD. In our proposed scheme, theTOAD tree architecture is used to perform BXOR op-eration. The use of many TOADs in this specific con-figuration can increase latency and complexity, butthese problems can be minimized if XOR with twoCP TOADs is used in this circuit, as demonstratedby Zoiros et al. [27] and by Houbavlis and Zoiros [35].This alternative technological option will enhancethe potentiality of this scheme for exploitation in so-phisticated interconnections of enhanced combina-torial and sequential functionality analogous to thebinary world.

4. Applications of an All-Optical GF (4) Adder Circuit

An all-optical GF(4) adder circuit can assume an im-portant and significant role in the design of some

Fig. 8. Variation of CR with FWHM of CP (σ) in picoseconds.

Fig. 9. Variation of BER with CP energy (Ec).Fig. 10. (Color online) All-optical quaternary inverter circuit.

,all-optical GF(4) adder circuit.

quaternary logic gate in the all-optical domain. Likethe binary world there are many kinds of logic gate inthe quaternary world. Here, we design some logicaloperation, namely, the inverter, the successor [1,2],and the clockwise cycle and counterclockwise cycle[1] with the help of the GF(4) adder circuit in anall-optical domain. The Reed–Muller theory playsa significant role in this logic synthesis and circuitdesign. According to its theory any arbitrary logicalfunction f ðx1; x2;…; xnÞ can be expressed as ANDand EXOR operations to minimize the hardware com-ponent as [36]

f ðx1; x2;…; xnÞ ¼ c0⊕c1 _x1⊕c2 _x2⊕…⊕cn _xn⊕cnþ1 _x1 _xn

×⊕…⊕c2n−1 _x1 _x2… _xn; ð19Þ

where _xi is either xi or its complement and cj is a bin-ary constant (1 or 0). The ⊕ is the EXOR operation.

A. Quaternary Inverter

An arithmetic approach to inverters inR-valued logicin the literature is provided by the formula [1,2]�x ¼ ðR − 1Þ − x, where x is the original value and isalso the inverted value of �x. For quaternary logicR ¼ 4. There are 4! four-valued reversible inverters.Again there are self-reversing inverters such as [1 0 32], [2 3 0 1], and [3 2 1 0]. The identity inverter [0 1 23] is also self-reversible. In Fig. 10 we propose a cir-cuit of an all-optical polarization encoded self-reversing inverter [3 2 1 0] with the help of theGF(4) adder circuit. Here one input (x) takes anyone of the four logical states whereas the other inputtakes logical states 3 as shown in Fig. 10. The circuitwill act as a quaternary inverter; if input x takes [0 12 3], the output will be [3 2 1 0]. This is confirmed in

Tables 1 and 2 that list operational details of the GF(4) adder circuits.

B. Quaternary Successor

The mathematical expression for quaternary succes-sor is [1,2] SucðxÞ ¼ ðxþ 1Þmod4. The truth table isgiven in Table 4. With the all-optical GF(4) addercircuits. we designed the quaternary successorshown in Fig. 11. The scheme consists of two GF(4) adder circuits, one PBS, one BS, one PC, andone BC. The different states at different positionsare shown in the circuits.

C. Quaternary Clockwise Cycle and CounterclockwiseCycle

The mathematical expressions for quaternary cwcycle (Xb) and ccw cycle (Xb

c) are [1]

Xb ¼ ðxþ bÞmod4; ð20Þ

Xbc ¼ ðx − bÞmod4; ð21Þ

where b can be any logical states ∈ f0; 1; 2; 3g. Thetruth table is given in Table 4. The quaternary cwcycle and ccw cycle can be easily designed with thehelp of an all-optical GF(4) adder and successor cir-cuits as shown in Fig. 12.

5. Conclusion

A novel scheme of an all-optical GF(4) adder circuithas been proposed and described. The theoreticalmodel was presented and verified through numericalsimulation. The feasibility and potentiality of the GF(4) adder circuit to perform some quaternary logicgate was also discussed. These basic quaternary logiccircuits such as the quaternary inverter, the succes-sor, the clockwise cycle, and the counterclockwise cy-cle gates have significant and important roles inmultivalued logic all-optical information processing.

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Table 4. Truth Table of Quaternary Inverter, Successor, Clockwise,and Counterclockwise Cycles

Input (X)

Outputs

Inverter Successor

Clockwise andCounterclockwise

Cycles

X1orXc3 X2orX

c2 X3orX

0 3 1 1 2 31 2 2 2 3 02 1 3 3 0 13 0 0 0 1 2

Fig. 12. (Color online) All-optical quaternary cw cycle and ccwcycle circuit; Suc, quaternary successor circuit.

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Quaternary Galois field adder based all-optical multivalued logic circuits

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