Readout Channel with Majority Logic Timestamp and Digital PeakDetector for Muon Chambers of the CBM Experiment

E. Atkin1, I. Bulbakov1, V. Ivanov1,3, P. Ivanov1, E. Malankin1, D. Normanov1, I. Sagdiev1,V. Samsonov1,3, V. Shumikhin1, O. Shumkin1, S. Vinogradov1, A. Voronin1,2

1National Research Nuclear University MEPhI, Moscow, Russia2Skobel’tsyn Institute of Nuclear Physics, Moscow State University, Russia

3Petersburg Nuclear Physics Institute, NRC Kurchatov Institute, Gatchina, Russia

Abstract

A prototype readout channel was manufactured in UMC CMOS 180 nm forthe purpose of the CBM experiment at the FAIR accelerator. The channelincludes a preamplifier with fast and slow CR-RC shapers, discriminator witha differential threshold setup circuit, 6 bit SAR ADC (40 MSps, 1.5 mWpower consumption), digital peak detector and block of the time stampregistration. The control data, clock and output data are supplied through aSLVS transmitter and receiver. The slow and fast channels have an 1500 e−

and 2000 e− ENC accordingly at a 50 pF detector capacitance. Powerconsumption is 10 mW/channel.

ASIC Structure

The MUCH detector is built with GEMs. Since the sensors will have differentgranularity, the requirements to the front-end electronics are also different forthe central and peripheral parts. Thus, the preamplifier is followed by twocircuits: a slow channel, optimized for S/N ratio in order to use it in theperiphery, and a fast one, adapted to the hit rate of the inner detector part,where the occupancy is the highest. The fast channel is also supposed to beused for the timestamp determination. Both channels are realized withCR-RC shapers with different peaking times, 60 ns and 260 ns accordingly.The channel is optimized to operate with the negative charge polarity. Thepreamplifier dynamic range is 100 fC. The channel occupancy is up to 1MHz. The signal from either the slow or fast shaper (depends on occupancy)is processed by a 6 bit SAR ADC. The ADC is followed by a digital peakdetector. The chip has fast and slow discriminators. The fast discriminatoroutput is connected to a timestamp block. Both fast and slow discriminatorscan be used by the logic for hit overlap detection. In the current version thedata from ADC, peak detector and timestamp are serialized and sent out viaan SLVS transmitter.

Analog Channel

Generator tests of the prototype ASIC functionality were provided. The testpulse from generator was supplied through the serial capacitance 1.2 pF.Functionalities of the CSA, Shapers, Comparators and DAC were checked.

CSASHAPER SLOW

SHAPER FAST

Majority Logic Timestamp

The timestamp block contains three Gray code counters which specify theglobal chip time. The signal from the fast discriminator starts the timestampblock. Value from counters is recorded to the local channel time registers.After that, the majority logic block compares data from registers and sendsthem to the timestamp output.

Digital Peak Detector

The digital peak detector finds thepeak in the ADC data. The peakdetector has a function of preventingfalse peak finding due to the presenceof noise spikes. The average sum ofthe previous three ADC samples iscompared with the current samplemultiplied by reduction factor. If theaverage sum is less than the currentsample, it means that the found peakis false.

ASIC Layout

The MUCH ASIC v3 was designed and prototyped via Europractice by meansof the 0.18 µm CMOS MMRF process of UMC. The die size is 3240 x 1525µm2.

References

•E. Atkin et al. 2015 JINST 10 C04006

•E. Malankin et al. 2016 JINST 11 C01084

Contacts

E. Malankin, ASIC lab and the Department of Electronics,National Research Nuclear University ”MEPhI”, Kashirskoe shosse 31, Moscow, 115409,Russia.

E-mail: ezmalankin@mephi.ru, tel. +7 499 3242597