Regular Expression Manipulation FSM Model Sequential Machine Theory Prof. K. J. Hintz Department of...

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Regular Expression ManipulationFSM Model

Sequential Machine Theory

Prof. K. J. HintzDepartment of Electrical and Computer

Engineering

Lecture 5

Modifications by Marek Perkowski

Null MachineNull MachineNull MachineNull Machine3 Methods for Proving That a Machine

Accepts No Words– By inspection

• Any path from the start state to a final state means that at least one word is accepted by the machine

– By state diagram manipulation• If a final state is relabeled as a start state, then the

machine must accept at least one word

Null MachineNull Machine

– By converting the regular expression into a deterministic FA

• If possible, FA must accept at least one word

• Conversion to FA may not be possible– Machine may have no final states.

– There is no path from the initial state to any final state.

Give examples

Reachability AnalysisReachability Analysis

Reachability analysis will

show that this machine will

never reach the final state

starting from initial state.

Show it.

Discuss reachability for computer hardware and robotics

State Diagram ManipulationState Diagram ManipulationA procedure to determine if a machine

accepts no strings1. Remove all edges (arrows) to the start

state.2. From the start state, identify all single-step

“next states.”3. Relabel these “next states” as start states

and eliminate the edges used to get there.4. go to (b)5. If a final state is relabeled as a start state,

then the machine must accept at least one word.

State Diagram ManipulationState Diagram Manipulation

Does Not Accept Any

Word Since

There Is No

Path From

- To +.

The final state is not not reachablereachable

The Complement MachineThe Complement MachineThe Complement MachineThe Complement Machine

• A Complement Machine Accepts All Expressions Other Than Those Accepted by the Original Machine

• Method– Change all non-final states into final states– Change all final states into non-final states– Leave start state unchanged

Language DecidabilityLanguage Decidability

Methods for Determining If Two Regular Expressions Define the Same Language– Language Enumeration with 1:1

correspondence between the 2 languages.– The regular languages can be accepted by

identical FAs.– Generate

L L L L Loverlap 1 2 2 1

This example demonstrates why it is useful to be able to check if language is empty

This is like xor of languages

Language OverlapLanguage Overlap

• If the Overlap Language Is NOT the Null Set, Then There Is Some Word in L1 Which Is Not Accepted by L2 and Vice Versa.

• If the Overlap Language Accepts the Null String, Then the Languages Are Not Equal.

L 1L 2L 1

DeMorgan’s TheoremDeMorgan’s Theorem

Applies Equally Well to Sets As Well As Boolean Algebra

Regular Expression Regular Expression EquivalenceEquivalence

Methodology– Construct the complement machines– Apply DeMorgan’s theorem since it is difficult

to form the intersect machine

L L L L L

L L L L

overlap

1 2 2 1

Show some special cases when it is easy to create the intersect

machine

Regular Expression EquivalenceRegular Expression Equivalence

Take the Unions of the Complemented and Non-complemented Several Times to Determine whether Language overlap is the Null Set or not

RE Equivalence Example*RE Equivalence Example*RE Equivalence Example*RE Equivalence Example*

Two REs are represented by their equivalent FAs (FA1 does = FA2)

*Cohen, Prob. 2, page 233.

Try to use first machine minimization method and

isomorphism

stateObviously looking at these two machines we see that they are equivalent, but how to

prove it?

RE Equivalence ExampleRE Equivalence Example

Form the Complement Machines

Make the Product Machine of FA2 and the Complement of FA1.

• States of Product Machine, FA1-bar & FA2

• Only One Start State / Multiple Final States

Start/Final -/+

New State State Vector

-/+ 1 ( p1, y1 )

+ 2 ( p1, y2 )

+ 3 ( p1, y3 )

Start/Final -/+

New State State Vector

4 ( p2, y1 )

+ 5 ( p2, y2 )

6 ( p2, y3 )

Product Machine State Table

Start/Final -/+

Present State a b

-/+ 1 5 3 + 2 5 3 + 3 5 3 4 5 3

+ 5 5 3 6 5 3

• States of Product Machine,

FA1-bar & FA2

State Diagram of Product

Reduced State DiagramReduced State Diagram

Non-Reachable States 2,4,6, are Removed

• Take the Complement Of the Union by changing final states to non-final and vice-versa

• No Final States, So Complement FA Accepts No Words

Do the Same for the Right Term of Loverlap

• Application of Same Procedure to Preceding Machine Also Results in No Recognizable Words.

• Since Both Terms of Loverlap are Null, Then REs Are Equivalent Since Their Union Is Null.

Finally we proved that these two machines are equivalent without the

need to minimize them.

Moore & Mealy MachinesMoore & Mealy MachinesMoore & Mealy MachinesMoore & Mealy Machines

• The Behavior of Sequential Machines Depends on Previous Inputs.– Moore Machine

• Output only depends on present state

– Mealy Machine• Output depends on both the present state and the

present input

Moore & Mealy MachinesMoore & Mealy Machines

Equivalent Descriptive Methods– Transition (state) table– Transition (state) diagram– Operational descriptions using set theory– (Language recognized by the machine)

Moore MachineMoore Machine

Present State

Comb Ckt

Memory

Comb Ckt

Output Is Only a Function of Present State

Output

Primitive State Diagram, MoorePrimitive State Diagram, Moore

Legend

state/output

C/0 D/0

Moore Machine State DiagramMoore Machine State Diagram

Legend

s1s0/z

10/1 11/1

Mealy MachineMealy Machine

Output Is Function of Present State AND Present Input

Present State

InputComb Ckt

Memory

Comb Ckt

Output

Primitive State Diagram, MealyPrimitive State Diagram, Mealy

Legend

input/output

off /0

Mealy Machine State DiagramMealy Machine State Diagram

Legend

x1x0 /z

Transition TableTransition Table

Present State

Variables

Input Variables

Next State

Variables

Output Variables

si xj sk zm

FSM Design ApproachesFSM Design Approaches

• “One-Hot”– One flip-flop is used to represent

each state– Costly in terms of discrete

hardware, but trivial to design– Efficient in FPGAs because FF part

of each CLB• Binary Coded State

– n flip-flops used to store 2n states– Most efficient– Need to account for unused states

Review the one-hot coded machines

and transition from non-deterministic to deterministic. Discuss parallel

state machines and similar diagrams

like Petri nets

FSM and ClocksFSM and Clocks

• Synchronous FSMs may change state only when a unique input, the clock, occurs

• Asynchronous FSMs may change state when input changes

• Next state depends on present input and present state for both Moore and Mealy

Synchronous versus Asynchronous Machines in Design

• Synchronous FSMs– Easier to design, turn the crank– Slower operation

• Asynchronous– Harder to design because of potential for races,

iterative solutions– Faster operation

Mealy “0101” DetectorMealy “0101” Detector

M = ( S, I, O, )

S: { A, B, C, D }

I: { ‘0’, ‘1’ }

O: { 0, 1 } = { not detected, detected}

next slide

Mealy Transition/Output TableMealy Transition/Output Table

Present InputPresentState ‘0’ ‘1’

A B/0 A/0B B/0 C/0C D/0 A/0D B/0 C/1

Next State/Output

“0101“ State Diagram“0101“ State Diagram

‘1’/0 ‘0’/0

‘0’/0

‘1’/0‘1’/0

‘0’/0

‘1’/1

‘0’/0

This machine detects

sequence whenever it

appears, mention smart

house for disabled and heart attack

devices

Moore “0101” Detector Moore “0101” Detector

M = ( S, I, O, )

S: { A, B, C, D, E }

I: { ‘0’, ‘1’ }

O: { 0, 1 } = { not detected, detected}

next slide

Moore Transition/Output TableMoore Transition/Output Table

Present InputPresentState ‘0’ ‘1’

Output()

A B A 0B B C 0C D A 0D B E 0E D A 1

Next State

Moore “0101“ State DiagramMoore “0101“ State Diagram

D/0C/0

B/0‘1’

‘0’

‘1’‘1’

‘0’

‘0’ detected

“01” det“010” det

“0101” det‘1’

‘0’‘1’

One state more.

Sequential Machines Sequential Machines ProblemsProblems

Three Problems of Sequential Machines– State minimization problem

• Determine all equivalent states of a sequential machine, and,

• Eliminate redundant states

– Machine Decomposition• Separate large machines into an interconnected set

of smaller machines

• Easier to design and analyze small machines

Instead to minimize, create minimal machine

in first run.

Instead to decompose, create decomposed machine in first run.

Good but not always realistic advises:

Sequential Machine ProblemsSequential Machine Problems

– State assignment problem• There is no guidance on which binary number to

assign to which state in a primitive state table

• Complexity of implementation is dependent on mapping of states to binary numbers

• Unsolved problem– Design all machines and compare

– Benefit of decomposition of large machine into smaller machines.

Set Theoretic DescriptionSet Theoretic Description

Moore Machine is an ordered quintuple

Moore= S I O

, , , ,

Finite set of states , s s s

Finite set of inputs , i i i

Finite set of outputs , o o o

Next state function which maps

Output function which maps

Set Theoretic DescriptionSet Theoretic Description

Mealy Machine is an ordered quintuple

maps whichfunctionOutput

maps whichfunction stateNext

o,,o,o, outputs ofset Finite

i,,i,i, inputs ofset Finite

s,,s,s, states ofset Finite

=Mealy

Recursive Definitions of DeltaRecursive Definitions of Delta

State Transition for Moore & Mealy– Single-valued, else not deterministic.– At least a partial function– Not necessarily injective or surjective– Shield’s nomenclature

: , , ,

s i sk k k1

Recursive Definitions of DeltaRecursive Definitions of Delta

is none or more occurrances of the definition

of a particular mapping from

. ., a string

then define

* , , . ., the response to a null string

is no state change

s e s i e

Recursive Definitions of BetaRecursive Definitions of Beta

• Causal, No Output for No Input.

• For a Given Input Sequence, There Will Be a Deterministic Output Sequence of the Same Length As the Input.

1 kkk ois

Recursive Definitions of LambdaRecursive Definitions of Lambda

Same Caveats As Beta

xxsasxas

,,*.,.,*

sk sk-1

Possible Exam ProblemsPossible Exam ProblemsPossible Exam ProblemsPossible Exam Problems• Find if two state machines (of any type, Mealy,

Moore or Rabin-Scott) describe the same regular language.

• Find if a machine describes an empty language.• Find a regular language accepted by arbitrary

type state machine, specified in any way (graph, table,etc.).

• Find the intersection, the union, the difference of two machines M1 and M2.

• Find a negation of a machine M.

Possible Exam ProblemsPossible Exam ProblemsPossible Exam ProblemsPossible Exam Problems

• Find Mealy Machine for arbitrary sequence detection.

• Find Moore Machine for arbitrary sequence detection, finite or infinite sequence over arbitrary alphabet.

• Convert a Mealy Machine to an equivalent Moore Machine.

• Convert a Moore Machine to an equivalent Mealy Machine.

Regular Expression Manipulation FSM Model Sequential Machine Theory Prof. K. J. Hintz Department of...

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