Post on 19-Mar-2020
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Results from the Cibola Flight Experiment’s 1st YearExperiment s 1 Year
Michael CaffreyKeith MorganKeith Morgan
Anthony SalazarDiane Roussel-Dupre
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 1
Rad-Hard Space Processing:Lags ground-based processing by 10 years!Lags ground-based processing by 10 years!
CFE RCC
Exponential increase in cost to fabricateAverage cost of .35µ 200mm Fab= $880/M
• Milspace small % of market• Disappearing Rad-Hard foundries• Eroding Rad Hard Market
Average cost of .35µ 200mm Fab $880/MAverage cost of .25µ 200mm Fab=$1329/M
# of Rad-Hard manufactures
• Eroding Rad-Hard Marketcommercial space weak
• Low Volume Demand->Difficult times ahead for space processing
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 2
Difficult times ahead for space processing->Need alternate technologies to meet needs
CFE Concept“Continuous, full bandwidth signal processing to deliver real-time data products to users”to de ve ea t e data p oducts to use s
Technology Demonstration:FPGA based parallel computing offers 100x performance advantage and adaptability• Processing gain => greater sensitivity, data reduction
R bl b t i i b l l l ith /t t• Reprogrammable => combats mission obsolescence, leverages new algorithms/targets after launch
Leveraging COTS technology • Reuse of commercial design tools, foundry, processes, masks
— Reduces lead time vs ASICs— Reduces validation and verification time— Enhances Government access to commercial process geometriesp g— Reduced cost (per part and foundry chasing costs)
• Fabricated on epi substrate for SEL immunity• Challenges
— Single Event Upset must be handled at system level— Relatively high power density and complex packaging issues— Parallel computing not necessarily right hammer for all problemsRaw Data
Description:
Orbit: Circular 560 Km, 35.4 degree inclinationSoftware Radio:• Four channels 20 MHz bandwidth each
Raw Data
Detection & Compression
• Four channels, 20 MHz bandwidth each• Tunable from 100 to 500 MHz, • 300 Gop/sec Re-Configurable Computer (RCC)• 4-element antenna array
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 3
CFE Project HighlightsS L h b STP (STP 1)Space Launch by STP (STP-1)
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478
CFE mated to launch adapter
FY06 CFE Project Highlights
5/24/06
Tracking Dish Installationg
7/13/06 EMI
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 5
6/15/06 Integrate Payload6/15/06 Integrate Payload
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 6
Statistics SummaryStatistics Summary
>18,000 Experiments32 UPLOADS>32 UPLOADS
From 03/01/07 to 08/25/08
18565 SOH files17 GB SOH, 244 GB SCI
Payld 9678 2 hrs 74 26%Payld 9678.2 hrs 74.26%Radio 2010.8 hrs 15.43%R1-FA 3857.7 hrs 29.60%R1-FB 3742.3 hrs 28.72%R1-FC 3744.2 hrs 28.73%R2-FA 3856.4 hrs 29.59%R2-FB 3738.6 hrs 28.69%R2-FC 3738.9 hrs 28.69%R3-FA 3774.0 hrs 28.96%R3-FB 3772.9 hrs 28.95%R3-FC 3769.1 hrs 28.92%
*seeduty,'2007-03-01','2008-04-15‘*onoff startTime endTime pSym=pSym DEBUG=DEBUG PRINTTIMES=PRINTTIMES maxTimes=maxTimes
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 7
onoff,startTime,endTime,pSym=pSym,DEBUG=DEBUG,PRINTTIMES=PRINTTIMES,maxTimes=maxTimes
CFE Payload
4x 20MHz Radios, 100-500MHz,
Reconfigurable computerReconfigurable computer
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 8
Powersupply
Payload Block Diagram
ASCM Bus
BAERad6K
Processor
EEPROM&
Space CraftInterface
s
RCCVirtex 3xFPGAProcessor withMemory dcard
EEPROM&
FLASH
RCCVirtex 3xFPGAProcessor withMemory dcard
RCCVirtex 3xFPGAProcessor withMemory dcard
2x12bitADC@100MHz
EEPROM&
FLASH
24MB, DOS FS 24MB, DOS FS
SV B
us
FPDP 200MB/ h
24MB, DOS FS 24MB, DOS FS
Radio100 - 500 MHz RF
100 - 500 MHz RF 55 - 95 MHz IF
55 - 95 MHz IF
FPDP 200MB/s each
100 500 MH RF 55 95 MHz IF
Digital Control & 50MHz RF ref
100 - 500 MHz RF
100 - 500 MHz RF
four 20MHz wide radio channels, gang tuned2 channels combined into each 50MHz RCC input
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 9
RF Signal FlowRF Signal Flow
-10
0
10ADC1
60
-50
-40
-30
-20LPA2
LPA1
0 5 10 15 20 25 30 35 40 45 50-70
-60
Frequency (MHz)
ADC2
-30
-20
-10
0
10
LPA3LPA4
Two baseline interferometerAntenna pairs occupy same portion of the spectrum
0 5 10 15 20 25 30 35 40 45 50-70
-60
-50
-40
Frequency (MHz)
Antenna pairs occupy same portion of the spectrumBandpass sampled (spectrum inverted)RF 100 – 500 MHzInstantaneous Bandwidth ~18 MHz
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 10
q y ( )100MHz 50MHz
Data FlowData Flow
IF3/4IF1/2
Mag
Freq (Note Cal Tone)
3 4
Mag
Freq (Note Cal Tone)
1 2
J223 J225
Antennas/Radio
FPDPA
IFAIFBFPDPB
J305J303
ADCFPDPAAGC
FPDPAFPDPAIF ¾ Processing
TimeseriesTimeseries100MHz,12b
RCC2 RCC1
FPDPB FPDPA
FPDPB FPDPBIF ½ ProcessingIF ¾ Processing
Cross ChannelComputation
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LA-UR-08-05478 Slide 11
RCC3
FPDPB FPDPA Computation
RCC Module Architecture & Testability
36 data3 control
RCC Module Architecture & Testability
TestPattern
Built in test will Fly•One test configuration for 9 XQVR1000•Tests system from ADC module through 3
Local SDRAM3 separate banks
each 32 x 8M
36 data
0xFF…FE0x00…000xFF…FD0x00…000xFF…FB 0x00…000xFF…F7
x3
y gRCC modules•Tests for
•Opens•Shorts•Ground Bounce
Local SDRAM3 separate banks
each 32 x 8M
36 data3 control
32 data
Buf
ferFPDP A
…
x3
•Ground Bounce•Crosstalk
•Does NOT test Si, working with Xilinx on Si test ideas for XQVR1K•Fault isolation via verifier ID and failure
Local SDRAM
36 data3 control
rB
FPDP B 32 d t
data pattern SEU Insertion•Microprocessor can inject ‘SEUs’ into the bitstream of the XQVR1K for observing upset consequences3 separate banks
each 32 x 8M
Actel controller SEU Processor configuration
Buf
fe
FPDP B data
Verify Test Pattern
x3 for observing upset consequences and testing system response
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 12
CRC
Backplane InterfaceASCM
Verify Test PatternGenerate Test Pattern
Payload Built in Self TestPayload Built in Self Test
Tests Data path from ADC Memory InterfaceProcessor Interface InterruptpSEU Detection X triggersPower LoadPower Load
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 13
Power = f(algorithm)
Each RCC board power usage ≈5 - 28W Each FPGA has >500 pins which are susceptible to thermal stresses• Maximize lifetimeMaximize lifetime
— Heat pipes limit max temperatures— Column Grid Array package more reliable— Matched CTE of thermount PCB to Ceramic Pkg— AlBeMet core has superior thermal transfer
ProtoFlight RCC Board
With heat pipes: ∆t=17 deg C
gWithout heat pipes: ∆t=50 deg C
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 14
Package Reliability
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LA-UR-08-05478 Slide 15
RCC1 Board Level +2 5V Current ConsumptionRCC1 Board Level +2.5V Current Consumption
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LA-UR-08-05478 Slide 16
RCC1 FPGA A Die TemperatureRCC1 FPGA A Die Temperature
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LA-UR-08-05478 Slide 17
Configuration SEU DetectionConfiguration SEU Detection
Parallel Connected Virtex
8b SelectMap Bus,15MHz
XQVR1KXQVR1KActel RT54SX32S
SRAMCRC
CodebookXQVR1K
Backplane InterfaceASCM 32b Local Memory Bus (w Parity), 15MHz, Interruptsy ( y), , p
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 18
Configuration Bitstream SEU Mitigation SchemeConfiguration Bitstream SEU Mitigation Scheme
Configure FPGA
SoftwareFunction
HardwareFunction
FPGAs
Load CRCCodebook
Readback FPGA
PartialConfigure
No Error
FPGAs
CalculateCRCs and Assemble
Single FrameCycle time~ 180ms for 3XQVR1000
Readback E F &CRCs and
Compare Frame
Error: Interrupt Microprocessor
Error Frame & Report
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478
Microprocessor (Device ID,Frame#,# of Frames,Exp CRC,Act CRC, Frame Data)
Vi t 1000 LEO SEU R t W i ht d D i T t lVirtex 1000 LEO SEU Rates Weighted Device Total
Forecast:
Low Earth Orbit Virtex 1000 - Total Upset Rates
1.00E+01
1.00E+02
ce-d
ay)
1.00E-01
1.00E+00
1.00E 01
SEU
(per
dev
ic
Best EstimateWorst Case
1.00E 01Sol Min Sol Max SolMin
Trap ProPeak*
SolMaxTrap Pro
Peak*
WorstWeek
WorstDay
Peak
Solar Condition
Measured: 365 SEUs / 1380 device days = .26 upsets/device day
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LA-UR-08-05478 Slide 20
Configuration SEUs by RegionConfiguration SEUs by Region
Track the time observing SEUs in each cellRecord the number, time, type, and location of configuration SEUs
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LA-UR-08-05478 Slide 21
Configuration SEUs / Device Day/ CellConfiguration SEUs / Device Day/ Cell
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LA-UR-08-05478 Slide 22
Future SEU Experiments: SAVE POWER / THROUGHPUT OVER FULL TMRSAVE POWER / THROUGHPUT OVER FULL TMR
Survey SEUs in BRAM and SDRAMDetectionDetection• -tool development and validation for smart (full / partial) detection insertion• -evaluate detection false alarm rate vs undetected upsets (golden compare)
TMRF ll d ti l TMR t l d l t dd d• Full and partial TMR tools need alarm out added
• Evaluation of alarm signal coverage
Domain Specific (software radio)• Evaluate the SNR impact of SEUs on software radio• Investigate radio specific schemes for mitigation
— Eg partition circuit on bit significance or error propagation significance• Develop tools for detection and mitigation
Detection + CorrectionDetection Correction• Lightweight model trains on circuit• Inputs are available to model if necessary (avoid if possible)• SEU results in dual redundancy error detect, model chooses correct output
Operated by Los Alamos National Security, LLC for NNSA NA-22: Office of Nonproliferation Research and Development
LA-UR-08-05478 Slide 23