RF circuit design: Basics

transcript

Akira Matsuzawa

Tokyo Institute of Technology

Contents

• Building blocks in RF system and basic performances

• Device characteristics in RF application• Low noise amplifier design• Mixer design• Oscillator design

Basic RF circuit block

Receiver

Transmitter

ImpedanceMatching

1)LowNoiseAmp. 2) Mixer

3) Oscillator

PowerAmp.

Filter

RF systems are composed of limited circuits blocks.LNA, Mixer, and Oscillator will be discussed in my talk.

Basic functions of RF building blocks

Log (f) Log (f)

dB dB1) Amplifier3) Filter

Down conversion

Up conversion

2) Mixer+ Oscillator

Desired

Undesired

Amplifier, frequency converter (mixer +oscillator), and filerare basic function blocks in RF system.

Frequency conversion

RF Amplifier

• Gain: Amplify small signal or generate large signal.• Noise: Smaller noise and larger SNR.• Linearity: Smaller non-linearity.

Non-linearity generates undesired frequency components.

.....)()()()( 33

221 +++= tvtvtvtv inininout ααα

( ) ( )( ) ( ) ( ) ( )( ) ( )( )tttttt 2121212

21 coscos2cos2cos2coscos ωωωωωωωω ++−+++=+

( ) ( )( ) ( )( ) ( )( ) ....2cos212cos

21coscos 1221

321 +−+−=+ tttt ωωωωωω

Input and output characteristics

1dBPout(1dB)

Fundamental IMD3

Slope=1Slope=3

SNR minSNR min

SFDRBDR

NoiseFloor

MDSCP1dB

Distortion and noise are important factors in RF amplifier, as well as power and gain.

Dynamic range

BWNFdBmFloorNoise log10174 ++−=

( ) min332 SNRFloorNoiseIIPSFDR −−=

SFDR: Spurious free dynamic rangeThe input power range over which third order inter-modulation productsare below the minimum detectable signal level.

BDR: Blocking dynamic range

kT limitation Bandwidth

MDS: Minimum detectable signal level= Noise Floor +SNRmin

min1 SNRFloorNoisePBDR dB −−=

Non-linearity

11 145.0

CP1dB: The input level at which the small signal gain has dropped by 1dB.

IMD3: The third order inter modulation term

IP3: The metric third order intercept point. It is the point where the amplitude ofthird order inter modulation is equal to the that of fundamental.

34αα

=IPA IIP3: Input referred intercept pointOIP3: Output referred intercept point

( )inout PIIPIMDP −⋅=− 33 2

MOS transistor

Source

gmvg’

vg’ rds

MOS Transistor Equivalent Circuit

Intrinsic gate voltage and gm are the most important factors in RF CMOS.

Cutoff frequency: fT

CingmViVi

CingmfT π2

tCIioVi

tIioIi

inCtgmIiogmViIo

ωω )cos(

fT: Frequency at which the current gain is unity.

Input current

Gate voltageS

Output current

Proportional to gmInversely proportional to Cin

For higher fT, increase gm and decrease Cin.

Amplifier gain

rrG 0⋅≈

=ωCin gmVg

Ig Id Log (G)

Log (f)

G=gmr0

o 00 ωω ==

For the larger gain

Fundamentally larger gmr0 oeff

VIgmrG ⋅

⎟⎠⎞

⎜⎝⎛

≈≈

Larger Ids or ro

Larger Q

CQLQro0

ω ==Q

Distortion and Cin increase

Veff is difficult to reduce

Higher fT and lower rs

For higher voltage gain, increase gm, fT, ro (Q), and decrease input and gate resistance

Characteristics of gm (Basic)

⎟⎠⎞

⎜⎝⎛

=⎟⎠⎞

⎜⎝⎛

2effeff VIds

gmVIdsgm

eff IWL

CnV ⋅⋅⋅=

TgsOXds

dVdIgm

⎟⎠⎞

⎜⎝⎛=

⎟⎠⎞

⎜⎝⎛=≡

⎟⎠⎞

⎜⎝⎛=−⎟

⎠⎞

⎜⎝⎛=

Scaling W/L ratio

Square law region

Gm is proportional to the Ids and inversely proportional to the Veff.

Veff is proportional to square root of Ids and inversely proportional to square root of (W/L) ratio.

dseff JLWIdsLV ⋅=∝

Veff is proportional to square root of drain current density.

Non-ideal effects to square low region

gssods

nUsIgm

⎟⎟⎠

⎞⎜⎜⎝

Sub-threshold regionLow Veff

0.2 0 0.2 0.4 0.6 0.80

3025.083

eff 0.4 10, Veff,( )

eff 0.2 5, Veff,( )

10.2 VeffVeff (V)

constnUIds

VeffIdsgm 2

/Ids (

)Mobility degradationHigh Veff

LvV ceff

μθθθμμ +≈+

( Weak inversion)

This effect becomes larger at large Veff and short channel length.

At larger Veff and lower Veff, two non-ideal effects are not negligible .

Distortion

Veff (V)

L=0.1umL=0.2um

L=0.4um

⋅⋅⋅⋅+++= 33

221 effeffeff VaVaVaIds

dVIda IPeff

ds=≡

-0.1 0 0.1 0.2 0.3 0.4 0.5

Veff (V)

Lower Veff gives higher gm, bur results in higher distortion.To obtain lower distortion ( higher IIP3), we must increase Veff.

Higher gm and lower distortion means higher Ids.

LC resonator

CQLQro0

ω ==Substrate

LC resonator can be regarded as resistance at the resonance frequency.

Substrate effect

SDSDSPAD

GateShield layer

RF power loss and noise generation

Substrate should be treated as resistive network.

This substrate resistance causes RF power loss and noise generation.

Shielding can reduce this effect.

Power loss in substrate

Rp(Ω）

1 101K 10K

Cp(pF)

1Gp(mS)

RpGp Cp

Equivalent

MOS: 10ΩcmGaAs: 1GΩcmCR

⎟⎟⎠

⎞⎜⎜⎝

⎟⎟⎠

⎞⎜⎜⎝

⎟⎟⎠

⎞⎜⎜⎝

Very low resistance or high resistance realizes low power loss.

Higher C and moderate Rsubresults in higher power loss.

GHz operation by CMOS

Cgmfπ2

The cutoff frequency of MOS becomes higher than that of Bipolar.Over several GHz operations have attained in CMOS technology

1995 2000 2005

fT : CMOS

fT : Bipolar (w/o SiGe)

D R/C for HDDIEEE 1394

CellularPhone

fT /10 (CMOS )

CDMA fT /60 (CMOS )

0.35um0.25um

0.18um

0.13um

Digital circuits

RF circuits

satTpeak

Lvfπ2

≈5GHz W-LAN

Effect of parasitic capacitance to fT

0 200 400 600 800 10000

2 .1010

4 .1010

6 .1010

5.786 1010.

1.576 109.

fti 0.2 W, 5 10 3., 0,

fti 0.2 W, 5 10 3., 0.1 10 12.,

fti 0.2 W, 5 10 3., 0.5 10 12.,

1 103.10 W

Cp=0.1pF

Cp=0.5pF

Ids=5mAL=0.2um

)(2 pgdgsT

CCCgmf

fT of actual circuit is reduced by a parasitic capacitance.There is an optimum gate width to obtain highest fT.

CingmVi

Cin=Cgs+Cgd

Region(1); Increased by increasing gmRegion(2); Decreased by increasing Cin

fT: MOS vs. Bipolar

⎟⎠⎞

⎜⎝⎛

IdsgmTU

Icgm ≡

Teff nUV 2min = n: 1.4

BipCMOS gmgm41,

kTUT 26≈≡

（Same operating current）

CingmfT π2

BipCMOS CinCin41,

< （Same fT）

Veff/2: 50-100mV(actual ckt.)

Even if fT of MOS is the same as that of Bipolar, fT of MOS is easily lowered by a parasitic capacitance.Because, gm of MOS is ½ to ¼ of that of Bipolar at the same current.

MOS Bipolar

Small parasitic capacitance is a key for RF CMOS design.

VT mismatch

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

)(1 1−mLW

0.4um Nch

0.4um Pch

0.13um Nch In w/o Halo*

0.13um Nch Boron w. Halo*

* Morifuji, et al., IEDM 2000.

VT mismatch degrades accuracy; ADC, OP amp, and Mixer.Larger gate area is needed for small VT mismatch.Scaling and proper channel structure improves mismatch.

LWTV ox

T ∝Δ

Larger gate area

Tox Scaling

Channel engineering

VT mismatch: Fluctuation of doping

基板

- --- - - - - - -

- - - -

- - -ddepl

VAVT 1=Adepl

Adeplox

NLWdAt

≈′==Δ

mVVnmtmWL

205,25.0

=ΔT.Mizuno, J.Okamura and A.Toriumi, ”Experimental study o f threshold voltage

fluctuation due to statistical variation of channel dopant number in MOSFETs,”IEEE Trans. On Electron Devices, ED-41, 2216 (1994)

=== μ

Courtesy of Prof. Taniguchi, Osaka Univ.

1/f noise

1E+02 1E+03 1E+04 1E+05 1E+06 1E+07

L=0.4um

L=1.0um

Bipolar

nMOSVdd=3VId=1mA

1E+02 1E+03 1E+04 1E+05 1E+06 1E+07

W/L=800/0.4Vdd=3VId=1mA

Bipolar

2 /Hz)

Frequency (Hz) Frequency (Hz)

2 /Hz)

Nch/Pch 0.4um Nch 0.4um/1.0um

1/f noise of MOS is larger than that of bipolar.

22 , oxvfvf

nf TSff

LWSV ∝

For the lower 1/f noise, the larger gate area is needed.

Noise figure: General

sss jXRZ +=

( )nis

ngsngrsn GRRR

IZVVF ++≈++=

++= 11

ningnvng kTGIkTRV 44 2,

NoiselessCircuit

ZsVn,rs Vng

The lower Rnv and Gni realizes the better for a lower noise figure.

ngsopt

IVR == ninvGRF 21min +≈

Noise figure: MOS transistor

nv GRRRF ++≈1

≈231NL

WRR totsrg =gsgnv RRR +=

5⎟⎠⎞

⎜⎝⎛≈

gmGωω

5511 ⎟

⎠⎞

⎜⎝⎛++≈

gmRsgmRs

11ωω

CgmR =⎟

⎠⎞

⎜⎝⎛≈

min 21+≈

Cgs rgs

( ) sTsgsg

gsin LLCgm

ssCLLsZ ω≈⎟

⎠⎞

⎜⎝⎛+++≈

( )gsgs LLC +=

Impedance matching

Low noise amplifier design

Narrowband LNA uses inductor degeneration for impedance matching.

Low NF design

rrgmZZ

rrF ggs

ggs ++≈⎟

⎠⎞

⎜⎝⎛+

ωωγ

Divide the gate

LWRr tot

WRr totsrg =

Rsr: Sheet resistanceN：The # of division

Low noise figure

1) Lower the gate resistance

Dived the gate or lower the gate sheet resistance

2) Reduce substrate loss

Use shield technique to the input bonding PAD.

Use high resistive substrate, if possible.

3) Increase drain current ( )ds

≈≈4) Increase Z0, if possible.

Reduce parasitic capacitance

Ids and Veff optimization

WIV ds

eff ∝

3 ZIVgmZF

IIPDR dseffLNA

LNA ≈∝−

3rd distortion

Adjust the Ids and Veff for optimization of gain, noise and distortion.

Lower Ids

Higher Ids

effVIIP ∝3

Dynamic range of LNA is proportional to Ids.

NF progress in MOS LNA

Gate length (μm)

0.35 0.250.5

)NF of MOS LNA is reaching 1dB.

( )( )tAV LOsso ωωπ

±= cos2Vs

Vo( )tAV sss ωcos=

( )tAV LOLOLO ωcos=

If VLO>>4Veff (Full swing)

FIF FIF

Fimage

RF spectrum IF spectrum

Mixer converts frequency, but image signal is converted to the same frequency.

Image-reject mixers

( )tLOωcos

LPF °− 45

Vin (t) Vout(t)

( )tLOωsin

( ) ( )tAtAtV imimdesdesin ωω coscos)( +=

( ) ( )tIAAtAAtV IFRcimIFcdesout ωω coscos)( +=

Ac: Conversion gain, IR: Image rejection

IR=0 if I/Q phase difference is 90° and Channel conversion gains are equal.

The quadrature mixing realizes image-suppression.Gain and phase matching is needed.

Gain mismatch and phase error

φγγφγγ

cos21cos21

++−+

=desired

φ: Gain ratio

:Phase error

A. Rofougaran, et al., IEEE J.S.C. Vol.33, No.4, April 1998. PP. 515-534.

Passive FET mixer

Low powerHigh linearityNo 1/F noise

No conversion gainNo isolation, Bi-directional

Passive FET mixer

MOS can realize a passive mixer easily.

Ultimately low power, but take care of isolation.

Active mixers

Single balanced mixer

Double balanced mixer

M1 M1’

M2 M3 M2’ M3’

Very small direct feed through and even order distortion

Active mixer design

ZZorZgmG

ππ22

gmkTRRgmAIRkTRv

≅≈

⎟⎠⎞

⎜⎝⎛

≈⎟⎠⎞

⎜⎝⎛ ++=

γπγπ

γγπγ

Mixer gain

Thermal noise

A larger dynamic range needs larger current

RL: Resistive component in ZL

when Zs is used

Ts TLO

1/F noise

1) Switch transistor (M2, M3)

CgsWLswn

∝≈

2) Load transistors Directly produces

Phase modulation

Shorter switching time or larger Ts/TLo ratio

The larger Ids is needed for high dynamic rangeand shorter switching time for low 1/f noise.

Oscillator

oscIrV 4

rVI odd

ωππ==

CQLQro0

L CQr0-1/gm

1) Amplitude condition

Oscillationamplitude

2) Oscillation condition

Headroomlimit

rgm effo

3,2,3,2 ,2 ω

There is an optimum Ids for low phase noise.

Phase noise of oscillator

( )ωjZ

[ ])(cos)( 0 ttAtv φω +=

ωφφω jdtd

m ==mω : Offset angular frequency

( )mmm SS ωωω φω2)( = )( mS ωω

( )mS ωφ

:Noise spectrum densityon offset angular frequency

:Noise spectrum densityon phase

ωωθ

φ dQd L

θΔ Phase error between in and out

S ωωω θω Δ⎟⎟⎠

⎞⎜⎜⎝

( ) ( )mmL

ωωω

ωωω θθφ ΔΔ ⎟⎟

⎞⎜⎜⎝

⎛=⎟⎟

⎞⎜⎜⎝

( )mS ωθΔ

:Noise spectrum densityon phase error

Phase-frequency relation and resonator characteristics determine phase noise.

Phase noise of oscillator

24 ⎟⎟

⎞⎜⎜⎝

⎛=⋅

Δ monn

ωωωm

mLjZ ≈+

( )ωjZ

-1/gm -1/gmr0

mQrZωωωω

0 ≈+

{ }⎥⎥⎦

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛⋅=

22log10

ωωω

0ωω <<m

Noise spectrum density

Phase noise

(Filter action)

Frequency characteristics of Phase noise in oscillator

LQBw =

Q ωω

⎟⎟⎠

⎞⎜⎜⎝

⎛( )mS ωφ

2 mL PsFkT

Q ωω

⎟⎟⎠

⎞⎜⎜⎝

PsFkT2

-9dB/oct(Slope =-3)

-6dB/oct(Slope=-2)

1/f noise Thermal

Thermal

ωθ =Δ

( )PsFkTS m

2=Δ ωθ

( )mmL

S ωωωω θφ Δ⎟⎟

⎞⎜⎜⎝

1/f noise and thermal noise is converted to 1/f3 and1/f2, respectively.

Up and down converted noise

)/( HzVVnoise

ωo 2ωo 3ωo

P (dBm)

Noiseshaping

Down-conv.Up-conv.

Noises around N*fo are up and down converted to fo.

FoM and minimum phase noise

IVfLffFoM

ddmm )(1

⎟⎟⎠

⎞⎜⎜⎝

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅⎟⎟

⎞⎜⎜⎝

⎛⋅⋅=⋅⎟⎟

⎞⎜⎜⎝

⎛⋅⋅=

roVFkT

19882 mo

IrF ⋅++= γπγ

Fm: Offset frequencyL(fm): Phase noise at offset freq.

F: Noise factor

ωπωππ

γπγπ

FoM is basically proportional to Q2.

at Iopt

Oscillator design

Bias currentIopt

Phase noise Oscillationamplitude

Larger VddLarge Veff1, but take care of Vo reductionLarge L1, W1 to reduce 1/f noiseEnough W/L for M2, M3Higher QLarger QLind for Lower Iopt

)( ⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎠⎞

⎜⎝⎛ +⋅⋅⋅=

VkTfL ωγ

1,2min

)( ⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎠⎞

⎜⎝⎛ +⋅⋅⋅=

effddoptm

VVQIkTfL γ

ωπωππ

Careful optimization reduces the oscillator phase noise.

Vo VoL

LxCsHi-Z at 2fo

(a) (b)(c)

CMOS oscillator circuits

Basic Low power (gm is higher) Low noise by filtering

E. Hegazi, ISSCC 2001

Filtering of 2fo component in OSC.

Noise filtering of 2fo component reduces the OSC phase noise to -10dB.

E. Hegazi, ISSCC 2001

-150.0

-140.0

-130.0

-120.0

-110.0

-100.0

1994 1995 1996 1997 1998 1999 2000 2001 2002

◆CMOS

■Si-bipolar/BiCMOS

▲SiGe-BiCMOS

Oscillator phase noise progress

Phase noise in CMOS oscillator becomes lower than that of bipolar.

Acknowledgment and references

• AcknowledgmentI would like to thank Prof. Asad Abidi in UCLA for his advices.

• References– Asad A. Abidi, “Power-Conscious design of Wireless circuits and

systems,” pp.665-695, “Trade-offs in Analog Circuit Design,” KluwerAcademic Publishers, 2002. (Edited by Chris Toumanzou, George Moschytz, and Barrie Gilbert)

– Thomas. H. Lee, “The design of CMOS RF ICs,” Cambridge University Press, Jan. 1998.

– Bezad, Razavi, “RF micro-electronics,” Prentice Hall, Nov. 1999.– Domine Leenaerts, Johan van der Tang, and Ciero Vaucher, “Circuit

Design for RF Transceivers,” Kluwer Academic Publishers, 2001.– Charles Chien, “Digital Radio Systems on A chip,” Kluwer Academic

Publishers, 2001.– E. Hegazi, et. Al., ”A Filtering Technique to Lower Oscillator Phase

Noise,” ISSCC 2001, 23.4, Feb. 2001.

RF circuit design: Basics

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