RICE UNIVERSITY ‘Stream’-based wireless computing Sridhar Rajagopal Research group meeting...

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RICE UNIVERSITY

‘Stream’-based wireless computing

Sridhar Rajagopal

Research group meeting December 17, 2002

The figures used in the slides are borrowed from papers at VT and Stanford.

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Motivation

‘Stream’-based computing what does it mean?

Not a well-defined term ‘computation’ that uses flow of self-guided

info. ‘sequence of data’

Related to flow of data through architecture

Application to implementing wireless algorithms

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Outline

Stallion reconfigurable computing at Virginia Tech ‘stream’-based computing #1 Custom Configurable Machines (CCM)

Imagine media processing at Stanford ‘stream’-based computing #2 programmable architectures

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Stallion at VT

Wormhole Run-Time Reconfiguration (RTR) coarse-grained structure reconfiguration using ‘streams’

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‘Stream’ packets

A stream packet

Stream flow through architecture

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Functional description of PE

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Stream module description

4 States:IDLE – reconf. in progressBUSY – doing workPROGRAM – load reconf. dataPASS – meant for next module

Need to output packet/cycleVALID – maintain sync. - set INVALID instead of wait states - strip information off stack

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Processing layer

Static section configures the reconf. section buffers data during reconf. & sends ‘IDLE’

packets Reconf. Section

processing of the data done here

Higher layers convert algorithm to data and configuration patterns

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Cart before the horse Colt before the Stallion

Colt architecture (also at VT)

IFU Mesh – Mesh of interconnected func. units

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Stallion chip

16-bit data4-control

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IFU mesh in Stallion

Dash-line –-skip buses

Can send operandsover 1/more IFUs

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IFU details

Only left input can do barrel shifting

ALU based on LUT

Control register – stores control information for reconfiguration

Optional Delay Register - provides latency to synchronize path lengths of different pipeline streams

Cond. unit

Output control unit

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Radio testbed at VT

Stallion

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Worm-hole routing

stream = worm architecture = holes

multiple, independent streams can wind their way through the chip simultaneously

parts of system can be processing, parts could be reconfiguring

GOAL: Layered Software Radio Architecture

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‘Stream’ processing at Stanford

Speeding up media applications

Need lots of computations per memory reference

Lots of data and sub-word parallelism

Current GPP architectures do not have enough ALUs

‘Stream’ processors to the rescue

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Special-purpose processors

Fed by dedicated wires/memoriesLots (100s) of ALUs

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Care and feeding of ALUs

DataBandwidth

Instruction Bandwidth

Instr.Cache

IP‘Feeding’ Structure Dwarfs ALU

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Architecture implications

Tremendous opportunities media problems have lots of parallelism and locality VLSI technology enables 100s of ALUs/chip (1000s

soon)• (in 0.18um 0.1mm2 per integer adder, 0.5mm2 per FP adder)

Challenging problems locality - global structures won’t work explicit parallelism - ILP won’t keep 100 ALUs busy memory - streaming applications don’t cache well

Its time to try some new approaches

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Register file organization

Register files functions: short term storage for intermediate results communication between multiple function

Global register files don’t scale with #ALUs need more registers to hold more results (grows with #ALUs ) need more ports to connect all of the units (grows with #ALUs 2 )

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Register files dwarf ALUs

N A rithm etic Units

32 ALUs

Size of RFto support32 ALUs

Size of1 ALU

Size of RFto support

1 ALU1 cm

4 ALUs 16 ALUs

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Distributed register files

Distributed register files means: not all functional units can access all data each functional unit input/output no longer

has a dedicated route from/to all register files

A D D 0 L/S A D D 1

can write toeither or

both busescan read

from eitherbus

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Stream processing

Kernel StreamInput Data

Output Data

Image 1 convolve convolve

Image 0 convolve convolve

Depth Map

Little data reuse (pixels never revisited) Highly data parallel (output pixels not dependent on other output

pixels) Compute intensive (60 operations per memory reference)

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Stream programming

Streams Communication

void main() { Stream<int> a(256); Stream<int> b(256); Stream<int> c(256); Stream<int> d(1024); ... example1(a, b, c); example2(c, d); ... }

Kernels Computation

KERNEL example1(istream<int> a, istream<int> b, ostream<int> c) { loop_stream(a) { int ai, bi, ci; a >> ai; b >> bi; ci = ai * 2 + bi * 3; c << ci; } }

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Stream Processor

Instructions are Load, Store, and Operateoperands are streams

Operate performs a compound stream operationread elements from input streamsperform a local computationappend elements to output streamsrepeat until input stream is consumed(e.g., triangle transform)

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Imagine

Stream Register FileNetworkInterface

StreamController

Imagine Stream Processor

HostProcessor

SDRAMSDRAM SDRAMSDRAM

Streaming Memory SystemM

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Arithmetic clusters

From SRF

To SRF

+ + * * /

Cross Point

Local Register File

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Bandwidth hierarchy

VLIW clusters with shared control 41.2 32-bit operations per word of memory bandwidth

2GB/s 32GB/s

ALU Cluster

544GB/s

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Conclusions

‘Streams’ shown to be promising for reconfigurable computing wireless may need reconfigurability

‘Streams’ shown to be promising for media processing wireless may have similar workloads

Important to understand pros and cons of different methodologies for good wireless architectures

Important to have the right tools

RICE UNIVERSITY ‘Stream’-based wireless computing Sridhar Rajagopal Research group meeting...

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