SEQ CPU Implementation

transcript

Outline

• SEQ Implementation

• Suggested Reading 4.3.2, 4.3.4

What we will discuss today?

• The implementation of a sequential CPU (SEQ)– Every Instruction finished in one cycle.– Instruction executes in sequential– No two instruction execute in parallel or overlap

SEQ Hardware Structure

• Stages– Fetch: Read instruction from memory– Decode: Read program registers– Execute: Compute value or address– Memory: Read or write data– Write Back: Write program registers– PC: Update program counter

InstructionInstruction memory PC increment

CCCC ALU

Data memory

Decode

Execute

Memory

Write back

icode:ifun, rA:rB valC

RegisterM

srcA, srcB

dstE,dstM

valA, valB

aluA,aluB

valEaddrs,data

valE,valM

newPCPC

A B Register File

Difference between semantics and implementation

• ISA– Every stage may update some states, these

updates occur sequentially

• SEQ– All the state update operations occur

simultaneously at clock rising

SEQ Hardware

• Blue boxes: predesigned hardware blocks– e.g., memories, ALU

• Gray boxes: control logic– Describe in HCL

• White ovals: labels for signals

• Thick lines: 32-bit word values

• Thin lines: 4-8 bit values

• Dotted lines: 1-bit values

Fetch Logic

• Predefined Blocks– PC: Register containing PC– Instruction memory: Read 6 bytes (PC to PC+5)– Split: Divide instruction byte into icode and ifun– Align: Get fields for rA, rB, and valC

Fetch Logic

• Control Blocks– Instr. Valid: Is this instruction valid?

– Need regids: Does this instruction have a register bytes?

– Need valC: Does this instruction have a constant word?

– icode|ifun: Set to “nop” if imem_error

Some Macros

Name Value

Meaning

INOP 0 Code for nop instruction

IHALT 1 Code for halt instruction

IRRMOVL 2 Code for rrmovl instruction

IIRMOVL 3 Code for irmovl instruction

IRMMOVL 4 Code for rmmovl instruction

IMRMOVL 5 Code for mrmovl instruction

IOPL 6 Code for integer op instructions

IJXX 7 Code for jump instructions

………… …… ……………………………

IPOPL B Code for popl instruction

Some Macros

Name Value

Meaning

RESP 6 Register ID for %esp

RNONE F Indicates no register file access

ALUADD 0 Function for addition operation

SAOK 1 Status code for normal operations

SADR 2 Status code for address exception

SINS 3 Status code for illegal instruction Exception

SHLT 4 Status code for halt

pushl rA A 0 rA 8

jXX Dest 7 fn Dest

popl rA B 0 rA 8

call Dest 8 0 Dest

rrmovl rA, rB 2 0 rA rB

irmovlV, rB 3 0 8 rB V

rmmovl rA, D(rB) 4 0 rA rB D

mrmovl D(rB), rA 5 0 rA rB D

OPl rA, rB 6 fn rA rB

ret 9 0

nop 0 0

halt 1 0

pushl rA A 0 rA 8pushl rA A 0A 0 rA 8rA 8

jXX Dest 7 fn DestjXX Dest 7 fn7 fn Dest

popl rA B 0 rA 8popl rA B 0B 0 rA 8rA 8

call Dest 8 0 Destcall Dest 8 08 0 Dest

rrmovl rA, rB 2 0 rA rBrrmovl rA, rB 2 02 0 rA rBrA rB

irmovlV, rB 3 0 8 rB VirmovlV, rB 3 03 0 8 rB8 rB V

rmmovl rA, D(rB) 4 0 rA rB Drmmovl rA, D(rB) 4 04 0 rA rBrA rB D

mrmovl D(rB), rA 5 0 rA rB Dmrmovl D(rB), rA 5 05 0 rA rBrA rB D

OPl rA, rB 6 fn rA rBOPl rA, rB 6 fn6 fn rA rBrA rB

ret 9 0ret 9 09 0

nop 0 0nop 0 00 0

halt 1 0halt 1 01 0

need_regids

Fetch Control Logic

bool need_regids = icode in { IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IPUSHL, IPOPL };

bool instr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL };

Decode & Write-Back Logic

• Predefined Blocks– Registers File

• Read ports A, B & Write ports E, M• Addresses are register IDs or F (no access)

Decode & Write Back Logic

• Control Logic– srcA: read port address for valA {rA, %esp}– srcB: read port address for valB {rB, %esp}– dstE: write port address for valE {rB, %esp}– dstM: write port address for valM {rA}– Cnd: used to decide whether set valE (cmovXX)

Decode & Write Back Logic

A Source

opl rA, rB

valA R[rA]Decode Read operand A

rmmovl rA, D(rB)

valA R[rA]Decode Read operand A

popl rA

valA R[%esp]Decode Read stack pointer

jXX Dest

Decode No operand

call Dest

valA R[%esp]Decode Read stack pointer

Decode No operand

A Source

int srcA = [icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : rA;icode in { IPOPL, IRET } : RESP;1 : RNONE; # Don't need register

E Destination

R[%esp] valE Update stack pointer

R[rB] valEopl rA, rB

Write-backrmmovl rA, D(rB)

popl rA

jXX Dest

call Dest

Write-back

Write back result

R[%esp] valE Update stack pointer

E Destination

int dstE = [icode in { IRRMOVL, IIRMOVL, IOPL} : rB;icode in { IPUSHL, IPOPL, ICALL, IRET }: RESP;1 : RNONE; # Don't need register

];// not conside cmovXX

Execute Logic

• Predefined Blocks– ALU: implements 4 required functions and

generate condition code values– CC: register with 3 condition code bits– cond: computes condition flag

Execute Logic

• Control Logical– Set CC: Should condition code register be loaded?– ALU A: Input A to ALU {valA, valC, +4, -4}– ALU B: Input B to ALU {valB, 0}– ALU fun: What function should ALU compute?

Execute Logic

ALU A Input

valE valB + –4 Decrement stack pointer

No operation

valE valB + 4 Increment stack pointer

valE valB + valC Compute effective address

valE valB OP valA Perform ALU operationOPl rA, rB

Executermmovl rA, D(rB)

popl rA

jXX Dest

call Dest

Execute

Execute valE valB + 4 Increment stack pointer

ALU A Input

int aluA = [icode in { IRRMOVL, IOPL } : valA;icode in { IIRMOVL, IRMMOVL,IMRMOVL}

: valC;icode in { ICALL, IPUSHL } : -4;icode in { IRET, IPOPL } : 4;# Other instructions don't need ALU

ALU Operation

valE valB + –4 Decrement stack pointer

No operation

valE valB + 4 Increment stack pointer

valE valB + valC Compute effective address

valE valB OP valA Perform ALU operationopl rA, rB

Execute

rmmovl rA, D(rB)

popl rA

jXX Dest

call Dest

Execute

Execute valE valB + 4 Increment stack pointer

ALU Operation / Condition Set

int alufun = [icode == IOPL : ifun;1 : ALUADD;

Bool set_cc = icode in { IOPL };

Memory Logic

• Predefined Blocks– Memory: Reads or writes memory word

Memory Logic

• Control Logical– Mem. read: should word be read?– Mem. write: should word be written?– Mem. addr.: Select address {valA, valE}– Mem. data.: Select data {valA, valP}

Memory Logic

Memory Address

opl rA, rB

Memory

rmmovl rA, D(rB)

popl rA

jXX Dest

call Dest

No operation

M4[valE] valAMemory Write value to memory

valM M4[valA]Memory Read from stack

M4[valE] valP Memory Write return value on stack

valM M4[valA] Memory Read return address

Memory No operation

Memory Address

int mem_addr = [icode in { IRMMOVL, IPUSHL,

ICALL, IMRMOVL } : valE;icode in { IPOPL, IRET } : valA;# Other instructions don't need address

Memory Read

opl rA, rB

Memory

rmmovl rA, D(rB)

popl rA

jXX Dest

call Dest

No operation

M4[valE] valAMemory Write value to memory

valM M4[valA]Memory Read from stack

M4[valE] valP Memory Write return value on stack

valM M4[valA] Memory Read return address

Memory No operation

Memory Read/Write

bool mem_read = icode in { IMRMOVL, IPOPL, IRET };

bool mem_write = icode in { IRMMOVL, IPUSHL, ICALL };

PC Update Logic

• New PC– Select next value of PC

PC Update

OPl rA, rB

rmmovl rA, D(rB)

popl rA

jXX Dest

call Dest

PC valPPC update Update PC

PC Bch ? valC : valPPC update Update PC

PC valCPC update Set PC to destination

PC valMPC update Set PC to return address

PC Update

int new_pc = [

icode == ICALL : valC;

icode == IJXX && Cnd : valC;

icode == IRET : valM;

1 : valP;

SEQ Summary

• Implementation– Express every instruction as series of simple

steps– Follow same general flow for each instruction

type– Assemble registers, memories, predesigned

combinational blocks– Connect with control logic

SEQ Summary

• Limitations– Too slow to be practical– In one cycle, must propagate through

instruction memory, register file, ALU, and data memory

– Would need to run clock very slowly– Hardware units only active for fraction of clock

SEQ CPU Implementation

Documents