Signal Processing Using Digital Technology

Jeremy BarstenJeremy Stockwell

December 10, 2002

Advisors:Dr. Thomas Stewart

Dr. Vinod Prasad

Digital Signal Processor Project Description Preliminary Work

Research Design

Standards and Patents Goals Schedule

Project Description All purpose digital signal processor

using FPGA/VHDL and ASIC/VLSI technology.

Useable for a variety of applications: Audio and Video Cellular Technology

Adapted depending on the application.

Project Description High-level Block Diagram:

Input ProcessedSignal Signal

DIGITALSIGNAL

PROCESSOR

Filter Design Manipulating a digital input

utilizing multipliers and adders. Direct Form II realization of an IIR

Filter: X(n) w(n) b0 y(n)

-a1 b1

-a2 b2 w(n-1)

w(n-2)

Z-1

Z-1

Signal Converters Each signal will be analog in

nature. Requires an analog-to-digital

converter at the input stage and a digital-to-analog converter at the output stage.

Type of converter will be determined later.

Adder and Multiplier Any basic signal processor consists

of different stages of addition and multiplication.

A n-bit by n-bit multiplication will take place and result in a 2*n-bit value.

This answer will be added to previous values stored in a data register (discussed later).

Adder and Multiplier Cellular Multiplication:

a3 a2 a1 a0

b0

b1

b2

b3

p7 p6 p5 p4 p3 p2 p1 p0

Adder and Multiplier For 2’s compliment addition and

multiplication:

Cellular Array

2’s Complement Block

2’s

B

L

O

C

K

Adder and Multiplier

x(n)-a1*w(n-1)

-a1 -a2

w(n-1) w(n-2)

x(n)

x(n)-a1*w(n-1)

Shows the consecutive steps in the addition, multiplication, and data management.

16-Bit Multiplier

32-bit Adder/Subtractor

Memory Management

16-Bit Multiplier

Memory Management

32-bit Adder/Subtractor

Data Management Need to store old calculated values

for later use. Need a “shift-and-store” type of

data management. Will deliver the correct data at the

appropriate time.

Data Management The possibility of overflow exists in

the addition and multiplication stage. For this reason, a truncation circuit is

needed to control and adjust the value of the adder/multiplier circuit.

Will also use truncation before sending out the final signal.

Preliminary Work Investigation of Xilinx compiler. Ripple carry adder v. Carry

look ahead adder. Parallel multiplier v. Serial

multiplier.

* 16-bit ripple carry adder will have 34 gate delays

Ripple Carry AdderRipple Carry Adder

CLA Adder

* 16-bit CLA adder will have 10 gate delays

Xilinx Implementation Implemented both adders using VHDL. Created simple adder in VHDL (a+b=c). Compared results to see what type of adder

was created by the compiler. Results:

CLA AdderRipple Adder

Simple Adder

Delay 11.05 ns 22.43 ns 11.05ns

Checked results using FPGA board.

Multiplier Advantages and disadvantages

of using a parallel multiplier v. a serial multiplier.

Investigate the feasibility of using a Parallel Multiplier.

Speed v. Area

Signed Serial Multiplier For a signed serial multiplier, it is

necessary to sign extend. For Example (-3 x 5):

1101(-3) x 0101(+5)

11111101 0000000 111101

+ 00000 11110001(-15)

Signed Serial Multiplier

Sign ExtensionSign Extension

Shift RegisterShift RegisterShift RegisterShift Register

Adder/SubtractorAdder/Subtractor

RegisterRegister

A B

Product

Area v. Speed Implemented Serial adder and

simple AxB adder in VHDL.

Area Delay Area Delay Area Delay

Serial Multiplier 7.14% 96.88ns 13.52% 210.8ns 24.49% 503.68ns

Parallel Multiplier 10.71% 27.41ns 28% 38.76ns 107.40% 51.06ns

Area v. Delay (serial)Area v. Delay

7.00%

9.00%

11.00%

13.00%

15.00%

17.00%

19.00%

21.00%

23.00%

25.00%

27.00%

96 146 196 246 296 346 396 446 496 546

Delay(ns)

Are

a

Area v. Delay (parallel)Area v. Delay

10.00%

30.00%

50.00%

70.00%

90.00%

110.00%

130.00%

27 32 37 42 47 52 57

Delay(ns)

Are

a

Other Multiplier Options It is possible to use a combination

of parallel and serial multipliers. For example it is possible to use

two 8-bit parallel multipliers in series which will double the delay but will save space.

Standards and Patents Searched the Internet for

standards and patents on digital signal processors.

Many of the standards were application specific.

Could not really find specific standards on digital signal processors.

Hardware and Software Programs

Xilinx Foundation Software Leonardo Spectrum L-Edit Pro v8.2 PSpice Circuit Simulation Xilinx XC4005ePC84 FPGA Board A/D and D/A converters

Project Goals Determine best trade-off between size

and speed for the adder/multiplier circuit.

VLSI implementation of a 4-bit adder and multiplier.

Determine the number of bits used in our processor to ensure stability.

Complete data management and truncation block of the processor.

Decide on specific application.

Project Schedule January/February:

Complete adder/multiplier in VHDL and implement on the FPGA board.

Complete VLSI design of adder/multiplier circuit. March:

Determine specific application and design the appropriate filter. April:

Complete data management and truncation block. Implement entire design on FPGA board and troubleshoot any

errors that arise. May:

Prepare final presentation and possibly present at Student Expo.

Signal Processing Using Digital Technology

Jeremy BarstenJeremy Stockwell

December 10, 2002

Advisors:Dr. Thomas Stewart

Dr. Vinod Prasad