Signal- und Power-Integrität (SPI) von Digitalen Systemen von Digitalen Systemen... · Signal- und...

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Signal- und Power-Integrität (SPI) von Digitalen Systemen

Institut für Theoretische Elektrotechnik

A. Vogt, H.-D. Brüns, C. Schuster

ERNI Kongress 2012, Uhingen, 11.11.12

Overview

1. Introduction

2. Power Integrity

3. Signal Integrity

4. Electromagnetic Compatibility

5. Outlook

http://www.tet.tu-harburg.de

Overview

1. Introduction

2. Power Integrity

3. Signal Integrity

5. Outlook

Power Plane Ground Plane

Driver Via

Receiver

A Possible Electrical Integrity Issue

Signal Integrity Issues: Attenuation, Reflection, Dispersion

Power Integrity Issues: Switching Noise, Crosstalk

EMC Issues: Near Field Coupling, Radiation Coupling

Overview

1. Introduction

2. Power Integrity

3. Signal Integrity

5. Outlook

Problems of Power Delivery

Ideal:

• Both ICs see the same voltage U0 between their power

and ground terminals

• Independent of time and switching

IC #1 IC #2

Real world:

• Finite source impedance ZPDN

• First approximation: series RL

IC #1 IC #2

With only one IC active there is a voltage drop across ZPDN!

R uIC L

iGate1, iGate2, …

uIC = U0 - Du

The goal of power integrity is to ensure an acceptable quality

of power delivery within the system, i.e. the design of an

adequate power delivery network (PDN).

This includes:

low "resistance"

low "inductance"

hierarchical decoupling

sufficient decoupling

Power Integrity

Impedance

Frequency

Target

System

Based on the simple example from before:

The Concept of Decoupling

) largefor (

(R = 0.7

L = 40 nH)

U0 ~ ZIC ( f )

… we ask what a so called "decoupling" or "bypass"

capacitor might do:

) largefor (1

1 2PDN

U0 ~ ZIC ( f ) C

R = 0.7 mW

L = 40 nH

C = 1 mF

W m57)( 0PDN Z

R = 0.7 mW

L = 40 nH

C = 1 mF

R = 10 mW

L = 40 nH

C = 1 mF

Heuristic explanation:

Frequency domain:

Beyond resonance frequency: the IC sees only the

impedance of the capacitor.

Time domain:

The capacitor is like a "small battery".

U0 ~ ZIC ( f ) C

Ideal world: … and real world:

R is also is called the EQUIVALENT SERIES RESISTANCE

(ESR) and L the EQUIVALENT SERIES INDUCTANCE (ESL).

C R L C

Power/Ground Planes

Example:

11 inch

10 mil Dielectric

Filling (er = 4)

(1 inch = 2.54 cm,

1 mil = 0.001 inch)

nF11r0pp d

Power Ground

Inductive Capacitive

Power/Ground Planes

Input (PDN) impedance

from before (VRM + 10

decaps)

Input (PDN)

impedance

including P/G

capacitance

Power/Ground Planes

Operation usually above the first resonance frequency…

Distributed behavior!

(VRM removed –

just the planes

present)

Distributed Behavior!

Discretization for Contour Integral Method (CIM)

Full-wave discretization CIM discretization

Further Information

IEEE Transactions on EMC 2010

Study Case

Relative dielectric permittivity εr 4.2

Relative permeability μr 1.0

Loss tangent tanδ 0.02

Plane conductivity κ (S/m) 5.8e+7

Plane thickness (mil) 1.2

Via diameter (mil) 10

Via pad diameter (mil) 20

Via keepout/antipad (mil) 36

Board dimension in inch

Observation ports

12,0 15,0

8.02,9

8.02,2

X. Duan, R. Rimolo-Donadio, H-D. Brüns, B. Archambeault, C. Schuster, “Special Session on

Power Integrity Techniques: Contour Integral Method for Rapid Computation of

Power/Ground Plane Impedance” , DesignCon 2010, Santa Clara

Comparison to Full-Wave Simulation

The dielectric thickness is 10 mil.

0.1 1 10 100 100010

Frequency [MHz]

Z11 CIM

Z11 full-wave

Z12 CIM

Z12 full-wave

Comparison to Measurement

0.1 1 10 100 1000-60

Frequency [MHz]

no decaps measured

no decaps CIM

20 decaps measured

20 decaps CIM

0.1 1 10 100 1000

Frequency [MHz]T

no decaps measured

no decaps CIM

20 decaps measured

20 decaps CIM

Electric Field Distribution @ 190MHz

Port 1 excited by 1 Watt power and port 2 terminated with 50 Ω

Full-wave CIM

Overview

1. Introduction

2. Power Integrity

3. Signal Integrity

5. Outlook

Signal Integrity

The goal of signal integrity is to insure an acceptable quality of

signals within the system.

This includes:

high transmission

low reflection

low crosstalk

low losses

(low power consumption)

Signal to

Noise Ratio

Frequency

Target

System

Effects on Signal Integrity

The ideal interconnect will simply delay the signal:

Any real interconnect will additionally change timing and

amplitude:

Effects on Signal Integrity

The deviations in timing and amplitude are in general called:

Timing jitter or simply: JITTER

Amplitude noise or simply: NOISE

More precise definitions of jitter and noise use the EYE

DIAGRAM. For such a diagram the received bit stream is

partioned in bit periods:

and the individual

partitions overlayed

on top of each other:

Eye Diagrams

Opening

Besides S-parameters and

step response eye diagrams

are another useful method

to analyze transmission

characteristics:

Eye Diagrams

Further Information

IEEE SPI 2012

Common Interconnect Problems

Insufficient

Shielding

Discontinuities

IC (Transmitter)

IC (Receiver)

Impedance

Mismatch

Insufficient Termination

We have seen that a realistic interconnect for digital signals

can suffer from many problems:

Insufficient Line Pitch and Width

SI Problems Inside the Motherboard

• Layer-layer inter-

connects: VIAs

• Striplines

Both „radiate“

Cross-talk

Parallel plane modes are excited whenever a current is flowing on

a via that crosses the cavity (either signal or power/ground via):

via currents

parallel plane modes

The Physics of Vias

Picture © TET, TUHH

Picture © IBM

Via Cross Section

Plane Cp

(Parallel Plate

Impedance)

Current

The Model for Vias

Picture © IBM

Decoupling capacitor model

Cavity

representation

Cavities joined by

segmentation

techniques

R. Rimolo-Donadio et al., “Physics-based via and trace models for efficient link simulation on multilayer structures

up to 40 GHz", IEEE Trans. Microw. Theory and Techn., vol. 57, no. 8, p.p. 2072-2083, August 2009.

Zpp Ztl

Linterc.

Zpp Ztl

Linterc.

Cavity

representation

Stacking the Deck

S-Parameter

Matrix

Port 1 Port n

Further Information

IEEE EMC Zürich 2008

MLSS – Multi-Layer Substrate Simulator

• Simulation tool for signal and power integrity issues.

6 Vias, 4 traces case

Centered striplines at

two levels, and thru vias

in a 6 cavity stackup

Full-wave model

Frequency [GHz]

FEM simulation

FIT simulation Full-wave model M

Frequency [GHz]

FEM simulation

FIT simulation

Comparison with Full-Wave Results

• 119 vias (76 signal,

43 ground)

• 14 differential

striplines (2D)

• 6 cavities

• Terminations

Comp. time: < 3 min

Assumption

of infinite

plates

Comparison with Full-Wave Results

43 Pictures © TET, TUHH

Picture © IBM

Comparison with Measurements

Models capture the salient features of the

hardware response despite the drastic

model simplification

|S13| [dB] - FEXT |S12| [dB] - IL

Link 10 -

S3 Stripline

Link 17 - S5

Stripline

Link 10 -

S3 Stripline

Link 17 - S5

Stripline

Measurement Link 10

Measurement Link 17

Model Link 10

Model Link 17

Overview

1. Introduction

2. Power Integrity

3. Signal Integrity

5. Outlook

Electromagnetic Compatibility

The goal of electromagnetic compatibility is to insure

acceptable levels of electromagnetic interference (EMI) of the

system with the outside.

This includes:

EMI source control

return current control

proper shielding

proper filtering

proper SI and PI

Frequency

Target

System

Sources of EMC Problems Digital Systems

Backplane

• Switching Noise, ICs

• Cavity resonances

• Interconnects

• Differential to Common-

mode conversion

Length mismatch Asymmetrical

ground pins

Via fields

Crosstalk

Impedance

discontinuity

There is no Truly Differential Signal

Further Information

IEEE EMC Symposium 2009

Development of the MoM Code CONCEPT-II

Full-wave solver suite based on the Method of Moments

Windows

Radiation due to Cavity Resonances

• PCB: height << other dimensions

→ TM-modes

→ CIM

• Radiated fields expressed with magnetic surface current

• CIM: no electric currents (PMC)

→ no radiation

• MoM: magnetic currents as

excitation

→ electric fields

Radiation due to Cavity Resonances

• External ports with both MoM and CIM

Coupling to the Outside World

Multi-Step Approach

• Interaction of a PCB with PEC scatterers

• Excited by a dipole generator in the center (1mW) of the

power plane pair

• PCB calculated with CIM, 3D interaction calculated with

Excitation: 1mV

0.3 mm d

Region for field plots

The virtual plane

for the MoM step

Multi-Step Approach – Electric Field

Multi-Step Approach – Comparison to Full-Wave MoM

• Good correlation (outside the PCB)

• Significant speed-up:

– Full-wave MoM: 80 s/freq

– CIM/MoM: 15 s/freq

Multi-Step Approach – Backscattering

• Induced noise voltage insignificant (less than 1%)

0 1 2 3 4 5 6 7 8 9 100

Frequency [GHz]

Induced n

put port

d = 2cm

d = 1cm

d = 0.5cm

d = 0.2cm

Excitation: 1mV

0.3 mm

d 5 cm

Further Information

IEEE EMC Europe 2012

Problem: Huge systems

• Reduce number of

unknowns

• Approximate Models

Roadmap

Overview

1. Introduction

2. Power Integrity

3. Signal Integrity

5. Outlook

Goals of SI, PI, and EMC

The basic goals of EMC, SI, and PI for an electrical system

are complementary to each other.

PI: insure acceptable quality

of power delivery within

SI: insure acceptable quality of

signals within

EMC: insure acceptable level

of interference with the outside

Frequency

Target

System

Frequency

Target System

Impedance

Target

System

Electrical Integrity

Thank you for your attention!

Alexander Vogt Institut für Theoretische Elektrotechnik

Technische Universität Hamburg-Harburg

Harburger Schloßstr. 20

21079 Hamburg, Germany

alexander.vogt@tuhh.de

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