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Single-stage G-band HBT Amplifier with 6.3 dB Gain at 175 GHz
M. Urteaga, D. Scott, T. Mathew, S. Krishnan, Y. Wei, M. Rodwell.
Department of Electrical and Computer Engineering,
University of California, Santa Barbara
urteaga@ece.ucsb.edu 1-805-893-8044 GaAsIC 2001 Oct. 2001, Baltimore, MD
OutlineGaAs IC 2001 UCSB
• Introduction
• Ultra-low parasitic InP HBT technology
• Circuit design
• Results
• Conclusion
Applications: Wideband communication systems Atmospheric sensing Automotive radar
Transistor-based ICs realized through submicron device scaling
State-of-the-art InP-based HEMT Amplifiers with submicron gate lengths
3-stage amplifier with 30 dB gain at 140 GHz.
Pobanz et. al., IEEE JSSC, Vol. 34, No. 9, Sept. 1999. 3-stage amplifier with 12-15 dB gain from 160-190 GHz
Lai et. al., 2000 IEDM, San Francisco, CA. 6-stage amplifier with 20 6 dB from 150-215 GHz.
Weinreb et. al., IEEE MGWL, Vol. 9, No. 7, Sept. 1999.
HBT is a vertical-transport device (vs. lateral-transport) Presents Challenges to Scaling
G-band Electronics (140-220 GHz)
Transferred-Substrate HBTs
• Substrate transfer allows simultaneous scaling of emitter and collector widths
• Maximum frequency of oscillation
• Submicron scaling of emitter and collector widths has resulted in record values of measured transistor power gains (U=20 dB at 110 GHz)
• Promising technology for ultra-high frequency tuned circuit applications
This Work Single-stage tuned amplifier with 6.3 dB gain at 175 GHz Gain-per-stage amongst highest reported in this band
cbbbCRff 8/max
Mesa HBT
Transferred-substrate HBT
InGaAs 1E19 Si 1000 Å
Grade 1E19 Si 200 Å
InAlAs 1E19 Si 700 Å
InAlAs 8E17 Si 500 Å
Grade 8E17 Si 233 Å
Grade 2E18 Be 67 Å
InGaAs 4E19 Be 400 Å
InGaAs 1E16 Si 400 Å
InGaAs 1E18 Si 50 Å
InGaAs 1E16 Si 2550 Å
InAlAs UID 2500 Å
S.I. InP Bias conditions for the band diagram
Vbe = 0.7 V, Vce = 0.9 V
InAlAs/InGaAs HBT Material System
Layer Structure AlInAs/GaInAs graded base HBT
Band diagram under normal operating voltagesVce = 0.9 V, Vbe= 0.7 V
• 500 Å 5E19 graded base (Eg = kT), 3000 Å collector
-2
-1.5
-1
-0.5
0
0.5
0 1000 2000 3000 4000 5000 6000
Distance, Å
Gradedbase
Collector depletion regionEmitter
Schottkycollector
Band Diagram
2kT base bandgap grading
Transferred-Substrate Process Flow
• Emitter metal• Emitter etch• Self-aligned base• Mesa isolation
• Polyimide planarization• Interconnect metal• Silicon nitride insulation• Benzocyclobutene, etch vias• Electroplate gold• Bond to carrier wafer with solder
• Remove InP substrate • Collector metal• Collector recess etch
Ultra-high fmax Submicron HBTs
• Electron beam lithography used to define submicron emitter and collector stripes
• Minimum feature sizes 0.2 m emitter widths 0.3 m collector widths
• Amplifier device dimensions: Emitter area: 0.4 x 6 m2
Collector area: 0.7 x 6.4 m2
• Aggressive scaling of transistor dimensions predicts progressive improvement of fmax
As we scale HBT to <0.4 um, fmax keeps increasing, devicemeasurements become very difficult
0.3 m Emitter before polyimide planarization
Submicron Collector Stripes(typical: 0.7 um collector)
Device Measurements
RF Measurements:• Unilateral power gain shows peaking in DC-45 GHz band
• 75-110 GHz measurements corrupted by excessive probe-to-probe coupling
• Recent device measurements have shown negative unilateral power gain in W- and G- bands (2001 DRC, Notre Dame)
• Second-order device physics may be important in ultra-low parasitic devices
Implications
Devices have extremely high power gains in 140-220 GHz bands, but fmax cannot be determined from 20 dB/decade extrapolation
• Bias Conditions: VCE = 1.2 V, IC = 4.8 mA
• Device dimensions: Emitter area: 0.4 x 6 m2
Collector area: 0.7 x 6.4 m2
• f = 160 GHz
• DC properties: = 20, BVCEO = 1.5 V
U
MSG/MAG
MSG/MAG
h21
h21
RF Gains
140 150 160 170 180 190 200 210 220
Frequency, GHz
-5.0
-2.5
0.0
2.5
5.0
7.5
S21, dB
-40
-30
-20
-10
0
10
S11, S
22, d
B
• Simple common-emitter design conjugately matched at 200 GHz
• Simulations predicted 6.2 dB gain
• Designed using hybrid-pi model derived from DC-50 GHz measurements of previous generation devices
• Electromagnetic simulator (Agilent’s Momentum) was used to characterize critical passive elements
• Shunt R-C network at output provides low frequency stabilization
0.2pF
50 301.2ps
50
300.2ps
801.2ps
0.6ps
801.2ps
50
IN
OUT
S21
S11,S22
Amplifier Design
Schematic
• Transferred-substrate technology provides low inductance microstrip wiring environment
Ideal for Mixed Signal ICs
• Advantages for MMIC design: Low via inductance Reduced fringing fields
• Disadvantages for MMIC design: Increased conductor losses
• Resistive losses are inversely proportional to the substrate thickness for a given Zo
• Amplifier simulations with lossless matching network showed 2 dB more gain
• Possible Solutions: Use airbridge transmission lines Find optimum substrate thickness
Design Considerations in Sub-mmwave Bands
• HP8510C VNA with Oleson Microwave Lab mmwave Extenders
• GGB Industries coplanar wafer probes with WR-5 waveguide connectors
• Full-two port T/R measurement capability
• Line-Reflect-Line calibration with on-wafer standards
• Internal bias Tee’s in probes for biasing active devices
140-220 GHz VNA Measurements
UCSB 140-220 GHz VNA Measurement Set-up
Amplifier Measurements
• Measured 6.3 dB peak gain at 175 GHz
• Device dimensions: Emitter area: 0.4 x 6 m2
Collector area: 0.7 x 6.4 m2
• Device bias conditions: Ic= 4.8 mA, VCE = 1.2 V
Cell Dimensions: 690m x 350 m
150 160 170 180 190 200 210140 220
-2
0
2
4
6
-4
8
Frequency, GHz
S21
, dB
150 160 170 180 190 200 210140 220
-16
-12
-8
-4
-20
0
Frequency, GHz
S11
, S22
, dB
S11
S22
S21
• Amplifier designed for 200 GHz
• Peak gain measured at 175 GHz
• Possible sources for discrepancy: Matching network design Device model
Simulation vs. Measurement
150 160 170 180 190 200 210140 220
-2.5
0.0
2.5
5.0
-5.0
7.5
Frequency, GHz
S21, dB
Sim.Meas.
150 160 170 180 190 200 210140 220
-35
-30
-25
-20
-15
-10
-5
-40
0
Frequency, GHz
S11,S
22, d
BMeas.
Sim.
• Breakout of matching network without active device was measured on-wafer
• Measurement compared to circuit simulation of passive components
• Simulation shows good agreement with measurement
• Verifies design approach of combining E-M simulation of critical passive elements with standard microstrip models
Matching Network BreakoutSimulation Vs. Measurement
freq (140.0GHz to 220.0GHz)
S21
S22
S11
Red- SimulationBlue- Measurement
Matching Network Design
• Design used a hybrid-pi device model based on DC-50 GHz measurements
• Measurements of individual devices in 140-220 GHz band show poor agreement with model
• Discrepancies may be due to weakness in device model and/or measurement inaccuracies
• Device dimensions: Emitter area: 0.4 x 6 m2
Collector area: 0.7 x 6.4 m2
• Bias Conditions: VCE = 1.2 V, IC = 4.8 mA
HBT Hybrid-Pi ModelDerived from DC-50 GHz Measurements
Device Modeling I: Hybrid-Pi Model
1.59
43
7.0
45
9.5
17
0.4
281
0.60
0.126
76
-5 -4 -3 -2 -1 0 1 2 3 4 5
freq (140.0GHz to 220.0GHz)freq (6.000GHz to 45.00GHz)freq (6.000GHz to 45.00GHz)freq (140.0GHz to 220.0GHz)
-0.15 -0.10 -0.05 0.00 0.05 0.10 0.15
freq (140.0GHz to 220.0GHz)freq (6.000GHz to 45.00GHz)freq (6.000GHz to 45.00GHz)freq (140.0GHz to 220.0GHz)
• Measurements and simulations of device from 6-45 GHz and 140-220 GHz
• Large discrepancies in S11 and S22
• Anomalous S12 believed to be due to excessive probe-to-probe coupling
Red- SimulationBlue- Measurement
Device Modeling II: Model vs. Measurement
S11, S22
S21
S12
• Simulated amplifier using measured device S-parameters in the 140-220 GHz band
• Simulation shows good agreement with measured amplifier results
• Results point to weakness in hybrid-pi model used in the design
• Improved device models are necessary for better physical understanding but measured S-parameter can be used in future amplifier designs
Simulation versus Measured ResultsSimulation Using Measured Device S-parameters
Simulation vs. Measurement
150 160 170 180 190 200 210140 220
-2.5
0.0
2.5
5.0
-5.0
7.5
Frequency, GHz
S21, dB
Sim.Meas.
150 160 170 180 190 200 210140 220
-35
-30
-25
-20
-15
-10
-5
-40
0
Frequency, GHz
S11,S
22, d
B
Meas.
Sim.
Multi-stage Amplifier Design
• Three-stage amplifier designed using measured transistor S-parameters
• Simulated 20 dB gain at 175 GHz
• Design currently being fabricated
Simulation Results
Multi-stage amplifier layout 150 160 170 180 190 200 210140 220
-20
-10
0
10
20
-30
30
Freq (GHz)
S21
(dB
)
150 160 170 180 190 200 210140 220
-40-35
-30
-25
-20-15
-10
-5
-45
0
Freq (GHz)
S11
,S22
(dB
)
Conclusions UCSB
• Single-stage HBT amplifier with 6.3 dB at 175 GHz • Simple design provides direction for future high frequency MMIC work in
transferred-substrate process• Observed anomalies in extending hybrid-pi model to higher frequencies
Future Work• Multi-stage amplifiers and oscillators• Improved device performance for higher frequency operation
AcknowledgementsThis work was supported by the ONR under grant N0014-99-1-0041
And the AFOSR under grant F49620-99-1-0079
GaAs IC 2001