Post on 25-Nov-2014
transcript
Semiconductor Components Industries, LLC, 1999
August, 1999 – Rev. 21 Publication Order Number:
AN1048/D
By George TempletonThyristor Applications Engineer
INTRODUCTION
Edited and Updated
RC networks are used to control voltage transients thatcould falsely turn-on a thyristor. These networks are calledsnubbers.
The simple snubber consists of a series resistor andcapacitor placed around the thyristor. These componentsalong with the load inductance form a series CRL circuit.Snubber theory follows from the solution of the circuit’sdifferential equation.
Many RC combinations are capable of providing accept-able performance. However, improperly used snubbers cancause unreliable circuit operation and damage to the semi-conductor device.
Both turn-on and turn-off protection may be necessaryfor reliability. Sometimes the thyristor must function with arange of load values. The type of thyristors used, circuitconfiguration, and load characteristics are influential.
Snubber design involves compromises. They includecost, voltage rate, peak voltage, and turn-on stress. Practi-cal solutions depend on device and circuit physics.
STATIC dVdt
WHAT IS STATIC dVdt
?
Static dVdt
is a measure of the ability of a thyristor to
retain a blocking state under the influence of a voltagetransient.
dVdt
s DEVICE PHYSICS
Static dVdt
turn-on is a consequence of the Miller effect
and regeneration (Figure 1). A change in voltage across thejunction capacitance induces a current through it. This cur-
rent is proportional to the rate of voltage change dVdt . It
triggers the device on when it becomes large enough toraise the sum of the NPN and PNP transistor alphas to unity.
Figure 6.1. ModeldVdt
s
IA CJ
dVdt
1 (N p)
CEFFCJ
1(Np)
IBP
IJ
IJ
IK
IBN
ICN
I1
I2
ICP
IA
TWO TRANSISTOR MODELOF
SCR
CJN
CJP
PNP
A
C
G
CJ
NE
PB
NB
PEV
tGNPN
INTEGRATEDSTRUCTURE
K
A
K
dvdt
http://onsemi.com
APPLICATION NOTE
AN1048/D
http://onsemi.com2
CONDITIONS INFLUENCING dVdt
s
Transients occurring at line crossing or when there is noinitial voltage across the thyristor are worst case. The col-lector junction capacitance is greatest then because thedepletion layer widens at higher voltage.
Small transients are incapable of charging the self-capacitance of the gate layer to its forward biased thresholdvoltage (Figure 2). Capacitance voltage divider actionbetween the collector and gate-cathode junctions and built-in resistors that shunt current away from the cathode emit-ter are responsible for this effect.
PEAK MAIN TERMINAL VOLTAGE (VOLTS)
700 800
80
60
MAC 228A10 TRIACTJ = 110°C
600500400300200
100
120
140
160
201000
180
40
STAT
IC
(
V/
s) µdV dt
Figure 6.2. Exponential versus Peak VoltagedVdt
s
Static dVdt
does not depend strongly on voltage for opera-
tion below the maximum voltage and temperature rating.Avalanche multiplication will increase leakage current and
reduce dVdt
capability if a transient is within roughly 50 volts
of the actual device breakover voltage.
A higher rated voltage device guarantees increased dVdt
at
lower voltage. This is a consequence of the exponential rat-ing method where a 400 V device rated at 50 V/µs has a
higher dVdt
to 200 V than a 200 V device with an identical
rating. However, the same diffusion recipe usually appliesfor all voltages. So actual capabilities of the product are notmuch different.
Heat increases current gain and leakage, lowering
dVdt
s, the gate trigger voltage and noise immunity
(Figure 3).
Figure 6.3. Exponential versus TemperaturedVdt
s
STAT
IC
(
V/
s) µdV dt
170
150
130
110
30
50
70
90
100 115 130 14585705540
MAC 228A10VPK = 800 V
TJ, JUNCTION TEMPERATURE (°C)
2510
dVdt
s
FAILURE MODE
Occasional unwanted turn-on by a transient may beacceptable in a heater circuit but isn’t in a fire preventionsprinkler system or for the control of a large motor. Turn-onis destructive when the follow-on current amplitude or rateis excessive. If the thyristor shorts the power line or acharged capacitor, it will be damaged.
Static dVdt
turn-on is non-destructive when series imped-
ance limits the surge. The thyristor turns off after a half-
cycle of conduction. High dVdt
aids current spreading in the
thyristor, improving its ability to withstand dIdt
. Breakdown
turn-on does not have this benefit and should be prevented.
Figure 6.4. Exponential versusGate to MT 1 Resistance
dVdt
s
STAT
IC
(
V/
s) µdV dt
20
100 10000
10 10,000GATE-MT1 RESISTANCE (OHMS)
MAC 228A10800 V 110°C
40
60
80
100
120
140
RINTERNAL = 600 Ω
AN1048/D
http://onsemi.com3
IMPROVING dVdt
s
Static dVdt
can be improved by adding an external resistor
from the gate to MT1 (Figure 4). The resistor provides a
path for leakage and dVdt
induced currents that originate in
the drive circuit or the thyristor itself.Non-sensitive devices (Figure 5) have internal shorting
resistors dispersed throughout the chip’s cathode area. Thisdesign feature improves noise immunity and high tempera-ture blocking stability at the expense of increased triggerand holding current. External resistors are optional for non-sensitive SCRs and TRIACs. They should be comparable insize to the internal shorting resistance of the device (20 to100 ohms) to provide maximum improvement. The internalresistance of the thyristor should be measured with an ohm-meter that does not forward bias a diode junction.
Figure 6.5. Exponential versusJunction Temperature
dVdt
s
STAT
IC
(
V/
s) µdV dt
800
1000
1200
1400
130120110100
2000
2200
1800
1600
9080706050600
TJ, JUNCTION TEMPERATURE (°C)
MAC 15-8VPK = 600 V
Sensitive gate TRIACs run 100 to 1000 ohms. With an
external resistor, their dVdt
capability remains inferior to
non-sensitive devices because lateral resistance within thegate layer reduces its benefit.
Sensitive gate SCRs (IGT 200 µA) have no built-inresistor. They should be used with an external resistor. Therecommended value of the resistor is 1000 ohms. Higher
values reduce maximum operating temperature and dVdt
s(Figure 6). The capability of these parts varies by more than100 to 1 depending on gate-cathode termination.
GAT
E-C
ATH
OD
E R
ESIS
TAN
CE
(OH
MS)
Figure 6.6. Exponential versusGate-Cathode Resistance
dVdt
s
10MEG
1MEG
100K
0.01 1001010K
0.1 1
MCR22-006TA = 65°C
0.001
KG
A10V
STATIC dVdt
(Vs)
A gate-cathode capacitor (Figure 7) provides a shuntpath for transient currents in the same manner as the resis-tor. It also filters noise currents from the drive circuit andenhances the built-in gate-cathode capacitance voltagedivider effect. The gate drive circuit needs to be able tocharge the capacitor without excessive delay, but it doesnot need to supply continuous current as it would for a
resistor that increases dVdt
the same amount. However, the
capacitor does not enhance static thermal stability.
Figure 6.7. Exponential versus Gateto MT1 Capacitance
dVdt
s
STAT
IC
(
V/
s) µdV dt
GATE TO MT1 CAPACITANCE (µF)
130
120
110
100
90
80
70
60
MAC 228A10800 V 110°C
10.10.010.001
The maximum dVdt
s improvement occurs with a short.
Actual improvement stops before this because of spreadingresistance in the thyristor. An external capacitor of about0.1 µF allows the maximum enhancement at a higher valueof RGK.
AN1048/D
http://onsemi.com4
One should keep the thyristor cool for the highest dVdt
s.
Also devices should be tested in the application circuit atthe highest possible temperature using thyristors with thelowest measured trigger current.
TRIAC COMMUTATING dVdt
WHAT IS COMMUTATING dVdt
?
The commutating dVdt
rating applies when a TRIAC has
been conducting and attempts to turn-off with an inductiveload. The current and voltage are out of phase (Figure 8).The TRIAC attempts to turn-off as the current drops belowthe holding value. Now the line voltage is high and in theopposite polarity to the direction of conduction. Successfulturn-off requires the voltage across the TRIAC to rise to theinstantaneous line voltage at a rate slow enough to preventretriggering of the device.
TIMEΦ
i
PHASEANGLE
iVLINE G
1
2R L
TIME
VLINE
MT2
-1V
VOLT
AGE/
CU
RR
ENT
Figure 6.8. TRIAC Inductive Load Turn-Off dVdt
c
dIdt
c
dVdt
c
VMT2-1
dVdt
c DEVICE PHYSICS
A TRIAC functions like two SCRs connected in inverse-parallel. So, a transient of either polarity turns it on.
There is charge within the crystal’s volume because ofprior conduction (Figure 9). The charge at the boundariesof the collector junction depletion layer responsible for
dVdt
s is also present. TRIACs have lower dV
dt
c than
dVdt
s because of this additional charge.
The volume charge storage within the TRIAC dependson the peak current before turn-off and its rate of zero
crossing dIdt
c. In the classic circuit, the load impedance
and line frequency determine dIdt
c. The rate of crossing
for sinusoidal currents is given by the slope of the secantline between the 50% and 0% levels as:
dIdt
c
6 f ITM1000
Ams
where f = line frequency and ITM = maximum on-state cur-rent in the TRIAC.
Turn-off depends on both the Miller effect displacement
current generated by dVdt
across the collector capacitance
and the currents resulting from internal charge storagewithin the volume of the device (Figure 10). If the reverserecovery current resulting from both these components ishigh, the lateral IR drop within the TRIAC base layer willforward bias the emitter and turn the TRIAC on. Commu-
tating dVdt
capability is lower when turning off from the pos-
itive direction of current conduction because of devicegeometry. The gate is on the top of the die and obstructscurrent flow.
Recombination takes place throughout the conductionperiod and along the back side of the current wave as itdeclines to zero. Turn-off capability depends on its shape. If
the current amplitude is small and its zero crossing dIdt
c is
low, there is little volume charge storage and turn-off
becomes limited by dVdt
s. At moderate current amplitudes,
the volume charge begins to influence turn-off, requiring alarger snubber. When the current is large or has rapid zero
crossing, dVdt
c has little influence. Commutating dI
dt and
delay time to voltage reapplication determine whether turn-off will be successful or not (Figures 11, 12).
STORED CHARGEFROM POSITIVECONDUCTION
PreviouslyConducting Side
NP
+ –
LATERAL VOLTAGEDROP
REVERSE RECOVERYCURRENT PATH
G MT1
TOP
MT2
N N N
N
N N N
Figure 6.9. TRIAC Structure and Current Flowat Commutation
AN1048/D
http://onsemi.com5
CHARGEDUE TO
dV/dt
Figure 6.10. TRIAC Current and Voltageat Commutation
didt
c
dVdt
c
TIME
IRRMVOLUME
STORAGECHARGE
VMT2-1
0
VOLT
AGE/
CU
RR
ENT
MAI
N T
ERM
INAL
VO
LTAG
E (V
)
Figure 6.11. Snubber Delay Time
E
td0
VT
TIME
EV
NO
RM
ALIZ
ED D
ELAY
TIM
E
Figure 6.12. Delay Time To Normalized Voltage
0.2
DAMPING FACTOR
0.02
0.03
0.05
0.1
0.2
0.5
10.50.30.001 0.002 0.005 0.01 0.02 0.2
0.1
0.05
0.02
0.01
0.05 0.1
(t *
= W
d0
0.005VTE
RL = 0M = 1IRRM = 0
t d)CONDITIONS INFLUENCING dV
dt
c
Commutating dVdt
depends on charge storage and recov-
ery dynamics in addition to the variables influencing staticdVdt
. High temperatures increase minority carrier life-time
and the size of recovery currents, making turn-off more dif-ficult. Loads that slow the rate of current zero-crossing aidturn-off. Those with harmonic content hinder turn-off.
Circuit Examples
Figure 13 shows a TRIAC controlling an inductive loadin a bridge. The inductive load has a time constant longerthan the line period. This causes the load current to remainconstant and the TRIAC current to switch rapidly as the linevoltage reverses. This application is notorious for causing
TRIAC turn-off difficulty because of high dIdt
c.
Figure 6.13. Phase Controlling a Motor in a Bridge
LR8.3 s
+
t
i
CRS
60 Hz
LS
–R L
DC MOTOR
i
dIdtc
High currents lead to high junction temperatures andrates of current crossing. Motors can have 5 to 6 times thenormal current amplitude at start-up. This increases bothjunction temperature and the rate of current crossing, lead-ing to turn-off problems.
The line frequency causes high rates of current crossingin 400 Hz applications. Resonant transformer circuits aredoubly periodic and have current harmonics at both the pri-mary and secondary resonance. Non-sinusoidal currentscan lead to turn-off difficulty even if the current amplitudeis low before zero-crossing.
dVdt
c FAILURE MODE
dVdt
c failure causes a loss of phase control. Temporary
turn-on or total turn-off failure is possible. This can bedestructive if the TRIAC conducts asymmetrically causing adc current component and magnetic saturation. The windingresistance limits the current. Failure results because ofexcessive surge current and junction temperature.
AN1048/D
http://onsemi.com6
IMPROVING dVdt
c
The same steps that improve dVdt
s aid dV
dt
c except
when stored charge dominates turn-off. Steps that reducethe stored charge or soften the commutation are necessarythen.
Larger TRIACs have better turn-off capability thansmaller ones with a given load. The current density is lowerin the larger device allowing recombination to claim agreater proportion of the internal charge. Also junctiontemperatures are lower.
TRIACs with high gate trigger currents have greaterturn-off ability because of lower spreading resistance in thegate layer, reduced Miller effect, or shorter lifetime.
The rate of current crossing can be adjusted by adding acommutation softening inductor in series with the load.Small high permeability “square loop” inductors saturatecausing no significant disturbance to the load current. Theinductor resets as the current crosses zero introducing alarge inductance into the snubber circuit at that time. Thisslows the current crossing and delays the reapplication ofblocking voltage aiding turn-off.
The commutation inductor is a circuit element thatintroduces time delay, as opposed to inductance, into the
circuit. It will have little influence on observed dVdt
at the
device. The following example illustrates the improvementresulting from the addition of an inductor constructed bywinding 33 turns of number 18 wire on a tape wound core(52000-1A). This core is very small having an outsidediameter of 3/4 inch and a thickness of 1/8 inch. The delaytime can be calculated from:
ts (N A B 108)
Ewhere:
ts = time delay to saturation in seconds.B = saturating flux density in GaussA = effective core cross sectional area in cm2
N = number of turns.
For the described inductor:
ts (33 turns) (0.076 cm2) (28000 Gauss)
(1 10–8) (175 V) 4.0 s.
The saturation current of the inductor does not need to bemuch larger than the TRIAC trigger current. Turn-off fail-ure will result before recovery currents become greater thanthis value. This criterion allows sizing the inductor with thefollowing equation:
Is Hs ML0.4 N
where :
Hs = MMF to saturate = 0.5 OerstedML = mean magnetic path length = 4.99 cm.
Is (.5) (4.99)
.4 33 60 mA.
SNUBBER PHYSICS
UNDAMPED NATURAL RESONANCE
0 ILC Radianssecond
Resonance determines dVdt
and boosts the peak capacitor
voltage when the snubber resistor is small. C and L are
related to one another by ω02. dVdt
scales linearly with ω0when the damping factor is held constant. A ten to one
reduction in dVdt
requires a 100 to 1 increase in either
component.
DAMPING FACTOR
ρ R2
CL
The damping factor is proportional to the ratio of thecircuit loss and its surge impedance. It determines the trade
off between dVdt
and peak voltage. Damping factors between
0.01 and 1.0 are recommended.
The Snubber Resistor
Damping and dVdt
When ρ 0.5, the snubber resistor is small, and dVdt
depends mostly on resonance. There is little improvement
in dVdt
for damping factors less than 0.3, but peak voltage
and snubber discharge current increase. The voltage wavehas a 1-COS (θ) shape with overshoot and ringing. Maxi-
mum dVdt
occurs at a time later than t = 0. There is a time
delay before the voltage rise, and the peak voltage almostdoubles.
When ρ 0.5, the voltage wave is nearly exponential in
shape. The maximum instantaneous dVdt
occurs at t = 0.
There is little time delay and moderate voltage overshoot.
When ρ 1.0, the snubber resistor is large and dVdt
depends mostly on its value. There is some overshoot eventhrough the circuit is overdamped.
High load inductance requires large snubber resistors andsmall snubber capacitors. Low inductances imply smallresistors and large capacitors.
AN1048/D
http://onsemi.com7
Damping and Transient Voltages
Figure 14 shows a series inductor and filter capacitorconnected across the ac main line. The peak to peak voltageof a transient disturbance increases by nearly four times.Also the duration of the disturbance spreads because ofringing, increasing the chance of malfunction or damage tothe voltage sensitive circuit. Closing a switch causes thisbehavior. The problem can be reduced by adding a dampingresistor in series with the capacitor.
V (V
OLT
S)
Figure 6.14. Undamped LC Filter Magnifies andLengthens a Transient
V0.1µF
100 µH 0.05
0 10 µs
340 VVOLTAGESENSITIVECIRCUIT
0
+ 700
– 700
TIME (µs)0 2010
dIdt
Non-Inductive Resistor
The snubber resistor limits the capacitor discharge
current and reduces dIdt
stress. High dIdt
destroys the thyristor
even though the pulse duration is very short.The rate of current rise is directly proportional to circuit
voltage and inversely proportional to series inductance.The snubber is often the major offender because of its lowinductance and close proximity to the thyristor.
With no transient suppressor, breakdown of the thyristorsets the maximum voltage on the capacitor. It is possible toexceed the highest rated voltage in the device seriesbecause high voltage devices are often used to supply lowvoltage specifications.
The minimum value of the snubber resistor depends onthe type of thyristor, triggering quadrants, gate currentamplitude, voltage, repetitive or non-repetitive operation,and required life expectancy. There is no simple way to pre-dict the rate of current rise because it depends on turn-onspeed of the thyristor, circuit layout, type and size of snub-ber capacitor, and inductance in the snubber resistor. Theequations in Appendix D describe the circuit. However, thevalues required for the model are not easily obtained exceptby testing. Therefore, reliability should be verified in theactual application circuit.
Table 1 shows suggested minimum resistor values esti-mated (Appendix A) by testing a 20 piece sample from thefour different TRIAC die sizes.
Table 1. Minimum Non-inductive Snubber Resistorfor Four Quadrant Triggering.
TRIAC TypePeak VC
VoltsRs
Ohms
dIdt
A/µs
Non-Sensitive Gate(IGT 10 mA)8 to 40 A(RMS)
200300400600800
3.36.8113951
170250308400400
Reducing dIdt
TRIAC dIdt
can be improved by avoiding quadrant 4
triggering. Most optocoupler circuits operate the TRIAC inquadrants 1 and 3. Integrated circuit drivers use quadrants 2and 3. Zero crossing trigger devices are helpful becausethey prohibit triggering when the voltage is high.
Driving the gate with a high amplitude fast rise pulse
increases dIdt
capability. The gate ratings section defines the
maximum allowed current.Inductance in series with the snubber capacitor reduces
dIdt
. It should not be more than five percent of the load
inductance to prevent degradation of the snubber’s dVdt
suppression capability. Wirewound snubber resistorssometimes serve this purpose. Alternatively, a separateinductor can be added in series with the snubber capacitor.It can be small because it does not need to carry the loadcurrent. For example, 18 turns of AWG No. 20 wire on aT50-3 (1/2 inch) powdered iron core creates a non-saturat-ing 6.0 µH inductor.
A 10 ohm, 0.33 µF snubber charged to 650 volts resulted
in a 1000 A/µs dIdt
. Replacement of the non-inductive snub-
ber resistor with a 20 watt wirewound unit lowered the rateof rise to a non-destructive 170 A/µs at 800 V. The inductorgave an 80 A/µs rise at 800 V with the non–inductiveresistor.
The Snubber Capacitor
A damping factor of 0.3 minimizes the size of the snub-
ber capacitor for a given value of dVdt
. This reduces the cost
and physical dimensions of the capacitor. However, it raisesvoltage causing a counter balancing cost increase.
Snubber operation relies on the charging of the snubbercapacitor. Turn-off snubbers need a minimum conductionangle long enough to discharge the capacitor. It should be atleast several time constants (RS CS).
AN1048/D
http://onsemi.com8
STORED ENERGY
Inductive Switching Transients
E 12
L I02 Watt-seconds or Joules
I0 = current in Amperes flowing in theinductor at t = 0.
Resonant charging cannot boost the supply voltage atturn-off by more than 2. If there is an initial current flowingin the load inductance at turn-off, much higher voltages arepossible. Energy storage is negligible when a TRIAC turnsoff because of its low holding or recovery current.
The presence of an additional switch such as a relay, ther-mostat or breaker allows the interruption of load current andthe generation of high spike voltages at switch opening. Theenergy in the inductance transfers into the circuit capacitanceand determines the peak voltage (Figure 15).
dVdt
IC
VPK I LC
Figure 6.15. Interrupting Inductive Load Current
VPK
C
L
I
FAST
SLOW
(b.) Unprotected Circuit(a.) Protected Circuit
OPTIONALR
Capacitor Discharge
The energy s tored in the snubber capac i tor
Ec 12
CV2 transfers to the snubber resistor and
thyristor every time it turns on. The power loss is propor-tional to frequency (PAV = 120 Ec @ 60 Hz).
CURRENT DIVERSION
The current flowing in the load inductor cannot changeinstantly. This current diverts through the snubber resistor
causing a spike of theoretically infinite dVdt
with magnitude
equal to (IRRM R) or (IH R).
LOAD PHASE ANGLE
Highly inductive loads cause increased voltage and
dVdt
c at turn-off. However, they help to protect the
thyristor from transients and dVdt
s. The load serves as the
snubber inductor and limits the rate of inrush current if the
device does turn on. Resistance in the load lowers dVdt
and
VPK (Figure 16).
dVdt
M = 0.25
M = 0.5
M = 0.75
VPK
1.3
E
0.4
0.2
00 0.2 0.4 0.6 0.8 1
0.9
1
1.1
1.2
1.4
1.5
1.6
1.7
1.4
1.2
1
0.8
0.6
2.2
2.1
2
1.9
1.8
DAMPING FACTOR
M = 0
M = RS / (RL + RS)
M = 1
dV dt( )
0
NO
RM
ALIZ
EDdV dt
M RESISTIVE DIVISION RATIO RS
RL RS
IRRM 0
Figure 6.16. 0 To 63% dVdt
/ (E
W )
NO
RM
ALIZ
ED P
EAK
VOLT
AGE
V
/EPK
CHARACTERISTIC VOLTAGE WAVES
Damping factor and reverse recovery current determinethe shape of the voltage wave. It is not exponential whenthe snubber damping factor is less than 0.5 (Figure 17) orwhen significant recovery currents are present.
V
(VO
LTS)
MT 2-
1
063% dVdt
s 100 Vs, E 250 V,
RL 0, IRRM 0
Figure 6.17. Voltage Waves For DifferentDamping Factors
ρ = 0
1
TIME (µs)
0.30.1
0
ρ = 0.1
ρ = 0.3 ρ = 1
3.52.82.1 4.2 4.9 5.6 6.30.70
100
200
300
400500
1.4 70
AN1048/D
http://onsemi.com9
NO
RM
ALIZ
ED P
EAK
VOLT
AGE
AND
dV dt
(RL 0, M 1, IRRM 0)
NORMALIZED dVdt
dVdtE 0
NORMALIZED VPK VPK
E
Figure 6.18. Trade-Off Between V PK and dVdt
DAMPING FACTOR (ρ)0
0–63%E
1
10–63%
0.80.60.40.2 1.2 1.81.4 1.6 2
2.8
2.6
2.4
2.2
1.8
1.6
1.4
2
1
1.2
0.80.6
0.4
0.2
0
dVdt
dVdt
o
VPKdVdt
10–63%
dVdtMAX
A variety of wave parameters (Figure 18) describe dVdt
Some are easy to solve for and assist understanding. These
include the initial dVdt
, the maximum instantaneous dVdt
, and
the average dVdt
to the peak reapplied voltage. The 0 to 63%
dVdt
s and 10 to 63% dV
dt
c definitions on device data
sheets are easy to measure but difficult to compute.
NON-IDEAL BEHAVIORSCORE LOSSES
The magnetic core materials in typical 60 Hz loadsintroduce losses at the snubber natural frequency. Theyappear as a resistance in series with the load inductance and
winding dc resistance (Figure 19). This causes actual dVdt
to
be less than the theoretical value.
Figure 6.19. Inductor Model
L R
C
L DEPENDS ON CURRENT AMPLITUDE, CORESATURATION
R INCLUDES CORE LOSS, WINDING R. INCREASESWITH FREQUENCY
C WINDING CAPACITANCE. DEPENDS ONINSULATION, WIRE SIZE, GEOMETRY
COMPLEX LOADS
Many real-world inductances are non-linear. Their corematerials are not gapped causing inductance to vary withcurrent amplitude. Small signal measurements poorly char-acterize them. For modeling purposes, it is best to measurethem in the actual application.
Complex load circuits should be checked for transientvoltages and currents at turn-on and off. With a capacitiveload, turn-on at peak input voltage causes the maximumsurge current. Motor starting current runs 4 to 6 times thesteady state value. Generator action can boost voltagesabove the line value. Incandescent lamps have cold startcurrents 10 to 20 times the steady state value. Transformersgenerate voltage spikes when they are energized. Powerfactor correction circuits and switching devices createcomplex loads. In most cases, the simple CRL modelallows an approximate snubber design. However, there isno substitute for testing and measuring the worst case loadconditions.
SURGE CURRENTS IN INDUCTIVE CIRCUITS
Inductive loads with long L/R time constants causeasymmetric multi-cycle surges at start up (Figure 20). Trig-gering at zero voltage crossing is the worst case condition.The surge can be eliminated by triggering at the zero cur-rent crossing angle.
i (AM
PER
ES)
Figure 6.20. Start-Up Surge For Inductive Circuit
240VAC
20 MHY
i 0.1Ω
TIME (MILLISECONDS)
40
ZERO VOLTAGE TRIGGERING, IRMS = 30 A
0
90
80 160120 200
Core remanence and saturation cause surge currents.They depend on trigger angle, line impedance, core charac-teristics, and direction of the residual magnetization. Forexample, a 2.8 kVA 120 V 1:1 transformer with a 1.0ampere load produced 160 ampere currents at start-up. Softstarting the circuit at a small conduction angle reduces thiscurrent.
Transformer cores are usually not gapped and saturateeasily. A small asymmetry in the conduction angle causesmagnetic saturation and multi-cycle current surges.
AN1048/D
http://onsemi.com10
Steps to achieve reliable operation include: 1. Supply sufficient trigger current amplitude. TRIACs
have different trigger currents depending on theirquadrant of operation. Marginal gate current oroptocoupler LED current causes halfwave operation.
2. Supply sufficient gate current duration to achievelatching. Inductive loads slow down the main terminalcurrent rise. The gate current must remain above thespecified IGT until the main terminal current exceedsthe latching value. Both a resistive bleeder around theload and the snubber discharge current help latching.
3. Use a snubber to prevent TRIAC dVdt
c failure.
4. Minimize designed-in trigger asymmetry. Triggeringmust be correct every half-cycle including the first. Usea storage scope to investigate circuit behavior during thefirst few cycles of turn-on. Alternatively, get the gatecircuit up and running before energizing the load.
5. Derive the trigger synchronization from the line insteadof the TRIAC main terminal voltage. This avoidsregenerative interaction between the core hysteresisand the triggering angle preventing trigger runaway,halfwave operation, and core saturation.
6. Avoid high surge currents at start-up. Use a currentprobe to determine surge amplitude. Use a soft startcircuit to reduce inrush current.
DISTRIBUTED WINDING CAPACITANCE
There are small capacitances between the turns and lay-ers of a coil. Lumped together, they model as a single shuntcapacitance. The load inductor behaves like a capacitor atfrequencies above its self-resonance. It becomes ineffective
in controlling dVdt
and VPK when a fast transient such as that
resulting from the closing of a switch occurs. This problemcan be solved by adding a small snubber across the line.
SELF-CAPACITANCE
A thyristor has self-capacitance which limits dVdt
when the
load inductance is large. Large load inductances, high powerfactors, and low voltages may allow snubberless operation.
SNUBBER EXAMPLES
WITHOUT INDUCTANCE
Power TRIAC Example
Figure 21 shows a transient voltage applied to a TRIACcontrolling a resistive load. Theoretically there will be aninstantaneous step of voltage across the TRIAC. The onlyelements slowing this rate are the inductance of the wiringand the self-capacitance of the thyristor. There is an expo-nential capacitor charging component added along with adecaying component because of the IR drop in the snubber
resistor. The non-inductive snubber circuit is useful whenthe load resistance is much larger than the snubber resistor.
e(t o) E RSRS RL
et (1 et)
Figure 6.21. Non-Inductive Snubber Circuit
Vstep ERS
RS RL
RESISTORCOMPONENT
TIMEt = 0
eE τ = (RL + RS) CS
e
CS
RS
RL
E
CAPACITORCOMPONENT
Opto-TRIAC Examples
Single Snubber, Time Constant Design
Figure 22 illustrates the use of the RC time constantdesign method. The optocoupler sees only the voltageacross the snubber capacitor. The resistor R1 supplies thetrigger current of the power TRIAC. A worst case designprocedure assumes that the voltage across the powerTRIAC changes instantly. The capacitor voltage rises to63% of the maximum in one time constant. Then:
R1 CS 0.63 E
dVdt
s
where dVdt
sis the rated static dV
dt
for the optocoupler.
DESIGN dVdt
(0.63) (170)
(2400) (0.1 F) 0.45 Vs
φ CNTL
MOC3021
10 V/µs
TIME240 µs
0.63 (170)
L = 318 MHY
1 A, 60 Hz
RinVCC
C10.1 µF
170 V6 2.4 k18012N6073A
1 V/µs4
2
dVdt
(Vs)
Power TRIAC Optocoupler
0.99 0.35
Figure 6.22. Single Snubber For Sensitive Gate TRIACand Phase Controllable Optocoupler ( ρ = 0.67)
AN1048/D
http://onsemi.com11
The optocoupler conducts current only long enough totrigger the power device. When it turns on, the voltagebetween MT2 and the gate drops below the forward thresh-old voltage of the opto-TRIAC causing turn-off. The opto-
coupler sees dVdt
s when the power TRIAC turns off later
in the conduction cycle at zero current crossing. Therefore,it is not necessary to design for the lower optocoupler
dVdt
c rating. In this example, a single snubber designed
for the optocoupler protects both devices.
Figure 6.23. Anti-Parallel SCR Driver
(50 V/µs SNUBBER, ρ = 1.0)
120 V400 Hz
1 MHY
MCR265–4
430
100
MCR265–4
1N4001
0.022µF
1
51
1N4001
100VCC
6
5
4
3
2
MO
C30
31
Optocouplers with SCRs
Anti-parallel SCR circuits result in the same dVdt
across
the optocoupler and SCR (Figure 23). Phase controllableopto-couplers require the SCRs to be snubbed to their lowerdVdt
rating. Anti-parallel SCR circuits are free from the
charge storage behaviors that reduce the turn-off capabilityof TRIACs. Each SCR conducts for a half-cycle and has thenext half cycle of the ac line in which to recover. The turn-
off dVdt
of the conducting SCR becomes a static forward
blocking dVdt
for the other device. Use the SCR data sheet
dVdt
s rating in the snubber design.
A SCR used inside a rectifier bridge to control an ac loadwill not have a half cycle in which to recover. The availabletime decreases with increasing line voltage. This makes thecircuit less attractive. Inductive transients can be sup-pressed by a snubber at the input to the bridge or across theSCR. However, the time limitation still applies.
OPTO dVdt
cZero-crossing optocouplers can be used to switch
inductive loads at currents less than 100 mA (Figure 24).
However a power TRIAC along with the optocouplershould be used for higher load currents.
LOAD
CU
RR
ENT
(mA
RM
S)
Figure 6.24. MOC 3062 Inductive Load Current versus T A
CS = 0.01
CS = 0.001
NO SNUBBER
(RS = 100 Ω, VRMS = 220 V, POWER FACTOR = 0.5)
TA, AMBIENT TEMPERATURE (°C)
020
80
70
60
50
40
30
20
10
100908030 40 50 60 70
A phase controllable optocoupler is recommended with apower device. When the load current is small, a MAC97ATRIAC is suitable.
Unusual circuit conditions sometimes lead to unwanted
operation of an optocoupler in dVdt
c mode. Very large cur-
rents in the power device cause increased voltages betweenMT2 and the gate that hold the optocoupler on. Use of alarger TRIAC or other measures that limit inrush currentsolve this problem.
Very short conduction times leave residual charge in theoptocoupler. A minimum conduction angle allows recoverybefore voltage reapplication.
THE SNUBBER WITH INDUCTANCE
Consider an overdamped snubber using a large capacitorwhose voltage changes insignificantly during the timeunder consideration. The circuit reduces to an equivalentL/R series charging circuit.
The current through the snubber resistor is:
i VR
1 et ,
and the voltage across the TRIAC is:
e i RS.
The voltage wave across the TRIAC has an exponentialrise with maximum rate at t = 0. Taking its derivative givesits value as:
dVdt
0
V RSL
.
AN1048/D
http://onsemi.com12
Highly overdamped snubber circuits are not practicaldesigns. The example illustrates several properties: 1. The initial voltage appears completely across the circuit
inductance. Thus, it determines the rate of change of
current through the snubber resistor and the initial dVdt
.
This result does not change when there is resistance inthe load and holds true for all damping factors.
2. The snubber works because the inductor controls therate of current change through the resistor and the rateof capacitor charging. Snubber design cannot ignorethe inductance. This approach suggests that the snubbercapacitance is not important but that is only true forthis hypothetical condition. The snubber resistor shuntsthe thyristor causing unacceptable leakage when thecapacitor is not present. If the power loss is tolerable,dVdt
can be controlled without the capacitor. An
example is the soft-start circuit used to limit inrushcurrent in switching power supplies (Figure 25).
Figure 6.25. Surge Current Limiting Fora Switching Power Supply
dVdt
ERSL
SNUBBERL G
RS
E
Snubber With No C
E
C1AC LINERECTIFIER
BRIDGE
SNUBBERL
AC LINERECTIFIER
BRIDGE C1G
RS
TRIAC DESIGN PROCEDURE dVdt
c1. Refer to Figure 18 and select a particular damping
factor (ρ) giving a suitable trade-off between VPK and dVdt
.
Determine the normalized dVdt
corresponding to the chosen
damping factor.The voltage E depends on the load phase angle:
E 2 VRMS Sin () where tan1XLRL where
φ = measured phase angle between line V and load IRL = measured dc resistance of the load.Then
Z VRMSIRMS
RL2 XL
2 XL Z2 RL2 and
L XL
2 fLine.
If only the load current is known, assume a pure inductance.This gives a conservative design. Then:
L VRMS
2 fLine IRMSwhere E 2 VRMS.
For example:
E 2 120 170 V; L 120(8 A) (377 rps)
39.8 mH.
Read from the graph at ρ = 0.6, VPK = (1.25) 170 = 213 V.
Use 400 V TRIAC. Read dVdt (ρ0.6)
1.0.
2. Apply the resonance criterion:
0 spec dVdt dV
dt(P)E.
0 5 106 VS(1) (170 V)
29.4 103 r ps.
C 102 L
0.029 F
3. Apply the damping criterion:
RS 2ρ LC 2(0.6) 39.8 103
0.029 106 1400ohms.
dVdt
c SAFE AREA CURVE
Figure 26 shows a MAC15 TRIAC turn-off safeoperating area curve. Turn-off occurs without problem
under the curve. The region is bounded by static dVdt
at low
values of dIdt
c and delay time at high currents. Reduction
of the peak current permits operation at higher linefrequency. This TRIAC operated at f = 400 Hz, TJ = 125°C,and ITM = 6.0 amperes using a 30 ohm and 0.068 µFsnubber. Low damping factors extend operation to higher
dIdt
c, but capacitor sizes increase. The addition of a small,
saturable commutation inductor extends the allowedcurrent rate by introducing recovery delay time.
AN1048/D
http://onsemi.com13
dV dt( )
(V/
s)
µc
dIdt
cAMPERESMILLISECOND
Figure 6.26. versus T J = 125°CdVdt
cdIdt
c
100
10
0.15010
1
WITH COMMUTATION L
3014 18 22 26 34 38 42 46
– ITM = 15 A
dIdt
c 6 f ITM 103 Ams
MAC 16-8, COMMUTATIONAL L 33 TURNS # 18,52000-1A TAPE WOUND CORE 34 INCH OD
STATIC dVdt
DESIGN
There is usually some inductance in the ac main andpower wiring. The inductance may be more than 100 µH ifthere is a transformer in the circuit or nearly zero when ashunt power factor correction capacitor is present. Usuallythe line inductance is roughly several µH. The minimuminductance must be known or defined by adding a seriesinductor to insure reliable operation (Figure 27).
Figure 6.27. Snubbing For a Resistive Load
50 V/µs
0.33 µF10
LS1
100 µH20 A
340V 12 Ω
HEATER
One hundred µH is a suggested value for starting thedesign. Plug the assumed inductance into the equation forC. Larger values of inductance result in higher snubber
resistance and reduced dIdt
. For example:
Given E = 240 2 340 V.
Pick ρ = 0.3.
Then from Figure 18, VPK = 1.42 (340) = 483 V.Thus, it will be necessary to use a 600 V device. Using thepreviously stated formulas for ω0, C and R we find:
0 50 106 VS(0.73) (340 V)
201450 rps
C 1(201450)2 (100 106)
0.2464 F
R 2 (0.3) 100 106
0.2464 106 12 ohms
VARIABLE LOADS
The snubber should be designed for the smallest load
inductance because dVdt
will then be highest because of its
dependence on ω0. This requires a higher voltage device foroperation with the largest inductance because of the corre-sponding low damping factor.
Figure 28 describes dVdt
for an 8.0 ampere load at various
power factors. The minimum inductance is a component
added to prevent static dVdt
firing with a resistive load.
LRMAC 218A6FP
8 A LOAD
68 Ω 120 V60 Hz
0.033 µF
dVdt
s 100 Vs dV
dt
c 5 Vs
ρR L Vstep VPK
dvdtρ
Ω MHY V V V/µs
0.75 15 0.1 170 191 86
0.03 0 39.8 170 325 4.0
0.04 10.6 28.1 120 225 3.3
0.06 13.5 17.3 74 136 2.6
Figure 6.28. Snubber For a Variable Load
AN1048/D
http://onsemi.com14
EXAMPLES OF SNUBBER DESIGNS
Table 2 describes snubber RC values for dVdt
s.
Figures 31 and 32 show possible R and C values for a 5.0
V/µs dVdt
c assuming a pure inductive load.
Table 2. Static Designs
(E = 340 V, Vpeak = 500 V, ρ = 0.3)
dVdt
5.0 V/µs 50 V/µs 100 V/µs
LµH
CµF
ROhm
CµF
ROhm
CµF
ROhm
47 0.15 10100 0.33 10 0.1 20220 0.15 22 0.033 47500 0.068 51 0.015 1101000 3.0 11 0.033 100
TRANSIENT AND NOISE SUPPRESSION
Transients arise internally from normal circuit operationor externally from the environment. The latter is partic-ularly frustrating because the transient characteristics areundefined. A statistical description applies. Greater orsmaller stresses are possible. Long duration high voltagetransients are much less probable than those of loweramplitude and higher frequency. Environments with infre-quent lightning and load switching see transient voltagesbelow 3.0 kV.
Figure 6.29. Snubber Resistor For = 5.0 V/ µsdVdtc
R
(OH
MS)
S
80 A
40 A
20 A
0
0.6 A RMS 2.5 A
5 A
DAMPING FACTOR
10.90.80.70.60.50.40.30.20.1
10K
100
1000
10
10 A
PURE INDUCTIVE LOAD, V 120 VRMS,IRRM 0
Figure 6.30. Snubber Capacitor For = 5.0 V/ µsdVdtc
C
( F
)S
µ
0.001
2.5 A0.01
0.6 A
5 A
10 A
20 A
1
0.1
80 A RMS
40 A
0
DAMPING FACTOR
10.90.80.70.60.50.40.30.20.1
PURE INDUCTIVE LOAD, V 120 VRMS,IRRM 0
The natural frequencies and impedances of indoor acwiring result in damped oscillatory surges with typical fre-quencies ranging from 30 kHz to 1.5 MHz. Surge ampli-tude depends on both the wiring and the source of surgeenergy. Disturbances tend to die out at locations far awayfrom the source. Spark-over (6.0 kV in indoor ac wiring)sets the maximum voltage when transient suppressors arenot present. Transients closer to the service entrance or inheavy wiring have higher amplitudes, longer durations, andmore damping because of the lower inductance at thoselocations.
The simple CRL snubber is a low pass filter attenuatingfrequencies above its natural resonance. A steady statesinusoidal input voltage results in a sine wave output at thesame frequency. With no snubber resistor, the rate of rolloff approaches 12 dB per octave. The corner frequency is atthe snubber’s natural resonance. If the damping factor islow, the response peaks at this frequency. The snubberresistor degrades filter characteristics introducing anup-turn at ω = 1 / (RC). The roll-off approaches 6.0dB/octave at frequencies above this. Inductance in thesnubber resistor further reduces the roll-off rate.
Figure 32 describes the frequency response of the circuitin Figure 27. Figure 31 gives the theoretical response to a3.0 kV 100 kHz ring-wave. The snubber reduces the peakvoltage across the thyristor. However, the fast rise input
causes a high dVdt
step when series inductance is added to the
snubber resistor. Limiting the input voltage with a transientsuppressor reduces the step.
AN1048/D
http://onsemi.com15
Figure 6.31. Theoretical Response of Figure 33 Circuitto 3.0 kV IEEE 587 Ring Wave (R SC = 27.5 Ω)
V
(VO
LTS)
MT 2-
1
400
WITH 5 µHY
450 V MOVAT AC INPUT
WITH 5 µHY ANDWITHOUT 5 µHY
654210
TIME (µs)
3– 400
0
Figure 6.32. Snubber Frequency Response VoutVin
VOLT
AGE
GAI
N (d
B)
FREQUENCY (Hz)10K
WITH 5 µHY
WITHOUT 5µHY
– 40
0.33 µF
10
5 µH
12
Vin
100 µH
1M
+ 10
0
100K
– 30
– 20
– 10
Vout
The noise induced into a circuit is proportional to dVdt
when coupling is by stray capacitance, and dIdt
when the
coupling is by mutual inductance. Best suppressionrequires the use of a voltage limiting device along with arate limiting CRL snubber.
The thyristor is best protected by preventing turn-on
from dVdt
or breakover. The circuit should be designed for
what can happen instead of what normally occurs.In Figure 30, a MOV connected across the line protects
many parallel circuit branches and their loads. The MOV
defines the maximum input voltage and dIdt
through the load.
With the snubber, it sets the maximum dVdt
and peak voltage
across the thyristor. The MOV must be large because thereis little surge limiting impedance to prevent its burn-out.
In Figure 32, there is a separate suppressor across eachthyristor. The load impedance limits the surge energy deliv-ered from the line. This allows the use of a smaller devicebut omits load protection. This arrangement protects eachthyristor when its load is a possible transient source.
Figure 6.33. Limiting Line Voltage
VMAX
Figure 6.34. Limiting Thyristor Voltage
It is desirable to place the suppression device directlyacross the source of transient energy to prevent the induc-tion of energy into other circuits. However, there is noprotection for energy injected between the load and its con-trolling thyristor. Placing the suppressor directly acrosseach thyristor positively limits maximum voltage and snub-
ber discharge dIdt
.
EXAMPLES OF SNUBBER APPLICATIONS
In Figure 35, TRIACs switch a 3 phase motor on and offand reverse its rotation. Each TRIAC pair functions as aSPDT switch. The turn-on of one TRIAC applies the differ-ential voltage between line phases across the blockingdevice without the benefit of the motor impedance toconstrain the rate of voltage rise. The inductors are added to
prevent static dVdt
firing and a line-to-line short.
AN1048/D
http://onsemi.com16
Figure 6.35. 3 Phase Reversing Motor
MOC3081
SNUBBERALL MOV’S ARE 275VRMSALL TRIACS AREMAC218A10FP
0.15µF
22 Ω2 W
WIREWOUND
43
4
6
G1
2
91
1/3 HP208 V
3 PHASE
100 µH
REV
φ1
91
G
12
300
6
FWD
4
SNUBBER
N
φ2
φ3
MOC3081
91
G
12
300
64
SNUBBER
MOC3081
91
G
12
300
64
SNUBBER
MOC3081
91
G
12
300
46
SNUBBER
REV
FWD
100 µHMOC3081
SNU
BBER
AN1048/D
http://onsemi.com17
Figure 36 shows a split phase capacitor-run motor withreversing accomplished by switching the capacitor in serieswith one or the other winding. The forward and reverseTRIACs function as a SPDT switch. Reversing the motorapplies the voltage on the capacitor abruptly across theblocking thyristor. Again, the inductor L is added to prevent
dVdt
s firing of the blocking TRIAC. If turn-on occurs, the
forward and reverse TRIACs short the capacitors (Cs)resulting in damage to them. It is wise to add the resistor RSto limit the discharge current.
Figure 6.36. Split Phase Reversing Motor
5.6
3.75330 V
MOTOR1/70 HP0.26 A
2N6073
115
500 µH
LS
REV
46 V/µsMAX
FWD
0.191
CS
0.1
RS
91
Figure 37 shows a “ tap changer.” This circuit allows theoperation of switching power supplies from a 120 or 240vac line. When the TRIAC is on, the circuit functions as aconventional voltage doubler with diodes D1 and D2 con-ducting on alternate half-cycles. In this mode of operation,
inrush current and dIdt
are hazards to TRIAC reliability.
Series impedance is necessary to prevent damage to theTRIAC.
The TRIAC is off when the circuit is not doubling. In thisstate, the TRIAC sees the difference between the line volt-age and the voltage at the intersection of C1 and C2. Tran-
sients on the line cause dVdt
s firing of the TRIAC. High
inrush current, dIdt
, and overvoltage damage to the filter
capacitor are possibilities. Prevention requires the additionof a RC snubber across the TRIAC and an inductor in serieswith the line.
THYRISTOR TYPES
Sensitive gate thyristors are easy to turn-on because oftheir low trigger current requirements. However, they have
less dVdt
capability than similar non-sensitive devices. A
non-sensitive thyristor should be used for high dVdt
.
TRIAC commutating dVdt
ratings are 5 to 20 times less
than static dVdt
ratings.
Figure 6.37. Tap Changer For Dual VoltageSwitching Power Supply
–C1
+
RL
0 G
CSRS
120 V
240 V
SNUBBER INDUCTOR
120 VACOR
240 VAC
D1D2
D4D3
–C2
+
Phase controllable optocouplers have lower dVdt
ratings
than zero crossing optocouplers and power TRIACs. Theseshould be used when a dc voltage component is present, orto prevent turn-on delay.
Zero crossing optocouplers have more dVdt
capability than
power thyristors; and they should be used in place of phasecontrollable devices in static switching applications.
APPENDIX A
MEASURING dVdt
s
Figure 38 shows a test circuit for measuring the static dVdt
of power thyristors. A 1000 volt FET switch insures that thevoltage across the device under test (D.U.T.) rises rapidlyfrom zero. A differential preamp allows the use of aN-channel device while keeping the storage scope chassisat ground for safety purposes. The rate of voltage rise isadjusted by a variable RC time constant. The chargingresistance is low to avoid waveform distortion because ofthe thyristor’s self-capacitance but is large enough to pre-
vent damage to the D.U.T. from turn-on dIdt
. Mounting the
miniature range switches, capacitors, and G-K networkclose to the device under test reduces stray inductance andallows testing at more than 10 kV/µs.
AN1048/D
http://onsemi.com18
Figure 6.38. Circuit For Static Measurement of Power ThyristorsdVdt
X100 PROBE
X100 PROBE
DIFFERENTIALPREAMP
MOUNT DUT ONTEMPERATURE CONTROLLEDCµ PLATE
DUT
2
1G
RGK
2 W20 k
VDRM/VRRM SELECT 2 W
27
0.33 1000 V 0.0471000 V
100010 WATT
WIREWOUND
10001/4 W
562 W
VERNIER
822 W
1002 W
470 pF
0.001
0.005
0.01
0.047
0.1
0.47
1.2 MEG2 W EACH1 MEG
POWER2 W
TEST
MTP1N100
ALL COMPONENTS ARE NON-INDUCTIVE UNLESS OTHERWISE SHOWN
0–1000 V10 mA
1N967A18 V
1N914
f = 10 HzPW = 100 µs50 Ω PULSEGENERATOR
20 V
dVdt
APPENDIX B
MEASURING dVdt
c
A test fixture to measure commutating dVdt
is shown in
Figure 39. It is a capacitor discharge circuit with the loadseries resonant. The single pulse test aids temperature con-trol and allows the use of lower power components. Thelimited energy in the load capacitor reduces burn and shockhazards. The conventional load and snubber circuit pro-vides recovery and damping behaviors like those in theapplication.
The voltage across the load capacitor triggers the D.U.T.It terminates the gate current when the load capacitor volt-age crosses zero and the TRIAC current is at its peak.
Each VDRM, ITM combination requires different compo-nents. Calculate their values using the equations given inFigure 39.
Commercial chokes simplify the construction of the nec-essary inductors. Their inductance should be adjusted byincreasing the air gap in the core. Removal of the magneticpole piece reduces inductance by 4 to 6 but extends the cur-rent without saturation.
The load capacitor consists of a parallel bank of 1500Vdc non-polar units, with individual bleeders mounted ateach capacitor for safety purposes.
An optional adjustable voltage clamp prevents TRIACbreakdown.
To measure dVdt
c, synchronize the storage scope on the
current waveform and verify the proper current amplitudeand period. Increase the initial voltage on the capacitor tocompensate for losses within the coil if necessary. Adjustthe snubber until the device fails to turn off after the firsthalf-cycle. Inspect the rate of voltage rise at the fastestpassing condition.
AN1048/D
http://onsemi.com19
–
+
–
+
2 W51+ 5CS
2N3904
0.1
2.2 k1/2SYNC
TRIACUNDERTEST
562 WATT
CASECONTROLLED
HEATSINK
0.1
2N3906
– 5 G1
2
PEARSON301 X
2N3904
1/2 W120
2N3906
1201/2 W
2N3906
2N3904RS
1/2 W
– +
0.22270 k 1N5343
7.5 V
0.22Q1Q3
2N3906
2N3904
1/2 W360
1 k
– 5 + 5
NON-INDUCTIVERESISTOR DECADE
0–10 k, 1 Ω STEP
2 W51 k
51 k2 W
HG = W AT LOW LD10-1000-1000
+ CLAMP
MR760
– CLAMP
62 µF1 kV
LL
6.2 MEG 2W
150 k
910 k2 W
2 W
910 k
RL
Q3 Q1
70 mA
1.5 kV
TRIAD C30X50 H, 3500 Ω
2 W51
6.2 MEG 2W
360
1 k
270 k
2N39042N3906
Q3 Q1
0-1
kV 2
0 m
A
C
(NO
N-P
OLA
R)
L
MR
760
MR
760
2.2
M2.
2 M
2.2
M, 2
W
2.2
M, 2
W2.
2 M
2.2
M
0.01
Figure 6.39. Test Circuit For Power TRIACsdVdt
c
µ
CL IPK
W0 VCi
Ip T
2 VCiLL
VCiW0 IPK
T2
4 2 CLW0
I
LLdIdtc 6f IPK 106
As
dVdt
CAP
ACIT
OR
DEC
ADE
1–10
F
, 0.0
1–1
F,
100
pF–
0.0
1
Fµ
µ
0.01
AN1048/D
http://onsemi.com20
APPENDIX CdVdt
DERIVATIONS
DEFINITIONS
1.0 RT RL RS Total Resistance
1.1 M RSRT
Snubber Divider Ratio
1.2 0 1L CS Undamped Natural Frequency
Damped Natural Frequency
1.3 RT2 L
Wave Decrement Factor
1.4 χ2 12 LI2
12 CV2
Initial Energy In InductorFinal Energy In Capacitor
1.5 χ IE
LC Initial Current Factor
1.6 ρ RT2
CL
0 Damping Factor
1.7 V0L E RS I Initial Voltage drop at t 0
across the load
1.8 ICS
–E RL
L
dVdt
0 Initial instantaneous dV
dtat t 0, ignoring
any initial instantaneous voltage step att 0 because of IRRM
1.9 dVdt
0 VOL
RTL . For all damping conditions
2.0 When I 0, dVdt
0
E RSL
dVdt
max Maximum instantaneous dV
dt
tmax Time of maximum instantaneous dVdt
tpeak Time of maximum instantaneous peakvoltage across thyristor
Average dVdt
VPK tPK Slope of the secant line
from t 0 through VPKVPK Maximum instantaneous voltage across the
thyristor.
CONSTANTS (depending on the damping factor):
2.1 No Damping (ρ 0) 0RT ρ 0
2.2 Underdamped (0 ρ 1)
02 2 0 1 ρ2
2.3 Critical Damped (ρ 1)
0, 0, R 2 LC , C 2
RT
2.4 Overdamped (ρ 1)
2 02 0 ρ2 1
Laplace transforms for the current and voltage in Figure 40are:
3.0 i(S)ELSI
S2SRTL 1
LC
; e ES
S V0L
S2RTL
S 1LC
INITIAL CONDITIONSI IRRMVCS 0
Figure 6.40. Equivalent Circuit for Load and Snubber
t = 0I
RL L
CS
RSe
The inverse laplace transform for each of the conditionsgives:
UNDERDAMPED (Typical Snubber Design)
4.0 e E V0LCos (t)
sin (t)e t
sin (t) et
4.1 dedt
V0L2 Cos (t)
(2–2)
sin (t)e–t
Cos (t)–
sin (t) e–t
4.2 tPK 1 tan1
2 V0L
V0L22
When M 0, RS 0, I 0 : tPK
AN1048/D
http://onsemi.com21
4.3 VPK E
0 tPK 0
2 V0L2 2 V0L
When I 0, RL 0, M 1:
4.4VPK
E (1 e tPK)
Average dVdt
VPKtPK
4.5 tmax 1ATN (2 V0L (2 32))
V0L(3 32) (2 2)
4.6 dVdt
max V0L
2022 V0L 2 e– tmax
NO DAMPING
5.0 e E (1 Cos (0t)) IC 0
sin (0t)
5.1 dedt
E 0 sin (0t) IC
Cos (0t)
5.2 dVdt
0 I
C 0 when I 0
5.3 tPK tan1 I
CE 0
0
5.4 VPK E E2 I2
02C2
5.5 dVdtAVG
VPKtPK
5.6 tmax 10tan10 EC
I 1
02
when I 0
5.7 dVdt
max I
CE202 C2I2 0E when I0
CRITICAL DAMPING
6.0 e E V0L(1 t)et tet
6.1 dedt
VOL (2 t) (1 t) et
6.2 tPK
2
2 V0L
V0L
6.3 VPK E – V0L (1– tPK)– tPK e– tPK
6.4 Average dVdt
VPKtPK
When I 0, RS 0, M 0
e(t) rises asymptotically to E. tPK and average dVdt
do not exist.
6.5 tmax 3V0L 2
2V0L
When I 0, tmax 0
ForRSRT
34,
then dVdt max
dVdt
0
6.6 dVdt
max
V0L (2– tmax) (1– tmax) e– tmax
APPENDIX D
SNUBBER DISCHARGE dIdt
DERIVATIONS
OVERDAMPED
1.0 i VCS LS
–t sinh (t)
1.1 iPK VCS
CSLS e– tPK
1.2 tPK 1 tanh –1
CRITICAL DAMPED
2.0 i VCSLS
te–t
2.1 iPK 0.736VCSRS
2.2 tPK 1
AN1048/D
http://onsemi.com22
UNDERDAMPED
3.0 i VCS LS
e–t sin (t)
3.1 iPK VCS
CSLS
e– tPK
3.2 tPK 1
tan –1
Figure 6.41. Equivalent Circuit for Snubber Discharge
LSRS
CSVCS i
t = 0
INITIAL CONDITIONS :i 0, VCS INITIAL VOLTAGE
NO DAMPING
4.0 i VCS LS
sin (t)
4.1 iPK VCS
CSLS
4.2 tPK
2
BIBLIOGRAPHY
Bird, B. M. and K. G. King. An Introduction To PowerElectronics. John Wiley & Sons, 1983, pp. 250–281.
Blicher, Adolph. Thyristor Physics. Springer-Verlag, 1976.
Gempe, Horst. “Applications of Zero Voltage CrossingOptically Isolated TRIAC Drivers,” AN982, Motorola Inc.,1987.
“Guide for Surge Withstand Capability (SWC) Tests,”ANSI 337.90A-1974, IEEE Std 472–1974.
“IEEE Guide for Surge Voltages in Low-Voltage AC PowerCircuits,” ANSI/IEEE C62.41-1980, IEEE Std 587–1980.
Ikeda, Shigeru and Tsuneo Araki. “The dIdt
Capability of
Thyristors,” Proceedings of the IEEE, Vol. 53, No. 8,August 1967.
Kervin, Doug. “The MOC3011 and MOC3021,” EB-101,Motorola Inc., 1982.
McMurray, William. “Optimum Snubbers For PowerSemiconductors,” IEEE Transactions On Industry Applica-tions, Vol. IA-8, September/October 1972.
Rice, L. R. “Why R-C Networks And Which One For YourConverter,” Westinghouse Tech Tips 5-2.
“Saturable Reactor For Increasing Turn-On SwitchingCapability,” SCR Manual Sixth Edition, General Electric,1979.
Zell, H. P. “Design Chart For Capacitor-Discharge PulseCircuits,” EDN Magazine, June 10, 1968.
AN1048/D
http://onsemi.com23
Notes
AN1048/D
http://onsemi.com24
USA/EUROPE Literature Fulfillment :Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone : 303–675–2175 or 800–344–3860 Toll Free USA/CanadaFax: 303–675–2176 or 800–344–3867 Toll Free USA/CanadaEmail : ONlit@hibbertco.com
Fax Response Line *: 303–675–2167800–344–3810 Toll Free USA/Canada*To receive a Fax of our publications
N. America Technical Support : 800–282–9855 Toll Free USA/Canada
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATIONASIA/PACIFIC : LDC for ON Semiconductor – Asia SupportPhone : 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)Email : ONlit–asia@hibbertco.com
JAPAN : ON Semiconductor, Japan Customer Focus Center4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549Phone : 81–3–5487–8345Email : r14153@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local Sales Representative.
AN1048/D
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.