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SoC Challenges &Transaction Level Modeling
(TLM)Dr. Eng. Amr T. Abdel-Hamid
ELECT 1002
Spring 2008
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Table Of Contents
SoC Challenges
TLM Model Concepts
TLMs for different design domains
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SoC Challenges
Explosive Complexity: The smaller the better
Time-to-market the amount of time
required for conceiving an idea into a real product for sales Shorter times-to-market
Sky-rocketing Cost
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System Design Level
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Solutions
TLM Reuse of implementations (IP Design Reuse) System standards
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Classic Design Flow
SoftwareImplementation
System Level Design (Co-design Level)
System Integration
RTL Model
Gate Model
Layout
Behavioral Model(Spec.)
H/W DesignS/W Design
Algorithmic Design Architectural Design
Partitioning
Gate Synthesis
RTLImplementation
LayoutGeneration
VHDL/Verilog
Synthesis Tools
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System Description Models
Transistor levelHSpice, Schematic
Gate levelNetlist, PALASM, TEGAS
RT LevelHDLs
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Modern Design Flow
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Levels of Abstraction
Three levels of abstraction:1. Functional level
• Executable Specification• Un-Timed
2. Architecture level• Analyze SoC architecture• Early SW development• Estimated timing
3. Micro-Architecture level• Pin level• RTL/Behavioral HW design• Exact Timing
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Transaction Level Modeling - TLM
Transaction is the exchange of data or an event between two component of a modeled and simulated system data can be anything from a word to a complex data structure event transaction models synchronization aspects that ensure correct
operation of the SoC The behavior of functional blocks can be separated from
communication The communication is described in terms of sending transactions
TLM only focus on mapping out data flow details, i.e. the type of data that flows and where it is
stored
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TLM – cont.RTL: • The bus is wires• Each device on the bus has a pin-accurate interface• Each device interface must implement the bus protocolTLM: • Bus model enforces the bus protocol• Each device communicates via transaction level API• Less code, fewer pins, fewer•events => much faster
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Basics of TLM
Module : structural entity, which contain processes, ports, channels, and other modules
Channel : implements one or more interfaces, and serves as a container for communication functionality
Port : object through which a module can access a channel’s interface.
Transaction : exchange of a data or an event between two components of a modeled and simulated system
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Basics of TLM
Hierarchical channels contain processes, ports, modules and channels, but primitive channels do not
Primitive & Hierarchical Channel
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TLM Advantages SW development delay
SW team can begin SW developing or testing stage much sooner
HW/SW communicationHW parts can communicate with SW parts in this common environment. Makes the SW debug easier.
Design space exploration
Designers can decide on its partitioning (module and HW/SW partitioning) in the early stages of the design.
Simulation speedThe number of events decreases
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TLM Abstraction Models
A. "Specification model" "Untimed functioal models"
B. "Component-assembly model" "Architecture model" "Timed functonal model"
C. "Bus-arbitration model" "Transaction model"
D. "Bus-functional model" "Communicatin model" "Behavior level model" E. "Cycle-accurate computation model"
F. "Implementation model" "Register transfer model"
Computation
Communication
A B
C
D F
Un-timed
Approximate- timed
Cycle- timed
Un-timed
Approximate- timed E
Cycle- timed
Time granularity for communication/computation objects can be classified into 3 basic categories.
Models B, C, D and E could be classified as TLMs.
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1. Specification model
2. PE*-assembly model or Component Assembly
3. Bus-arbitration model4. Time-accurate communication model 5. Cycle-accurate computation model
6. Implementation model
TLM Abstraction Models
* Processing elements
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v2 = v1 + b*b; v3= v1- b*b;
v1
v1 = a*a;
v2
v4 = v2 + v3;c = sequ(v4);
B1
B2
v3
B3
B4
B2B3
A: “Specification Model”
Objects- Computation
-Behaviors- Communication
-Variables
Composition
- Hierarchy
- Order
-Sequential
-Parallel
-Piped
-States
- Synchronization
-Notify/Wait
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B: “Component-Assembly Model”
v3
v3= v1- b*b;
B3
v4 = v2 + v3;c = sequ(v4);
B4
PE3
v2 = v1 + b*b;
B2
PE2
v1 = a*a;
B1
PE1
cv2
cv
12
cv11
Objects- Computation
- Proc
- IPs
- Memories- Communication
-Variable channels
Composition
- Hierarchy
- Order
-Sequential
-Parallel
-Piped
-States
- Synchronization
-Notify/Wait
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C: “Bus-Arbitration Model”
v2 = v1 + b*b;
B2
PE2
v1 = a*a;
B1
PE1
v3
v3= v1- b*b;
B3
v4 = v2 + v3;c = sequ(v4);
B4
PE3
cv12
cv11
cv2
PE4(Arbiter)
3
1 2
1. Master interface2. Slave interface3. Arbiter interface
Objects- Computation
- Proc
- IPs (Arbiters)
- Memories- Communication
- Abstract bus channels
Composition
- Hierarchy
- Order
-Sequential
-Parallel
-Piped
-States
- Synchronization
-Notify/Wait
Bus arbiter arbitrates bus conflict
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v2 = v1 + b*b;
B2
PE2
v1 = a*a;
B1
PE1
v3
v3= v1- b*b;
B3
v4 = v2 + v3;c = sequ(v4);
B4
PE3
PE4(Arbiter)
3
1 2
1: master i nterf ace2: sl ave i nterf ace3: arbi tor i nterf ace
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address[15:0]
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D: “Bus-Functional Model”
Objects- Computation
- Proc
- IPs (Arbiters)
- Memories- Communication
- Protocol bus channels
Composition
- Hierarchy
- Order
-Sequential
-Parallel
-Piped
-States
- Synchronization
-Notify/Wait
•Time/cycle accurate communication (time constraint) •Approximate timed computation •Protocol channel provides functions for all abstraction bus transaction
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E: “Cycle-Accurate Computation Model”
PE3
cv12
cv11
cv2
3
1 2
1. Master interface2. Slave interface3. Arbiter interface4. Wrapper
S0
S1
S2
S3
S4
PE4
S0
S1
S2
S3
4
4
PE2
PE1
MOV r1, 10MUL r1, r1, r1
....
...MLA r1, r2, r2, r1
....
4
4
Objects- Computation
- Proc
- IPs (Arbiters)
- Memories
- Wrappers- Communication
- Abstract bus channels
Composition
- Hierarchy
- Order
-Sequential
-Parallel
-Piped
-States
- Synchronization
-Notify/Wait
• Modeled at register-transfer level • PE are pin accurate and execute cycle-accurately• Wrappers convert data transfer from higher level of abstraction to lower level abstraction
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PE2PE1
PE3PE4
S0
S1
S2
S3
S4
MOV r1, 10MUL r1, r1, r1
....
...MLA r1, r2, r2, r1
....
S0
S1
S2
S3
MCNTRMADDRMDATA
interrupt
interrupt
interrupt
req req
F: “Implementation Model”
Objects- Computation
- Proc
- IPs (Arbiters)
- Memories- Communication
-Buses (wires)
Composition
- Hierarchy
- Order
-Sequential
-Parallel
-Piped
-States
- Synchronization
-Notify/Wait
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SOC Design Tasks1. PE assembly and model generation
Bus-arbitrationmodel
Specificationmodel
1
PE-assembly model
2
Time-accurateCommunication
model
3
Implementation model
4
Cycle-accurateComputation
model
5
6
7 8
SystemDesign
ComponentDesign
2. Communication exploration and bus-arbitration model generation
3. Protocol refinement and time-accurate communication model generation
4. RTL/ISS* synthesis
5. IP replacement
6. Interconnect network generation
7. Accurate communication feedback
8. Accurate computation feedback
* ISS : Instruction set simulator
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SOC Design Tasks
Computation
Communication
A B
C
D F
Un-timed
Approximate- timed
Cycle- timed
Un-timed
Approximate- timed E
Cycle- timed
1
2
3
4
5
6
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Characteristics of Different Abstraction Models
Models Communication time
Computation time
Communication scheme
PE interface
Specification model
no no variable (no PE)
Component-assembly model
no approximate variable channel abstract
Bus-arbitration model
approximate approximate abstract bus channel
abstract
Bus-functional model
time/cycle accurate
approximate protocol bus channel
abstract
Cycle-accurate computation
model
approximate cycle-accurate abstract bus channel
pin-accurate
Implementation model
cycle-accurate cycle-accurate bus (wire) pin-accurate
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ReferencesThe credit of these slides goes to: D. Gajski, L. Cai, “Transaction Level Modeling: An Overview”, Center for Embedded Computer Systems, University of California, Irvine, 2004. Z. Navabi, “The Role of SystemC in theEvolution of Hardware Design”, Worcester Polytechnic Institute. B. Vanthournout, “SoC design methodology Using SystemC”, Coware, 2003. F. Ghenassia, “Transaction Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems, Springer, 2005.
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