Post on 06-May-2015
transcript
INFLUENCE 2013National Conference on Mega Trends in Engineering
(August 16 & 17, 2013)
“Study of VLSI Design Methodologies and Limitations using CAD tools for CMOS Technology”
Presented By:
Ayoush Johari VVS Lavanya School of Interdisciplinary Science and Technology School of Interdisciplinary Science and Technology International Institute of Information Technology International Institute of Information Technology
Pune, India Pune, India
Rakeshwari PalDepartment of Electrical and Electronics Engineering
Trinity Institute of Technology and Research Bhopal, India
Tuesday 11 April 2023 VLSI Design Methodologies and Limitations using CAD Tools
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VLSI Technology and Design Drivers
Source: http://www.gdiamos.net
Less Power Consumption
Less Price/ More Economical
More or Less components per board/system
Less Price/ More Economical
Higher reliability
Improved Interconnects
More Compactness
High Speed of Operation
Lesser Manufacturing Costs
Area Utilization/compactness
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Why not Silicon Compiler ?
source : http://www.vlsicad.ucsd.edu/maryjanerwin/psu
Spec/Verilog/VHDL
Verification CAD developers
VLSI designers
Process people
Testing team
Circuit on Silicon
Synthesis
Routing
Placement
Ideal Scenario Reality
Silicon Compiler Design Methodology
Simple Tasks
No Human Interaction
Complex Procedures
Lots Of Human Interaction
Tuesday 11 April 2023 VLSI Design Methodologies and Limitations using CAD Tools
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View of IC Designer
Design parameters by which Design success is measured:
Performance Specifications
Size of Wafer, Die and overall manufacturing cost
Design time including engineering and time to tape out
Ease of Test pattern generation , verification and testability.
Design is a continuous tradeoff between namely 3 parameters namely Price, Power and performance.
Figure 1: Generalized View of a IC Designersource: http://ic.engin.brown.edu/classes/EN1600S08/projects.html
Proposed Architecture
Algorithm
Process Technology
VLSI CAD
Tools
Chip for fabrication
Tuesday 11 April 2023 VLSI Design Methodologies and Limitations using CAD Tools
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VLSI Design Methodologies
Full Custom Design
Semi Custom Design
Gate Array Design
Standard Cell Design
FPGA Based Design
PLA Based Control
Hardwired Control
CPLD Based Design
RT-Level Synthesis
HDL Based Design Methodology
IP Cores, SOCs, DSPs, MEMs
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VLSI Design Methodologies
Systematic design methods or the design methodologies are necessary for successfully designing complex digital hardware.
Our design methods usually differ by the number of abstraction levels and the complexities involved.
A Gated array, standard cell design, full custom design, CPLDs FPGAs are some of the design methodologies well known.
Figure 2: Abstraction hierarchies in VLSI Design Methods
More Levels of abstraction
Less Levels of abstraction
Synthesis Analysis
System Specifications
Final Chip
Manual Automation
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Design Flow Evolution
Past- 250-180nm Present- 90-45nm Future 22.5-10nm
Source http://www.vlsicad.ucsd.edu/
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VLSI Design Complexities
VLSI Design is a process of converting an to a Idea Chip.
source: LSI Logic LEA300K ;(0.6 mm CMOS)www.lsi.com
Problem Domain complexity
Development Process complexity
Choice Domain complexity
Testing related complexity
Packaging related complexity
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VLSI CAD Tools Current systems are very complex.
Design abstraction and decomposition is done to manage complexities.
Tools automate the process of converting our design from
one abstraction level to another.
Design automation tools improve productivity.
The First IC based microprocessor was built using manual design.source : http://ic.engin.brown.edu/classes/lecture6
Figure 3: Layout of 4004 microprocessor invented by Intel Engineers Federico Faggin, Ted Hoff, and Stanley Mazor
To get the chip to the market fast CAD tools are indeed needed.
Tuesday 11 April 2023 10
Classification and Comparison of VLSI CAD Tools
S.No. CAD ToolOpen
Source/ Licensed
Type Function
1 Cadence EDA LicensedAnalog and Mixed signal
Complete CAD Flow
2 Mentor Graphics EDA
LicensedAnalog and Mixed signal
Complete CAD Flow
3 Synopsys EDA LicensedAnalog and Mixed signal
Complete CAD Flow
4 Tanner EDA LicensedAnalog and Mixed signal
Complete CAD Flow
5 Alliance Open Source
Mixed Signal
Logic to Layout
6 Electric CAD Open Source
Mixed Signal
Logic to Layout
7 Magic Open Source
Mixed Signal
Circuit Layout
8 SystemCOpen Source
ElectronicSystem Level
Library for Digital Design
9 myHDL Open Source
Electronic System Level
Hardware Description
language
Table : Comparative study of various open source and licensed set of VLSI EDA tools.[18]
1. High Level Synthesis(HDLs)
3. Circuit Optimization Tools
2. Logic Synthesis Tools
3.1 Transistor Sizing Tools
3.2 Process Variation Tools
3.3 Stastical Design Tools
4. Layout Tools
4.1 Floorplanning
4.2 Place and Route
4.3 Module Generation
4.4 Automatic Cell Placement Routing
5. Layout Extraction Tools
6. Simulation (Spice for circuit level Simulation)
7. Layout Schematic Verification Tools
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VLSI CAD Tools (Contd..)
Front End Tools
VLSI CAD Tools
Editors
Design Entry
Back End Tools
Simulation
Synthesis
Timing Analysis
DFT Insertion
Test Generation
Place & Route
Floor Planning
Extraction
LVS, LVL
ERC,DRC
Pattern Generators
Format Converters
Pattern Generators
DesignCapture Tools
Synthesis Tools
VHDL/Verilog
Editors
System Verilog / SystemC, Vera
State Charts
RTL Synthesis
Behavioral Synthesis
FPGA Synthesis
FSM Capture
Logic Synthesis
Physical Synthesis
Module/Cells
DSP Synthesis
Tuesday 11 April 2023 VLSI Design Methodologies and Limitations using CAD Tools
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VLSI CAD Tools (Contd..)
Analysis Tools
VLSI CAD Tools
Netlist Compare
DRC,ERC
Testing Related Tools
Ratio Checker
Fan-in/ Fan-Out Checker
ICE/ Hardware
Timing Verifier
Formal Verifiers
Checkers Verifiers
Power Checker
DFT
ATPG
Design and Analysis
Tuesday 11 April 2023 VLSI Design Methodologies and Limitations using CAD Tools 13
compilation/synthesis
VHDL / Verilog / SystemC
device layout find wire routesmask layout patterns
design schematics
source :http://ic.engin.brown.edu/classes/lecture1
• Design development is facilitated using Computer-Aided Design (CAD) tools
Tuesday 11 April 2023 VLSI Design Methodologies and Limitations using CAD Tools 14
tape out
mask writermasks
wafer
printing
die
dice
mask layout patterns
test and packaging
chip
source: http://ic.engin.brown.edu/classes/lecture1
• Design development is facilitated using Computer-Aided Design (CAD) tools
Tuesday 11 April 2023 VLSI Design Methodologies and Limitations using CAD Tools 15
Simple VLSI CAD Tool Chain
if SEL == “00“ then Y = A;elseif SEL == “01“ then Y = B;elseif SEL == “10“ then Y = C;else Y = D;end if;
AB
C
D2:1 MUX
2:1 MUX2:1 MUX
SEL == 00
SEL == 01
SEL == 10
Y
Source: http://ic.engin.brown.edu/classes
Hardware Description Languages
Specifications
Layout and Routing
Synthesis
IC Layout /Area Cell Library
Schematic Entry
Simulation
Verification and timing/ power results
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VLSI CAD Tool Vendors
[26]
[27]
[28]
[29]
[30]
[32]
[31]
Tuesday 11 April 2023 VLSI Design Methodologies and Limitations using CAD Tools
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Typical VLSI Design Flows
Source: http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/nptel-cad1-01.pdf
Tuesday 11 April 2023 VLSI Design Methodologies and Limitations using CAD Tools
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Source: http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/nptel-cad1-01.pdf
Tuesday 11 April 2023 VLSI Design Methodologies and Limitations using CAD Tools
Design Representation Levels and Associated Formats
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Design Behavior
Architecture
Micro -Architecture
Software and Operating System
EDA Servers and Linux,
RTOS
Digital Hardware(Register Transfer)
Gate Level Netlist(Logic Gates & Latches)
Layout and Masks(Fabrication Patterns)
SystemC, VHDL, VerilogISA,C,C++
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VLSI Design Complexities vs CAD Tools
Design Challenges and Priorities
Algorithms and
CAD Tools
Methodology and
EDA Flows
Process Technology and Limitations
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Limitations and Challenges to Overcome
Design investment increasing for a given
application
Designer’s Aim – Transfer Design description in one domain into a fully equivalent design descriptions in respective other domains.
Guiding Design Organization Principles
Design Options available
to CMOS IC Designers.
Fast Prototyping
Low Volume
Custom Design
Labor Intensive
High Volume
Programmable Logic
Programmable Logic Structures
Programmable Interconnects
Mask Programmable Gate Arrays
Standard Cell Design
Mixed Standard Cell and Custom Cell
Full Custom mask Design
Design Time and Cost Decreasing
(for given application)
Performance Increasing,
Die Area Decreasing ,Power Dissipation
increasing
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Conclusion
VLSI Design – complexities increases as the time progresses .
Design Methodologies and CAD tools are integral parts in VLSI Design and go hand in hand and they evolve based on designer’s needs.
CAD Tools allows the freedom to VLSI Designers to focus on creativity with respect to process technology.
The development in the design tools, collaborative design methods, the role of human factors and integration factors in the design technology marks the outline of various design methodologies.
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References [1] Randal E. Bryant, Kwang-TingCheng , Andrew B Kahang, Kurt Kreutzer, Wojciech Maly,Richard Newton, Lawerance Pileggi, Jan M Rabaey, Alberto Saniovanni- Vincentelli, “Limitations and Challenges of CAD technology for CMOS VLSI” . [2] Catherine H. Gebotys, Mohamed I. Elmasry,“Vlsi Design Synthesis and Testability”. [3]A.H. Farrahi, D.J. Hathaway, M.Wang and M.Sarrafzadeh, “Quality OF EDA CAD Tools: Definitions, Metrices and Directions”.
[4] Anantha Chandrakasan, Isabel Yang, Carlin Veiri, Dimitri Antoniadis, “Design Considerations and tools for Low voltage Digital system Design” [5] Mike Spreitzer “Comparing Structurally different views of a VLSI Design” [6] Catherine H. Gebotys, Mohamed I. Elmasry, “VLSI Design Synthesis and Testibility” [7] T.S. Cheung, K.Asada, K.L. Yip, H. Wong, Y.C. Cheng, “Low Power CMOS Design Methodologies with reduced voltage swing ” [8] K.A. Sumithra Devi, “Algorithms for CAD tools VLSI design” [9] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits” , A Design perspective Second edition
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10] Dr. Nicos Bilalis, “Computer Aided Design CAD”, January 2000 edition [11] Course: “Trends in VLSI Design: Methodologies and CAD tools”. Presenter Raj Singh. IC Design group,CEERI,Pilani-333031 [12] P.van der Wolf. “CAD Frameworks: Principle and Architecture” Kluwer Academic Publishers,236pp [13] K.Chaudhary, A.Onawaza, and E.S. Kuh. “Algorithms for Performance Enhancement and Crosstalk Reduction”. In International conference on Computer Aided Design, pages 697-702,1993. [14] C.Chen and M.Sarrafzadeh. “Provably Good Algorithm for low power consumption and supply voltages” ”. In International conference on Computer Aided Design, pages 76-79,1999. [15] H.M. Chen, H.Zhou, F.Y.Young, D.F. Wong, H.H. Yang, and N.Sherwani. “Integrated Floorplanning and Interconnect Planning”. ”. In International conference on Computer Aided Design, pages 354-357,November 1999. [16]http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/index.php [17] https://www.coursera.org/course/vlsicad/ [18]http://www.vlsiacademy.org/open-source-cad-tools.html
References ( Contd..)
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[19] Static Free Software. July 2004 http://www.staticfreesoft.com [20] Cadence OrCAD Solutions, February2010.
http://www.cadence.com/products/orcad
[21] Alliance. http://www.asim.lip6.fr/recheche/alliance
[22] Magic VLSI Resource. http://www.opencircuitdesign.com/magic
[23]Custom IC Design, http://www.cadence.com/products/cic
[24] BSIM3- Introduction, www.device.eees.berkeley.edu/~bsim3
[25] IRSIM, http//:opencircuitdesign.com/irsim
[26]http://www.cadence.com/_layouts/images/imgbin/header/cadence_logo2.gif
[27] http://www.synopsys.com/Style%20Library/homeimages/snps_logo.gif
[28] http://www.mosis.com/graphics2/block_logo_2.jpg
[29] http://www.tanner.com/images/eda_icon.jpg
[30] http://www.magma-da.com/pics/common/logo.gif
[31] http://www.shellytech.com/Images/Logos/MentorGraphicsLogo.jpg
[32] http://www.rulabinsky.com/steve/plug.gif
References ( Contd..)
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Thank You...