Sub-threshold Sense Amplifier (SA) Compensation Using Auto-zeroing Circuitry

transcript

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01/21/2014

Peter BeshayDepartment of Electrical EngineeringUniversity of Virginia, Charlottesville

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Outline Motivation Introduction DAZ Circuit 16kB SRAM Chip Measurements Conclusion

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Motivation

Source: IdeaConnection.com

Source: groups.csail.edu/

Source: Implantable-device.com

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Motivation

SRAM are used in implantable devices Contribute significantly to the total

System-on-chip (SOC) power consumption

SRAM Power Consumption (1)

(1) N. Verma, Phd thesis

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Motivation

Minimum Energy occurs in sub-threshold [1]

Eactive = CVDD2

Etotal/operation minimized in sub-VT

Main LimitationsProcess Variations effect, Slow Speed

VDD (V)

(1) N. Verma, Phd thesisEnergy Consumption vs. VDD (1)

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Motivation

Work Focus

Minimizing the energy of the read operation of sub-threshold SRAMs.

Sense Amplifier are utilized during the read operation of the SRAMs.

The intrinsic offset voltage of the SAs causes increased read energy and degraded performance of the SRAM read operation [2].

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Outline Introduction DAZ Circuit 16kB SRAM Chip Measurements Conclusion

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Sense Amplifier

=1 if =0 Otherwise

𝑉 2

𝑨𝒏𝒂𝒍𝒐𝒈𝒚𝑉 1

𝑉 𝑜𝑢𝑡

Enable

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SA Offset Voltage

=1 if =0 Otherwise

𝑉 2

𝐕𝐨𝐟𝐟𝐬𝐞𝐭

𝑨𝒏𝒂𝒍𝒐𝒈𝒚

=1 if =0 Otherwise

𝑉 1

𝑉 2

𝑉 1

𝑉 𝑜𝑢𝑡

Enable

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=1 if =0 Otherwise

𝑉 2

𝑨𝒏𝒂𝒍𝒐𝒈𝒚

=1 if =0 Otherwise

𝑉 1

𝑉 2

𝑉 1

𝑉 𝑜𝑢𝑡

Enable

𝐎𝐜𝐜𝐮𝐫𝐞𝐧𝐜𝐞𝐬

SA Offset Voltage

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6T Bitcell

......…

6T Bitcell 6T Bitcell 6T Bitcell

6T SRAM Read Operation

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6T Bitcell

......…

6T Bitcell 6T Bitcell 6T Bitcell

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6T Bitcell

......…

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6T Bitcell

......…

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6T Bitcell

......…

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6T Bitcell

......…

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6T Bitcell

......…

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6T Bitcell

......…

B L ,BL

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6T Bitcell

......…

B L ,BL

∆V >

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6T Bitcell

......…

B L ,BL

∆V >

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6T Bitcell

......…

B L ,BL

∆V >

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6T Bitcell

......…

B L ,BL

Pre-charge

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6T Bitcell

......…

B L ,BL

Pre-charge

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6T Bitcell

......…

B L ,BL

Pre-charge

𝑬𝒑𝒓𝒆𝒄𝒉𝒂𝒓𝒈𝒆=𝐂𝐁𝐋𝐕𝐃𝐃∆𝐕6T SRAM Read Operation

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PMOS-input Latch SA

𝐄𝐍BL 𝐁𝐋

𝐄𝐍

OUT 𝐎𝐔𝐓

𝐄𝐍Cross coupled inverter to latch the output

Sense the input voltage

Enable the SA

Precharge the output to VDD 25

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𝐄𝐍BL=0.45V 𝐁𝐋=𝟎 .𝟒𝐕

𝐄𝐍

OUT 𝐎𝐔𝐓

𝐄𝐍

PMOS-input Latch SA

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𝐄𝐍BL=0.45V 𝐁𝐋=𝟎 .𝟒𝐕

𝐄𝐍

OUT 𝐎𝐔𝐓

𝐄𝐍

PMOS-input Latch SA

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Offset Voltage

𝐄𝐍BL=0.5 =0.5

𝐄𝐍

OUT 𝐎𝐔𝐓

𝐄𝐍

𝐈𝐃=𝐈𝟎𝐖𝐋 𝐞

𝐕𝐆𝐒−𝐕𝐭𝐡

𝐧𝐕𝐭𝐡𝐞𝐫𝐦𝐚𝐥 (𝟏−𝐞𝐕𝐃𝐒

𝐕 𝐭𝐡𝐞𝐫𝐦𝐚𝐥 )

∆ mismatch causes the currents to Be different, for zero differential input(BL=)

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Digital Auto-zeroing (DAZ)• We propose a digital auto-zeroing (DAZ) scheme

inspired by analog amplifier offset correction.

• The main advantages of the approach are• Near-zero offset after cancellation.• Suitable for sub-threshold operation due to the

repeated offset compensation phase.

• Several attempts have been made before to tackle the problem including:• Redundancy [3]

• Transistor upsizing [4]

• Digitally controlled compensation [5]

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Auto-zeroing in analog amplifiers• Amplification is done

in two phases

• Φ1: Sample the offset on a capacitor

• Φ2: Subtract the offset from the input signal

(2) K Kang et al, “Dynamic Offset Cancellation Technique” cse.psu.edu/~chip/course/analog/insoo/S04AmpOffset.ppt

Dynamic Offset Cancellation (2)

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DAZ Scheme

• Phase1 (ENR1)A zero differential input is applied to the sense amp.

• Phase2 (ENO)The SA resolves based on its intrinsic offset.

𝑉 𝑜𝑢𝑡

𝑇𝑢𝑛𝑒 h𝑡 𝑒𝑆𝐴

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DAZ Scheme

• Phase3 (ENR2)The differential input is applied to the sense amp.

• Phase4 (ENI)The SA resolves based on the differential input.

𝑉 𝑜𝑢𝑡

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DAZ Circuit

𝐄𝐍

𝐁𝐋

𝐄𝐍

OUT 𝐎𝐔𝐓

𝐄𝐍

• DAZ circuit applied to a latch-based sense amp with PMOS inputs

• DAZ circuit uses a split-phase clock and charge pump (CP) feedback circuit for repetitive compensation.

Charge Pump

𝐂𝐩

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DAZ Circuit

𝐄𝐍

𝐁𝐋

𝐄𝐍

OUT 𝐎𝐔𝐓

𝐄𝐍

Charge Pump

𝐂𝐩

• Transistors MC1 and MC2 control the drive strength of the right side of the SA.

• The CP controls the drive current in both MC1 and MC2 to equalize the strength of the SA right and left sides.

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DAZ Circuit

𝐄𝐍

𝐁𝐋

𝐄𝐍

OUT 𝐎𝐔𝐓

𝐄𝐍

𝐄𝐍𝐈M11

𝐄𝐍𝐑𝟐

CpCharge Pump

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Phase 1

𝐄𝐍

𝐁𝐋

𝐄𝐍

OUT 𝐎𝐔𝐓

𝐄𝐍

𝐄𝐍𝐈M11

𝐄𝐍𝐑𝟐 M12

ER1: A zero differential input is applied to the sense amp.

Charge Pump

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Phase 2

𝐄𝐍

𝐁𝐋

𝐄𝐍

OUT 𝐎𝐔𝐓

𝐄𝐍

𝐄𝐍𝐈M11

ENO: The SA resolves based on its intrinsic offset.

Charge Pump

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Phase 3

𝐄𝐍

𝐁𝐋

𝐄𝐍

OUT 𝐎𝐔𝐓

𝐄𝐍

𝐄𝐍𝐈M11

ER2: The differential input is applied to the sense amp.

Charge Pump

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Phase 4

𝐄𝐍

𝐁𝐋

𝐄𝐍

OUT 𝐎𝐔𝐓

𝐄𝐍

𝐄𝐍𝐈M11

ENI: The SA resolves based on the differential input.

Charge Pump

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Precision• The precision of the scheme depends on the accuracy

of setting the voltage on the output capacitor (Cp).

Settling Time= 60us

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Offset Tuning • Accuracy (offset voltage) vs. settling time trade-off

through Cp tuning.

0 2 4 6 8 10 12 14 16 18 205

Min Achieved Offset (mV)

Cp=0.74pF

Cp=0.43pF

Cp=0.24pF

Cp=0.14pFCp=0.13pF

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16kB SRAM Test-case• A 20mV DAZ SA is used in a 16kB SRAM with

1bank, 512 rows and 256 columns using commercial 45nm technology node [6].

• 10% reduction of the read energy• 24% reduction of the read delay

• 45nm technology test chip. • One regular SA array for benchmarking• DAZ SA array with Cp=32fF.

• DAZ circuit limits the absolute value of the maximum offset to 50 mV and provided 80% improvement in σ [6].

Chip Measurements

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Limitation• Area overhead (major concern in SRAM designs)

• 2.5X for 50mV offset compensation• Can be significant for small offsets

• Energy overhead of the continuous calibration (split phases, charge pump)• 3.5X the energy of a regular SA

• Sensitivity to split phase frequency.

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Conclusion• We proposed a circuit that is capable of improving sense-amp offset to

near zero, which is valuable for sub-threshold operation due to the repeated calibration phase.

• Applying the scheme on a 16 kB SRAM in 45nm technology node showed a reduction in the total energy and delay of 10% and 24% respectively.

• Measurements from a test chip fabricated in 45 nm technology showed the circuit’s ability to limit the absolute maximum value of the offset voltage to 50 mV using a 32fF output capacitance.

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References 1. B. H. Calhoun et al. "Sub-threshold circuit design with shrinking CMOS

devices." ISCAS 2009. 2. J. Ryan et al. “Minimizing Offset for Latching Voltage-Mode Sense Amplifiers

for Sub-threshold Operation” ISQED 2008. 3. N. Verma et al. “A 256 kb 65 nm 8T Sub-threshold SRAM Employing

Sense-Amplifier Redundancy” ISSCC 2008. 4. L. Pileggi et al. “Mismatch Analysis & Statistical Design” CICC 2008. 5. M. Bhargava et al. “Low-Overhead, Digital Offset Compensated, SRAM Sense

Amplifiers” CICC 2009. 6. P. Beshay et al. "A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-

Threshold Sense Amplifiers." JLPEA 2013

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Sub-threshold Sense Amplifier (SA) Compensation Using Auto-zeroing Circuitry

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