SuperCISC Compiler

C to VHDL compiler

Processor actors are bottleneck

Hardware acceleration

Ptolemy II Graphical Model CreationPtolemy II Graphical Model Creation

ACME Actor Generator

SoC Generation Tool FlowSoC Generation Tool Flow

2x2 Mesh Interconnect Network2x2 Mesh Interconnect Network

Xilinx Platform Studio SystemXilinx Platform Studio System

Processor Based Actors

Design complex components

Example: Switch arbiters

Describe functionality in C

Use Java Native Interface within Ptolemy II

Soft core processors run code on FPGA

2x2 Mesh Interconnect Network2x2 Mesh Interconnect Network

ACME actor library ACME actor library mirrors Ptolemy’s mirrors Ptolemy’s

Java libraryJava library

Xilinx library contains Xilinx library contains IP blocks and board IP blocks and board

descriptionsdescriptions

ACME

Graphical design entry

Uses Ptolemy II environment from UC Berkeley

Components called ‘actors’

Generate systems targeting FPGAs

System emulation

Rapid MPSoC prototyping

Processor and logic design

Logic Containing

VHDL Actors

Microblaze

Processor

Systems

Serial Port

for PC Communication

Actor Generator GUIActor Generator GUI

Extend Ptolemy II GUI Extend Ptolemy II GUI for graphical actor for graphical actor

creationcreation

Generated skeleton code for actorGenerated skeleton code for actor

ACME Actor GeneratorACME Actor Generator

Network

Switch

Processing Node

Rapid Prototyping and Emulation of Many-Core Chip Rapid Prototyping and Emulation of Many-Core Chip Multiprocessors with Integrated Hardware Multiprocessors with Integrated Hardware

AcceleratorsAccelerators

Colin J. IhrigColin J. Ihrig

University of PittsburghUniversity of Pittsburgh

Email: cji3@pitt.eduEmail: cji3@pitt.edu

Emulation AugmentationEmulation Augmentation

User specified latency and throughput circuitUser specified latency and throughput circuit

Processor / hardware synchronization Processor / hardware synchronization via a hardware barrier circuitvia a hardware barrier circuit

Three cycle throughput

One additional

latency cycle

Processors set / reset

barrier

Barrier clocks custom logic

Problem

Need to study new architectures

System design is time consuming

Software simulators do not scale well

Orders of magnitude slowdown

#pragma HWstartz = x + y;m = y << 3;n = m – y;if ( n < 0 ) n = 0;if ( q == 3 ) i = z + 5;else i = z – 2;j = n * i;#pragma HWend

SuperCISC CompilerSuperCISC Compiler

Emulation clock

Target vs. Host FPGA cycles

Decouples emulated system from FPGA

Tracked via hardware counters

Skeleton code generated for:

Ptolemy Java Actor

Java Native Interface C and Header files

ACME VHDL Actor

Actors automatically incorporated into ACME and Ptolemy II

Fast Simplex Link Bus

Connections

C to VHDL automation flow

Annotate C code with pragmas

Construct Super Dataflow Graph

Custom coprocessors in ACME