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Techniques and Algorithms for Techniques and Algorithms for Fault Grading of FPGA Fault Grading of FPGA
Interconnect Test ConfigurationsInterconnect Test Configurations
Techniques and Algorithms for Techniques and Algorithms for Fault Grading of FPGA Fault Grading of FPGA
Interconnect Test ConfigurationsInterconnect Test ConfigurationsMehdi Baradaran Tahoori and
Subhasish MitraIEEE Transactions on Computer-Aided Design of
Integrated Circuit and SystemsLaboratory of Reliable ComputingDepartment of Electrical EngineeringNational Tsing Hua UniversityHsinchu, Taiwan
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OutlineOutline Introduction FPGA model Interconnect fault model Previous work Testing for opens Testing for shorts Algorithms and implementation details Generalization for arbitrary logic Results Summary and Conclusion
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IntroductionIntroduction Almost 80% of transistors in an FPGA are
programmable switches and buffers
In order to test an FPGA, it needs test configurations and test vectors
The objective of this paper is to develop techniques to calculate fault coverage for a given set of test patterns
Switch- and gate-level fault simulation and fault-emulation technique are too time consuming
CLBs are configured as transparent logic
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FPGA modelFPGA model
CLB
LineSegments IOB
SwitchMatrix
Logicblock
Mux
N1 N2 N3
W1
W2
W3
E1
E2
E3
S1 S2 S3
SRAM
PIP
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Interconnect Fault ModelInterconnect Fault Model The stuck-at faults can be modeled as shorts to
VDD and ground lines
Fault list consists of All line segments and PIP stuck-opens faults The bridging fault of all connectable pair and
possible nonconnectable pair Interconnect Faults
Open Short Stuck-at
Line segmentopen
PIPstuck-open
Short Between
Line segments
PIPstuck-closed
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Previous Work (1)Previous Work (1) Fault emulation
The test configuration is modified to obtain a faulty configuration and then test vectors are applied
It is very time consuming Needs whole test configurations and test vectors
Unable to deal with shorts between lines which cannot be directly connected
1 00 1
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Previous Work (2)Previous Work (2) Fault simulation
Switch-level fault simulation Due to the very large number of transistors in the
FPGA, this method takes too much time Gate-level fault simulation
All interconnect and routing details are eliminated and only gate-to-gate connectivity information is preserved
&
&
+
1 1 1 1
1 1
&
& +
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Testing for Opens (1)Testing for Opens (1) Used and neighbor sets
Open detection in switch matrices Multiple independent paths Detectable and undetectable stuck-open faults
N1 N2 N3
W1
W2
W3
E1
E2
E3
S1 S2 S3Used set
Neighbor Set N1 N2 N3
W1
W2
W3
E1
E2
E3
S1 S2 S3
Circuit-->undetectable
ABCD
G
F E
H
L
FF
FF
open fault can be detected
open fault cannot be detected
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Testing for Opens (2)Testing for Opens (2) Modeling of opens in line segments
Extension to the Entire FPGA
ABC
D G
F
E H
I J
K
equivalent
LUT1 LUT2
F=XZ
Y
X
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Testing for Shorts (1)Testing for Shorts (1) Stuck-closed PIP detection in switch matrices
Detectable and undetectable stuck-closed faults
N1 N2 N3
W1
W2
W3
E1
E2
E3
S1 S2 S3
detectable
undetectable
W1
W3
E1
E3
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Testing for Shorts (2)Testing for Shorts (2) Short detection in the entire FPGA
The bridging fault between two routing resources, A and B, is detectable if A and B are a connectable pair via a PIP(P) P is in the neighbor set P stuck-closed fault is detectable A and B belong to different unrelated nets
Bridging faults in nonconnectable pairs Inductive fault analysis toolscandidate list
0
Bridging Fault
wire A
wire B
0
PIP Stuck-Closed
wire A
wire B
A
N1 N2 N3
W1
W2
W3
E1
E2
E3
S1 S2 S3
B
W1
W3
E1
E3
Net 1
Net 2
Logic Cell
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Flowchart for Fault Coverage Flowchart for Fault Coverage CalculationCalculation
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Algorithms and Implementation Algorithms and Implementation DetailsDetails
LUTs are configured as transparent logic
The test configurations are converted to the appropriate graph models
Switch matrices point are translated to nodes of graph
PIPs and line segments are converted to graph edges
Transparent logic
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Fault Coverage for OpensFault Coverage for Opens Undetectable open faulttest configuration which
form cycles in the graph model
Modified Depth First Search
ABCD
G
F E
H
L
FF
FF
open fault can be detected
open fault cannot be detected
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Fault Coverage for ShortsFault Coverage for Shorts Find-Connectables on the use set graph in order to
find all connected pairs in the graph DFS
For each neighbor set, check that if its ends are connected through a path in used set Floyd-Warshall algorithm
N1 N2 N3
W1
W2
W3
E1
E2
E3
S1 S2 S3
detectable
undetectable
W1
W3
E1
E3
Net 1
Net 2
Logic Cell
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Flowchart for The Complete MethodFlowchart for The Complete Method
1 1
Z=X
11
Z=F(X,Y)