The Micro Architecture Level Mic-1 architecture on Tanenbaum’s book Dept. of Computer Science...

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The Micro Architecture Level

Mic-1 architecture on Tanenbaum’s book

Dept. of Computer ScienceVirginia Commonwealth University

CMSC 312 Computer Organization 2 Hongsik Choi

Mic-1 block diagram

1. Why the C bus is represented as a bit map?

while B bus register is encoded in a 4 bit field

Only one register can be loaded onto B bus,

yet more than one register can be

selected to be loaded from C bus

2. Give a circuit diagram for “High bit”.

Simple answer?F =(JAMZ AND Z) OR (JAMN AND N) OR NEXT_ADDRESS[8]

Calculation of Next Address

MBR7Addr7

MBR0Addr0

Addr8MPC8

Calculation of Next address

MPC points to the next microinstruction.it is computed from

Next_Address JAM fields

the ALU status N and Z, the MBR

If JMPC MPC[0:7] = Addr[0:7]

Else Addr[0:7] OR MBR[0:7].

MPC[8] = Addr[8] or

(JAMZ and Z) or

(JAMN and Z)

Calculation of Next Address

3. Next address = 0x1FF and use JMPC?

Does it make sense? What if Next address is 0xFF?

111111111 (Next Address)

bbbbbbbb (MBR)

No, Meaningless

Next address is usually, 0x00 or 0x100

4. What if add k=5 after IF?

BIPUSH 5

ISTORE k

5 IJVM translation of i= k + n + 5

ILOAD k

ILOAD n

BIOUSH 5

ISTORE i

ILOAD k

ILOAD n

BIOUSH 5

ISTORE i

k+n k+n5

k k+n+5

k k+n+5k

6. Give the JAVA statement

ILOAD j

ILOAD n

BIPUSH 7

DUPIADD

ISTORE i

j-n j-nj7

j-n-7 j-n-7j-n-7

2(j-n-7)

i = j-n-7 + j-n-7

7. Is it possible?

If (Z) go to L1; else go to L2 // on page 259

Z : upper half or lower half

8.Why not: if_cmpeq3 Z = TOS-MDR;rd

If_icmpeq1 MAR=Sp=Sp-1; rd

If_icmpeq2 MAR=SP=SP-1

If_icmpeq3 H=MDR; rd

If_icmpeq4 OPC = TOS

If_icmpeq5 TOS = MDR

If_icmpeq6 Z=OPC-H; if (Z) go to T; else go to F

The only possible subtrahend is H

9. How long it will takes?

i = j+ k; w/ 2.tGHz Mic1

ILOAD(6)

IADD(4)

ISTORE(7)

23microinstructions *0.4nsec = 9.2 nsec

2.5GHz means 1 cycle / (1 / 2.5* G)sec = 0.4nanosec

ILOAD j

ILOAD k

ISTORE

Main PC = PC +1; fetch; go to (MBR)

Iload1 H=LV

Iload2 MAR=MBRU+H; rd

Iload3 MAR=SP=SP+1

Iload4 PC = PC +; fetch; wr

Iload5 TOS = MDR; go to main

IADD1 MAR=SP = SP-1; rd;

IADD2 H=TOS

IADD3 MDR = TOS+MDR-H;wr; goto main

ISTORE1 H=LV

ISTORE2 MAR=MBRU+H

ISTORE3 MDR=TOS; wr

ISTORE4 SP=MAR=SP-1; wr

ISTORE5 PC = PC +1; fetch

ISTORE6 TOS = MDRT; goto main

Microinstruction

Microinstruction: load k

ILOAD K 0x15 0x03

Microinstruction: iadd

IADD 0x60

Microinstruction: istore

ISTORE I 0x36 0x01

Microinstruction: Homework

by Nov 28

10 speed with Mic-2

Mic1 : 2 bus architecture

Mic2 : simplified decoding, 3 bus, IFU

Mic3 : 4 stage pipeline

Mic4 : 7 state pipeline

What is common?

PC is passed through the CPU and incremented

PC is used to fetch next byte

Operands are read from memory

Operand are written to memory

ALU does computation and results are stored back

IFU (Instruction Fetch Unit)

Independently increment PC and fetch next byte

(assemble 8 and 16 bit operands)

Depends on the opcode make available the next 8 or 16 bit whether or not doing so makes sense.

How to design IFU?

Fetch 4 bytes and load into shifter

Feed into MBR1 and MBR2

Whenever PC is changed, IFU must be changed

ILOAD(6)

IADD(4)

ISTORE(7)

ILOAD(3)

IADD(3)

ISTORE(5)

Main PC = PC +1; fetch; go to (MBR)Iload1 H=LVIload2 MAR=MBRU+H; rdIload3 MAR=SP=SP+1Iload4 PC = PC +; fetch; wrIload5 TOS = MDR; go to main

Iload1 MAR = LV + MBR1U;rd

Iload2 MAR=SP=SP+1

Iload3 TOS=MDR;wr;goto(MBR1)

as in Fig. 4-30 pp282-283

14 instn*0.4 = 5.6 nanosec

5.6/9.2 = x/100

x = 60.87sec

11 Write microcode for POPTWO

PopTwo1 SP=SP−1

PopTwo2 MAR=SP=SP−1; rd

PopTwo3

PopTwo4 TOS=MDR; gotoMain1

Pop1 MAR = SP -1; rd

Pop3 TOS = MDR; goto Main

12 loading locals 0- through 4

Special 1 byte opcodes for loading locals 0 to 3 onto the stack instead of ILOAD.

How should modify IJVM to make the best use of it.

Local 0 is the link pointer, (rarely used)

Let LV point first local variables as an offset( -1)

13 ISHR (Arithmetic Shit Right)

Use top two values, replacing with one value, Second word is operand to be shifted. It should be shifted between o-31 depending on the value of first

Opcode for ISHR is 122 (0x7A)

a. What is the arithmetic operation equivalent to shit right with a count of 2?

b. Write microcode.

Floor(fisrst)/2second

00000…1101000000…110

00000000…1

0000000…11

Extra: due Nov. 29th ?

14 ISHL

Fisrst*2second

15 INVOKRVIRTUAL

It needs to know how many parameters. Why?

Compute the base address of the new local variable frame by subtracting off the number of parameters from the stack

pointer and setting LV to point to OBJREF

16 DLOAD in Mic-2

dload1 MAR = LV + MBR1U; rddload2 H = MAR + 1dload3 MAR = SP = SP +1; wrdload4 MAR = H; rddload5 MAR = SP = SP + 1; wrdlaod6 TOS = MDR; goto (MBR)

17 finite state machine

18 equivalents?

19 finite state machine

20 IFU with a 5 byte shifter register

21 larger shifter for IFU

22 Mic 2 : go to

23 speed with Mic-2

24 Mic-4

25 two level cache

26 3 way cache?

27 pipeline

28 prefetch

29 cycle 6

30 dependency in pipeline

31 Rewrite Mic-1 intepreter

32 write simulator

The Micro Architecture Level Mic-1 architecture on Tanenbaum’s book Dept. of Computer Science...

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