Thermal Analysis for 3D Integration · H Heater S Thermal Sensor H0 H1 H2 H3 S0 S1 S2 S3 HP0 S HP1...

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Thermal Analysis for 3D Integration

GSA Oct 16 2013

Gene Matter, VP Application Engineering, DOCEA POWER

• Increasing thermal issues

– Technology scaling => higher power density

– 3D stacking with TSV => greater thermal issues

• Temperature impacts

– Power consumption

– Peak performance

– Ageing

– Package costs

• MPSoC architectures

– Dynamic applications, variable execution time

– Power management solutions (DVFS), can even worsen thermal properties!

Thermal mitigation schemes must be proposed at design time

Thermal issues for 3D IC and

heterogeneous assemblies

Thermal Modeling at the System Level

Physical Description Electrical Equivalent

Environment

Power Consumers

Materials

Compact Thermal Model

AceThermalModeler

Geometry

Physical Description

400 nodes 60sec extraction

• Heat transfer modeled via full 3D heat diffusion with no restriction to heat flow paths

• Support isotropic and anisotropic thermal conductivity

• Material homogenization and model reduction enabling dramatic reduction of the node count (Typically 4 orders of magnitude)

• Thermal model fully automated with Python scripts

Proposed Flow for Modeling Dynamic

Thermal Management

Simulation Output Reports

Aceplorer

Thermal Model Power Model

Use Case

Spatial effects Temporal effects

Rapid variations Long trends

• Analyze temperature dependent IP leakage

• Explore power/thermal management strategies

• Qualify environment capacitive effect

• Qualify design minimum cooling properties

– Given a power budget

– Given an environment: material, geometry

• Explore floor plan and proximity

dependencies

• Locate/Mitigate spatial and temporal hotspots

and gradients

• Identify optimal thermal sensor location

• Manage costs! Product: Die/Package,

Subsystem: PCB, chassis/enclosure, or

Complete Systems

Modeling Thermal at the System Level: Summary

Temporal effects

Spatial effects

Rapid variations

Long trends

Memory-on-Logic 3D stack

ARM1176

WideIO TSVs + Controllers 4 memory channels

3D NOC TSVs

3D NOC TSVs 4 * Heaters

Circuit Technology

-65nm CMOS TSV middle process

-Face2Back, Die2Die, Flip-Chip 3Dassembly

Main features

- WideIO memory controllers

- 3D Asynchronous NOC

- 3GPP LTE multi core CPU backbone

- Host CPU ARM1176

Circuit numbers

-125 Million Transistors

- 400 Macros

- 270 pads

- 1980 TSV for 3D NoC

- 1016 TSV for WideIO memory

- 933 Bumps for flip chip

Circuit performances

- WideIO 200MHz / 512 bits

- Units in the [350 - 400] MHz range

- Asynchronous NoC ~ 550 MHz

WIOMING stack

Back side alignment cross

~3000µm

8562 µm

~ 3 mm

Central Matrix copper post

Front side identification bump block

4950 µm

520 µm

•1386 µbumps matrix size•1016 µbumps per die

•252 Power•696 I/O Signal• 68 Not connected

•370 No µbumps

1016 backside micro-bumps / TSVs:

50µm x 40 µm pitch

For signal, test and power

No backside redistribution layer

Mechanical bumps added

933 frontside flip-chip bumps:

150 µm min. pitch

For signal, test and power

Assembly technology

Assembly Die-to-Die Stacking Face-to-Back

TSV process Via Middle TSV density 10µm diameter TSV xy pitch 50µm x 40 µm

Copper Pillars 20µm diameter

Central array of µbumps

Metal stack

Wide IO DRAM: face down

SoC: face down

Package

Substrate

supply IOs SoC signal and supply IOs,

SDRAM muxed test IOs

Peripheral bumps Central matrix µ-buffer

supply IOs

Metal stack

Package Balls

Package

molding

Flip-chip bumps

459 balls

Backside µ-bumps

SoC signal and supply IOs,

SDRAM muxed test IOs

Package: BGA 12x12, 581 balls

•TFBGA 12x12x1.2•481 outer rings balls•100 inner matrix balls•0.4mm ball pitch

1.2 mm

A1 ball corner identif ication

Package:

12 x 12 x 1.2 BGA

0.4 mm ball pitch

459 balls for signal, test and power

WIOMING 3D-Stack cross-view

[D. Dutoit & All, VLSI Symposium, 2013]

H Heater S Thermal

Sensor

Thermal Heaters & Sensors

• WIOMING instrumented with

– 8 Heaters (Resistance) • Can generate each 1Watt

– Thermal sensors • Accuracy ~1°C after calibration

• Full Software Control on the

to perform accurate 3D

Thermal Characterization

WIOMING system

Full-system thermal modeling including: WIOMING circuit

65nm SoC

WideIO DRAM memory

Daughter board

BGA socket

Mother board

AceThermalModeler - Thermal Model

ATM model: full system

Top assembly

WIOMING chip Daughter board

Daughter board balls

Spring probes

Base socket

Base socket balls Mother board

Full ATM model +5.2K system parts

16 power sources inside the chip: 8 heaters, 7 sensors and WideIO memory

6 power sources on mother board: FPGA and 5 peripheral ICs

10 defined materials

ATM model: WIOMING chip details

Top-die µ-bumps

Bottom-die

BGA substrate

Solder balls

Molding (epoxy)

Homogenization procedures

Combine multiple system parts into an equivalent one.

• Before homogenization

– System parts: 5244

– Materials: 10

– Nodes: 16milliion

After homogenization System parts: 68

Materials: 27

Nodes: 175 000

Thanks to homogenization, can simulate ATM model

Static simulation time : ~msec

Dynamic simulation time : ~sec

Simulation results: Center (memory controller) Heating

All 4 SME heaters ON:

Max error in temp. increase: 16.3%

Max error in total temp.: 9.91%

all SME heaters ON: 4W

SME_11 SME_12 SME_21 SME_22 MEP_0 MEP_1 MEP_2

Sensor

simulated

measured

all SME heaters ON: 4W

SME_11 SME_12 SME_21 SME_22 MEP_0 MEP_1 MEP_2

Sensor

simulated

measured

Simulation results: Bottom (CPU cores) Heating

Bottom MEP heaters ON:

Max error in temp. increase: -15.97%

Max error in total temp.: -9.26%

0 0.5 1 1.5 2

Power dissipation (W)

SME_12 - simu

SME_12 - meas

SME_21 - simu

SME_21 - meas

MEP_2 - simu

MEP_2 - meas

MEP_0 - simu

MEP_0 - meas

Simulation results: All Scenarios

• Average error of 4.22% and a worst case error lower than 12%.

Simulation results: Transient

• The transient temperature responses of the sensor BL2 for two power scenarios with different average distance from the active heaters

Average distance of 3.8mm from active heaters power scenario 2 (all center heaters on)

Average distance of 1.0mm from active heaters power scenario 4 (all bottom left heaters on)

Conclusion

Ready for early exploration of 3D stack with TSVs

Homogenization procedures to reduce model complexity

Full model generation automation using python scripts

Simulation complexity in ~seconds

Model correlation with Silicon

Performed on a real Memory-on-Logic 3D stack

WideIO DRAM + SOC 65nm, F2B, TSV middle, FlipChip

Error estimates in the 10-15% range

Requires a complete modeling of the full system

Thank You!

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Docea Power, Inc

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San Jose, California 95113

USA info@doceapower.com sales@doceapower.com support@doceapower.com

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Thermal Analysis for 3D Integration · H Heater S Thermal Sensor H0 H1 H2 H3 S0 S1 S2 S3 HP0 S HP1...

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