Post on 17-Jul-2020
transcript
Presented By
Andras Vass-Varnai
Thermal & Fluids Analysis Workshop
TFAWS 2019
August 26-30, 2019
NASA Langley Research Center
Hampton, VA
TFAWS Interdisciplinary Paper Session
Thermal characterization of SiC
MOSFET devices
Andras Vass-Varnai, Young Joon Cho, Joe Proulx,
Jimmy He, Peter Doughty Gabor Farkas,
Marta Rencz
Mentor Graphics a Siemens Business
Outline
• Thermal transient testing of MOSFET devices
– Potential problems with SiC
• A proposed simulation and test based method
• Experimental example
• Conclusions
TFAWS 2019 – August 26-30, 2019
Thermal transient testing of power devices
• Measure how heat is flowing through a package from junction to ambient
• Convert to a representation of the heat path as an Rth-Cth plot (Structure
Function)
• A non-destructive method to:
– Determining Zth
– Providing insight to heat path segments
– Comparing structures (e.g. to known good sample)
– Changes over time (delamination, cracks in substrate, etc.)
– and more…
TFAWS 2019 – August 26-30, 2019
• The forward voltage of a PN
junction under forced current
condition can be used as a very
accurate thermometer
• The change of the forward voltage
(TSP – temperature sensitive
parameter) should be carefully
calibrated against the change of
the temperature (see JEDEC
JESD51-1 and MIL-STD-750D)
– In the calibration
process the SVF
temperature
sensitivity of the
forward voltage is
obtained
T = VF·K
TFAWS 2019 – August 26-30, 2019
How is ∆Tj determined accurately?
@2mV/K sensitivity app.0.01 degC
resolution can be achieved
Thermal transient test workflow
4. Analyze
Vsense
Isense
1. Find the TSP
y = -0.001484x + 2.725130
2.580V2.600V2.620V2.640V2.660V2.680V2.700V
00.0°C 50.0°C 100.0°C
2. Calibrate
Ipower
t
1
P(t)
P(t)
3a. Power Step
t
T(t)
T(t)
3b. Record
TFAWS 2019 – August 26-30, 2019
Structure function example
• Each section of the Structure Function path represents physical objects the heat encounters. There
is a correlation between physical objects and sections of the RC path.
Die
Die Attach
Copper
Solder/
Insulation
Copper
Frame
TIM
Cold
Plate
Ambien
t
TFAWS 2019 – August 26-30, 2019
Measurement of MOSFET-s in general
• MOS diode (Threshold mode) – current step
method– Gate connected to the Drain
– The resulting two-pole device
behaves as a simple diode
– The threshold voltage can be
higher than 5V
• Heating on Rds,on, measurement on body diode– A negative sensor current is applied to the MOSFET
– For the heating, a sufficiently high voltage is applied to the gate
and the device heated with high current (IH-IS)
– Simultaneously to the heating current switched off the gate
voltage turned to zero -> the transistor closes and the sensor
current flows through the diode
TFAWS 2019 – August 26-30, 2019
For SiC the second strategy may work well
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
1e-4
0.01
1
100
10000
Rth [K/W]
Cth
[W
s/K
]
T3Ster Master: cumulative structure function(s)
ch_2_000000 - Ch. 2ch_2_001000 - Ch. 2ch_2_002000 - Ch. 2ch_2_003000 - Ch. 2
Separations in the structure functions
indicate changes to heat flow path i.e.
package structure. To better
understand the cause, we align the
curves based on a package component
known to be reliable: MOSFET
copper base-plate.
MOSFET
Cu base plate
Power cycling test data on a SiC MOSFET
TFAWS 2019 – August 26-30, 2019
Problems with SiC devices
• The SiO2 – SiC transition, may contain trapped charge carriers due to the
large concentration of crystalline errors at the interface
– Some techniques, such as post-oxidation annealing of the gate oxide
in nitric or nitrous oxide (NO or N2O) may improve the device
performance
• In some structures the movement of these trapped charges cause
electrical disturbances up to the several seconds range after the
switching
• Thermal transient tests should be carried out in connection modes,
where the gate potential remains unchanged during the process.
• This makes common test procedures, such as the “MOS diode” setup
and the fixed VDS arrangement unsuitable for testing SiC devices.
TFAWS 2019 – August 26-30, 2019
Examples of electrical parasitic response
• SiC MOSFET measured with 20A sensor current, 240 A
heating current and 15V VGS
1e-6 1e-5 1e-4 0.001 0.01 0.1 1 100
2
4
6
8
10
Time [s]
Tem
pera
ture
cha
nge
[°C
]
T3Ster Master: Recorded functions
240A_20A_long_g - Ch. 0
ΔT
[o C]
t [s]
Strong non-monotonous
behavior, even at larger
time constants
TFAWS 2019 – August 26-30, 2019
1e-6 1e-5 1e-4 0.001 0.01 0.1 1 10 1000
5
10
15
20
25
Time [s]
Tem
pera
ture
chang
e [°C
]
T3Ster Master: Recorded functions
10V_50A_20Along ng - Ch. 010V_50A_20A_grease - Ch. 0
1e-6 1e-5 1e-4 0.001 0.01 0.1 1 10 1000
5
10
15
20
25
Time [s]
Temperature change [°C]
T3Ster Master: Recorded functions
10V_50A_20Along ng - Ch. 010V_50A_20A_grease - Ch. 0
ΔT
[o C]
t [s]
Examples of electrical parasitic response
• SiC MOSFET measured with 20A sensor current, 5A
heating current and 10V VGS
No ideal fit if dual-
interface technique is used
– not pure thermal signal
TFAWS 2019 – August 26-30, 2019
Measuring the reverse diode always works
• As the issues demonstrated above most likely
correspond to a gate charge related phenomena, the SiC
diodes are not affected
1e-4 0.001 0.01 0.1 1 10 100
15
20
25
30
35
40
45
50
55
60
Time [s]
Me
asu
red tem
pera
ture
[°C
]
T3Ster Master: Recorded functions
TDIM_sample_8_SiC_50A_120_sec_no_grease_low_side_sample_8_SiC_50A_120_sec_grease_low_side - DryTDIM_sample_8_SiC_50A_120_sec_no_grease_low_side_sample_8_SiC_50A_120_sec_grease_low_side - Tim
ΔT
[o C]
t [s]
Separation is of pure
thermal origin
TFAWS 2019 – August 26-30, 2019
Proposed method
• Measuring the diode only is not
enough – transistor
characteristics is also
necessary
1. Use diode test data to calibrate
a the simulation model of the
component
2. Get the transistor thermal
properties from the calibrated
simulation model
TFAWS 2019 – August 26-30, 2019
Detailed Model Calibration
• Build detailed model of the component
• Adjust material properties and geometries until the simulated
thermal response matches the measurement
• Achieved via an automated optimization process
TFAWS 2019 – August 26-30, 2019
Calibrated – End of 1st Pulse
Best Guess – End of 1st Pulse
EXPERIMENTAL
Test arrangement and simulation model
• Use a Si IGBT package with
embedded reverse diodes
as demonstrator
• This allows not only
simulation but experimental
verification as well – may
not be possible in case of
SiC module
TFAWS 2019 – August 26-30, 2019
Comparison of test and simulation
• First simulation attempt – similar shape, but multiple
inaccuracies
TFAWS 2019 – August 26-30, 2019
Optimization of simulation parameters I.
• Main variables are
– Thermal conductivity coefficients
– Size of package features
– Specific heat and density (less important)
• Set up simulation scenarios
Unit Initial
Value
Parameter
range
Calibrated
Value
Active
Area mm2 81 64 ~ 81 79
Die
Adhesive W/mK 33 30 ~ 35 33
Ceramic W/mK 25 25 ~ 35 34
Solder W/mK 40 35 ~ 45 45
TFAWS 2019 – August 26-30, 2019
Cross-verification
• Very good match as the DA layer and the substrate is
already calibrated
• From here the package thermal metrics can be identified
accurately using simulation
TFAWS 2019 – August 26-30, 2019
Determining RthJC from model
• RthJC can be determined based on its definition.
– We used two possible interpretations:
• RthJC=𝑇𝑗 𝑚𝑎𝑥 −𝑇𝐶(𝑚𝑎𝑥)
𝑑𝑃
• RthJC=𝑇𝑗 𝑚𝑒𝑎𝑛 −𝑇𝐶(𝑚𝑒𝑎𝑛)
𝑑𝑃
Case regionJunction regions
TFAWS 2019 – August 26-30, 2019
Comparison of simulation data to test
• The divergence separation region of the structure
functions is in line with the RthJC range calculated based
on the model
Temperatures Maximum Mean
Base plate [°C] 70.3373 62.9045
IGBT active area [°C] 75.829 74.2957
RthJC [K/W] 0.079 0.163
dP=69.5W
TFAWS 2019 – August 26-30, 2019
Conclusions
• Thermal transient testing using electrical test methods can be applied to SiC
semiconductors package thermal characterization
• Certain novel compound semiconductor structures require non-standard test methods or in
particular cases may not be suited to this characterization method.
• The reverse diode, if present is a well measurable component
• Based on the thermal transient response of this component the package structure can be
identified
• If a thermal simulation environment is available, the simulation model can be calibrated to
the test-based structure functions
– The calibrated model will respond correctly in a wide range of time constants.
• Using this calibrated model the thermal properties of all heat sources in the package can
be simulated
• Having a calibrated package model has further benefits, it helps to identify a suitable way
to interpret the separation point of structure functions if the separation is not a clear single
point, but shows up rather like a continuous region
TFAWS 2019 – August 26-30, 2019