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Three-Dimensional Three-Dimensional Microelectronics Microelectronics Integration:Integration:Design, Analysis and Design, Analysis and CharacterizationCharacterization
Zeynep DilliPh.D. Program Dissertation Proposal
Introduction & Motivation: 3-D Introduction & Motivation: 3-D IntegrationIntegration Current trend in electronics: Tighter integration at every integration
level: Device Gate Chip … Board Main Board System Still Planar!
Limitations: Speed, compactness, signal clarity, robustness… “Smart Dust” systems
Ideally self-contained, self-powered and small May require mixed-signal integration 3-D stacking might be the ideal answer
Stacks with cap chips…
…with intertier vias
…with sidewall connections
3-D vs. 2-D Integration: 3-D vs. 2-D Integration: Advantages & Disadvantages Advantages & Disadvantages
1. Net system size reduction2. Increased active Si area/chip
footprint3. Delay reduction: faster clocks
or higher bandwidth• Shorter interconnects• Lower parasitic & load
impedance4. Potential intra-system noise
reduction5. Potential substrate noise
reduction6. Heterogeneous integration7. More freedom in geometric
design8. Lower power consumption.
1. Increased heat-dissipation problems
2. Increased design complexity.
Challenge to the Designer
3-D integration is a subject that ties together chip design, chip physics, device design, circuit design, electromagnetics, and geometrical layout problems.
OutlineOutline
Proof of concept: A 3-D integrated self-powering system
Circuit performance in 3-D integration Passive devices for self-contained 3-D
systems
Self-Powered Electronics by Self-Powered Electronics by 3-D Integration: Proof of 3-D Integration: Proof of
ConceptConcept
3D system concept: Three tiers Sensor (Energy harvesting: Photosensor) Storage (Energy: Capacitor) Electronics (Local Oscillator and Output Driver)
Process & CircuitProcess & Circuit 0.18 μm fully-depleted SOI process
3 metals p-type substrate, ~1014
Implants: Threshold adjustment, CBN and CBP (5x1017), source-drain, PSD and NSD (0.5x1019, 1x1019)
ip
Process informationProcess information
Silicon islands 50 nm thick
Three-metal process
Three tiers stacked
Through-vias Top two tiers
turned upside-down
Figure adapted from MIT_LL 3D01 Run Application Notes
Photodiodes: Design IssuesPhotodiodes: Design Issues
Photocurrent=Responsivity [A/W] x Incident Power Responsivity= Quantum efficiency x λ [μm] /1.24
For red light, λ [μm] /1.24 = 0.51 Incident Power = Intensity [W/μm2] x Area [μm2]
Sunlight intensity ≈ 1x10-9 W/μm2
Quantum Efficiency: η = [# electron-hole pairs]/ [# incident photons] Depends on reflectance, how many carrier pairs make it to the outer circuit,
and absorption At 633 nm (red light), absorption coef. ≈3.5e-4 1/nm
amount of photons absorbed in 50 nm depth is (1-exp(-αd)) ≈ 0.017
η = 0.017 x reflectance x ratio of non-recombined pairs ≈ 0.017 x 0.75=0.013
Photocurrent=0.013 x 0.51 x 1x10-9 x Area[μm2] = 6.63 pA/μm2
Major problem: The material depth is very small
Photodiodes: Design IssuesPhotodiodes: Design Issues Photocurrent=0.013 x 0.51 x 1x10-9 x Area[μm2] = 6.63 pA/μm2
Photosensitive area: pn-junction depletion region width (Wd) times length Available implants: Body threshold adjustment implants (p-type CBN and
n-type CBP, both 5x1017 cm-3); higher-doped source-drain implants and capacitor implants; undoped material is p-type, ~1014 cm-3.
Two diode designs: CBN/CBP diode and pin diode (CBP/intrinsic junction) CBN/CBP diode Wd=0.0684 μm; A=0.5472 μm2
Pin-diode Wd ≈ 1.5 μm; A=15 μm2; possibly problematic To increase: Higher-intensity light; optimal wavelength (higher
wavelength increases λ/1.24, but decreases absorption)
Layout Constraints: As many diodes as possible; diodes in regular arrays; need three bonding pads of a certain size; assigned area 250 μm by 250 μm only
Layout: 2062 CBN/CBP diodes: 7.48 nA; 52 pin diodes: 5.17 nA Expect about 12 nA
Layout: Tier 2, CapacitorLayout: Tier 2, CapacitorTop plate: Poly
Bottom plate: N-type capacitor implant, CAPN
Extracted value: 29 pF
Expected value: 30 pF
3-D System, Further 3-D System, Further Research, 1Research, 1 Test the device once fabrication is completed:
Self-contained system, 250 μm x 250 μm x 700 μm Design a version to be fabricated at LPS
Greater active photosensor depth Voltage regulator to prevent diode forward bias
current overtaking the photocurrent Investigate rectifying antennas as alternate
power source Preliminary investigation done on circuit board level See further work on passive structures
3-D System, Further 3-D System, Further Research, 2Research, 2 Compare yield of 3-D system with planar system of the
same footprint area Codify self-powering system design methodology
Photodiode-based: Photodiode power generation ability: Diode design and chip optical
design (microlenses/AR coatings…) Charge storage system: Capacitor, high-k dielectric use Power regulation circuit requirement
Rectifying-antenna based: Antenna properties: Possible low-k dielectric use Need for a transformer Rectifier diode design
Tied to load circuit characteristics
OutlineOutline
Proof of concept: A 3-D integrated self-powering system
Circuit performance in 3-D integration Passive devices for self-contained 3-D
systems
3-D Integration: Performance 3-D Integration: Performance StudyStudy
Speed Intra-chip communication
Heat Generation and dissipation
Noise Substrate noise External Interference
Signal Integrity Compare performance with planar integrated
circuits and connections
Performance: SpeedPerformance: Speed Bonding pads, wires: Extra load + parasitics:
Slow things down
Left: “External” ring oscillator, 11 stages (two stages are shown)
Internal Osc.Internal Osc. External Osc.External Osc. One-stage delayOne-stage delay
112 MHz (31-stage)(equivalent to 1.16 GHz for 3 stages)
398 KHz (11-stage)(equivalent to 1.46 MHz for 3 stages)
~330 ps for internal, ~330 ns for external dev.
Speed ratio: 794.5Load ratio: ~1000
Right: Internal ring oscillator, 31 stages,
output to divide-by-64 counter
Both are comprised of minimum-size transistors, simulated speed for 31 stages: 132 MHz.
3-D Connections vs. Planar Off-chip 3-D Connections vs. Planar Off-chip ConnectionsConnections
Chip-to-chip communication between different chips with vertical vias that require 12m x 12m metal pads
Cadence-extracted capacitance for a pad 9.23 fF: Same order of magnitude as inverter load cap
in2 out2
out1 in1
3-D Connections: “Symmetric” 3-D Connections: “Symmetric” ChipChip
Structures that can be connected in 3D and planar counterparts for comparison
3-D Connections: “Symmetric” 3-D Connections: “Symmetric” ChipChip
•A 31-stage planar ring oscillator and •A 31-stage 3-D ring oscillator (In the figure, groups of 5-5-5-5-5-6).
The proper pairs of pads have to be connected to each other through vertical through-chip vias post-fabrication for the circle to close.
To counter input
Simulation results:
Planar: 142 MHz3-D, six “layer”s: 122 MHz (six vertical pads as extra load)
“symmetry” axis
3-D Integration: Performance 3-D Integration: Performance StudyStudy
Speed Intra-chip communication
Heat Generation and dissipation
Noise Substrate noise External Interference
Signal Integrity Compare performance with planar integrated
circuits and connections
Performance: HeatPerformance: Heat Coupled simulation at device and chip level to characterize chip
heating: Generation, distribution and dissipation
Performance: HeatPerformance: Heat2( )o
TC T T H
t
Modified heat flow equation:
Integrated over a volume to obtain a “KCL” eqn.:
6
1
fo f
f Vf
T STCV H
t l
Discretized:
1, , , , , , 1, , , , , 1, , , , , 1 1
, , , , , ,1 1 1, , , , , ,2 2 2
( ) ( ) ( ) ( )( )
l l l l l l l li j k i j k i j k i j k i j k i j k i j k i j kth l l
i j k i j k i j kth th th
i j k i j k i j k
T T T T T T T TC I T
t R R R
“C(dV/dt) + (V2-V1)/R = I”
General Algorithm: Solve device equations for a range of temperatures; set up the chip thermal network including heat generation; assume initial temperatures and solve the thermal network; obtain heat generated by each transistor at that temperature; reevaluate heat generated by each transistor, repeat until convergence
Also Possible: Use solver to suggest layout solutions for heat dissipation
Performance: Performance: HeatHeat Device operation characteristics depend
on temperature (e.g. I-V characteristic of a diode)
Affects circuit operation (e.g. foscof a ring oscillator)
3-D Integration: Performance 3-D Integration: Performance StudyStudy
Speed Intra-chip communication
Heat Generation and dissipation
Noise Substrate noise External Interference
Signal Integrity Compare performance with planar integrated
circuits and connections
Performance: NoisePerformance: Noise
Substrate NoiseModeled as substrate currents [1] or lumped-
element networks [2]Characterized with test circuits [3] or S-
parameter measurements [4]
[1] Samavedam et al., 2000 [2] Badaroglu et al., 2004
[3] Nagata et al., 2001, Xu et al., 2001 [4] Bai, 2001
Performance: Signal Performance: Signal IntegrityIntegrity On-chip interconnects on lossy substrate: capacitively
and inductively coupled [1] Characterized with S-parameter measurements Equivalent circuit models found by parameter-fitting
[1] Zheng et al, 2000, 2001; Tripathi et al, 1985, 1988…
Performance: Signal Performance: Signal IntegrityIntegrity Substrate properties and return current paths
affect interconnect characteristics Three modes of operation, affecting loss and
dispersion [1] Mutual inductance from a return current with a
complex depth to calculate interconnect p.u.l inductance [2]
Effect of a second substrate stacked in proximity not investigated
Effect of vertical interconnects not investigated
[1] Hasegawa et al, 1971 [2] Weisshaar et al, 2002
Performance: Further Performance: Further Research, 1Research, 1 Speed: 3-D integrated chip in design
revision Heating: Planar heating characterization
chip in fabrication; 3-D heating characterization chip being designed
Noise: Design a planar chip to model and characterize the substrate noise coupling within; design a 3-D integrated chip to compare noise performances
Performance: Further Performance: Further Research, 2Research, 2 Signal Integrity: Adapting the heat-elements
network to coupled interconnect models Evaluate the sensitivity of different interconnect layouts
to external pulses Set up a coupled network Use random current sources as external pulses to generate a
coupling map Design interconnect chips for experimental verification
Interconnect equivalent circuit model/parameter alterations for 3-D integration
Investigate capacitive and inductive coupling to a nearby conductive, electrically disconnected substrate in addition to the associated substrate
Derive transmission line parameters Design chips for experimental verification
OutlineOutline
Proof of concept: A 3-D integrated self-powering system
Circuit performance in 3-D integration Passive devices for self-contained 3-D
systems
On-Chip Inductors and On-Chip Inductors and TransformersTransformers
Self-contained integrated systems may require passive structures: Communication with other
units in the network: on-chip antennas
Power harvesting: Rectifying antennas and transformers
Various analog circuits---mixers, tuned amplifiers, VCOs, impedance matching networks: Inductors, transformers, self-resonant LC structures
On-Chip Inductors and On-Chip Inductors and TransformersTransformers Planar inductor design
Number of turns Total length First/last segment length Trace width
Trace separation Metal layer Substrate doping Substrate shields Stacked or coiled structure
Planar inductor modeling Define an equivalent
circuit, parameter-match to measurements
Separate physics-based approaches for serial or shunt parameters
De-embedding and ExtractionDe-embedding and Extraction
--------Measured reference frame for DUT_full-----------------Ref. frame after Open is taken out-------
----DUT----
11(1/ )( )
m YL
11
11
(1/ )( )
(1/ )
m YQ
e Y
An on-chip inductor has frequency ranges where it behaves inductively or capacitively:
Tuning an Inductor with LightTuning an Inductor with Light
Bottom right: Shunt capacitance increases; fsr drops ~150-200 MHz
Top right: Substrate resistance decreases: peak impedance increases
Exploiting Self-ResonanceExploiting Self-Resonance Certain circuits need LC tanks
Mixers, tuned LNAs (as a tuned load) LC filters
There is some interest on intentionally integrating inductors with capacitors to obtain an LC tank
Use the equivalent circuit model in a circuit design to exploit this effect and investigate optimization; verify experimentally
Passives: Further ResearchPassives: Further Research 3-D inductors in chip stacks
Investigate multiple-substrate inductor geometries
Electromagnetic modeling, experimental verification
Low-k dielectrics Tunable Self-Resonant Structures
Controlled tuning methodology Photoelectrical Electrical Electromagnetic
Circuit applications
SummarySummary
3-D Self-contained System Design 3-D System Performance Analysis
SpeedHeatNoise Signal integrity
Passive Structures for Self-Contained Systems3-D passivesTunable passives
……And on another track…And on another track…
Engineering education research Past work:
Helped direct ECE program for Maryland Governor’s Institute of Technology program, Summer 2001
Co-authored textbook Benjamin Dasher Best Paper Award in FIE 2002
Contributed to the design of ENEE498D, Advanced Capstone Design Presented paper in ITHET 2004
Participated in departmental outreach programs GE program for high school teachers, MERIT students, WIE summer programs
Attending PHYS 708: Physics Education Research Seminar Engineering education is an open research field as well Considering several questions adapted from PER: Student knowledge body
characterization; concept lists for EE…