Timing Model Reduction for Hierarchical Timing Analysis

transcript

Shuo Zhou

Synopsys

November 7, 2006

Outline

• Static Timing Analysis in Design Flow

• Hierarchical timing analysis

• Proposed Techniques– Iterative timing model reduction algorithm b

ased on a biclique-star replacement technique.

• Experimental Results

• Conclusions

Static Timing Analysis in Design Flow

• Static Timer is integrated in each stage.• Need efficient static timer.

Design Flow

Floorplaning

Synthesis

Placement&Routing

Static TimingAnalysis

Hierarchical Timing Analysis• Hierarchical timing analysis is essential for

hierarchical design.

• Consider circuits inside the blocks to be fixed.

• Complexity O(n): n is #edges in timing models.

Partition Design into Blocks

Characterize Blocks into Timing Models

Problem Statement

• Timing model minimization for hierarchical timing analysis:

– Given a hierarchical block, construct an abstract timing model with minimal number of edges that covers the longest and shortest path delays of each pair of input and output in the block.

Previous Works• Transform timing graph [Visweswariah ICCAD’9

9, Moon DAC’02].

– Perform serial/parallel edge merging.

• Represent delay matrix with minimal number of edges.

– Optimal realization of a distance matrix [Hakimi Quart. Appl. Math. 22 (1964), Chung http://www.math.ucsd.edu/˜fan].

– Biclique-star replacement for bicliques with unit edge delay [Feder Symp. on Theoretical Aspects of Computer Science (2003)].

Terminologies: Bipartite Timing Model

• G = {B, D, E}– Input set B, output set D, and edge set E

– Longest and shortest delays.

Bipartite timing model

Timing graph

path: 1->4->5->7->8->10

Delay matrix• Element on row i col j is delay from input i to ou

tput j, for disconnected input i and output j.

• Row i implies input delay vector = {di,j| di,j from input i.}

Bipartite timing model

OutputsO4

Delay matrix

• Gs = (Bs, Ds, s, Es)

– Bs input set, Ds output set, center vertex s.

– Edges (i,s) and (s,j).

Star1 4

Biclique-Star Replacement• Basic idea: match various input delay vectors to a

pattern and cover each input delay vector by one edge plus the pattern.

Biclique #edge = 9

star #edge = 6

Replace

dij = dis+dsj

OutputsO4

Pattern=Input

vectors

Bipartite Timing Model Reduction

Biclique Search

Reduction Ratio Evaluation

ratio = #edges_covered/(r+c)

Biclique-star Replacement

Reduction > 1 Re-evaluation

Repeat

Delay Vector Subtraction• Input delay vector subtraction Sub(Ia, Ib)

– Distance vector V(Ia,Ib) = {jIa,Ib =da,j – db,j| j

[1..c]}

• Input vectors Ia, Ib share a pattern if all jIa,Ib ar

e equal.

V (I2,I1)=

Sub(I2,I1)

O4 O5 O6

Biclique Expansion for Replacements

• Choose an input delay vector as the pattern vector.

• Expand the biclique of the pattern vector by covering as many as possible input vectors.

• Replace the biclique by a star.

Biclique Expansion (G, Ia, Gc)I. Add edges (a,j) to biclique Gc;II. For each input vector Ii

1. Vector subtraction Sub(Ii,Ia);2. If all j

Ii,Ia = 0Ii,Ia add edges (i, j) to Gc.

Biclique-star Replacement (Gc,Ia,Gs)I. Add inputs, outputs, center vertex s, and edges (i,s), (s,j) to Gs

II. da,s = 0, ds,j = Ia,j;III. For each edge (i,s) in Gs

1. di,s = 0Ii,Ia;

#edge = 9

#edge = 8

0I2,I1

Replace

I3 4 5 7

2 3 4I1

V(I3,I1) =Sub(I3,I1)

O4 O5 O6step 2

V (I2,I1) =Sub(I2,I1)

O4 O5 O6

step 1

0I2,I1

Don’t Care Edges•Edge (i,j) is a don’t care edge in a biclique star replacement if path delay di,s + ds,j < di,j.

Replace

Biclique

Don’t Care Edge

Biclique Expansion with Don’t Cares

• Choice: try each in distance vector as di,s. • For d3,s =

– di,j is covered if di,s + ds,j = di,j, i.e., j = .– di,j is a don’t care edge if j > .– Output j has to be removed if j < .

#edges covered increases by 2

I3 4 5 7

2 3 4I1

V(I3,I1) =

O4 O5 O6

#edges covered decreases by 1

Biclique Expansion and Replacement with Don’t Cares

Biclique Expansion with Don’t Cares (G, Ia, Gc)I. Add edges (a,j) to Gc;

II. For each input vector Ii

1. Vector subtraction Sub(Ii,Ip);

2. For each j in the distance vector

For each k in distance vector

if k = j #covered++;

else if k < j #removed +=edges to output k;

3. If maximum (#covered - #removed of j )> 1;

For each k in distance vector

if k j Add edge (i,k) to Gc; else remove output k and edges to k.

Replacement with Don’t Cares (Gc, Ia, Gs)

I. Add inputs, outputs, center vertex s, and edges to Gs

II. da,s = 0, ds,j = Ia,j;

III. For each edge (i,s) in Gs

1. di,s = min(Ii,Ia ).

Replace

#edge = 9 #edge = 7

Don’t Care Edge

I1Min7

V (I2,I1)=Sub(I2,I1)

O4 O5 O6

step 1

I3 4 5 7

2 3 4I1

V(I3,I1) =Sub(I3,I1)

O4 O5 O6step 2

Bipartite Timing Model Reduction

Biclique Search

Reduction Ratio Evaluation

ratio = #edges_covered/(r+c)

Biclique-star Replacement

Reduction > 1 Re-evaluation

Star Graph to Bipartite Graph

Split s1,s2

Recover Stars

bipartite graph

star timing model

Star Graph to Bipartite Graph Transformation

Correctness

• G: the bipartite timing model before the reduction.

• G': the timing model after the reduction.

Edge delay di,j of any connected input i and output j in G is covered by the longest path delay d

i,j' from input i to output j in G' after the reduction.

Experimental Results• Test cases

– Block 1: 8499 inputs, 16885 outputs, and 138,360 edges

– Block 2: 4260 inputs, 7728 outputs and 103,414 edges

– EG-- #edges in original timing graph of the block.

– EB--#edges in bipartite timing model.– Em--#edges after timing model reduction.• Reduction rG = (EG – Em)/ EG.• Reduction rB = (EB – Em)/ EB.

Block1 EG = 138,360, EB = 262,491

Err_bound (ns)

Em rG rB

0 249,032 -80.0% 5.1%

0.1 41,696 69.9% 84.1%

1.0 36,980 73.3% 85.9%

10.0 35,981 74.0% 86.3%

100.0 36,169 73.9% 86.2%

• |di,j – di,j’| <= Err_bound, where di,j and di,j’ are delays from input i to output j before and after the reduction.

Buffer1 delay = 1.34ns.

Block2 EG = 103,414, EB= 465,190

Err_bound (ns)

Em rG rB

0 397,384 -284.3% 14.6%

0.01 49,613 52.0% 89.3%

0.10 29,477 71.5% 93.7%

1.0 21,192 79.5% 95.4%

10.0 20,262 80.4% 95.6%Buffer 1 delay = 0.74ns.

Conclusions

• We propose a biclique-star replacement technique and develop an iterative timing model reduction algorithm based the proposed technique.

• By allowing reasonable error bounds, the experimental results show that the proposed algorithm can effectively reduce the number of edges in the timing model.

Thanks!

References• C.W. Moon, H.~Kriplani, and K.~P. Belkhale, “Timing model extraction

of hierarchical blocks by graph reduction”, in DAC’02, 152-157.

• C. Visweswariah and A.R. Conn, “Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation”, in ICCAD’99, 244-251.

• S. L. Hakimi and S. S. Yau. “Distance matrix of a graph and its realizability.” Quart. Appl. Math. 22 (1964), 305–317.

• F. Chung, M. Garrett, R. Graham, and D. Shallcross. “Distance realization problems with applications to internet tomography.” http://www.math.ucsd.edu/˜fan.

• T. Feder and A. Meyerson and R. Motwani and L. O' Callaghan and R. Panigrahy, “Representing graph metrics with fewest edges.” in Proc. of Symp. on Theoretical Aspects of Computer Science (2003), 355--366.

Timing Model Reduction for Hierarchical Timing Analysis

Documents