Tool for Customizing Fault Tolerance in a System

transcript

Karan Maini and Sriharsha Yerramalla ECE 753 Project #10

May 1, 2014

Agenda• Introduction• Background and Related Work• Problem Statement Formulation• Implementation• Hardware Redundancy Techniques and FT Library• Synthesis Results – Area and Timing• Conclusion and Future Scope

• CAD Tools– Implementing electronic systems easier– Cut down on development time– Made verification process automated

• CAD Tools for Fault Tolerance– Did not leverage advancements– Fault Tolerance was introduced manually– Being picked up in the recent past

Introduction

• Need for Fault Tolerance– Real-time Systems– Operation Critical Systems– No guarantee of flawless execution

• Applications– Banking– ATM Machines– Spacecraft– Satellites

Introduction

• There has been several attempts made to develop an efficient tool without much manual intervention to introduce FT.

• This could be at various levels of granularity. • Our attempt is to make FT at module level

granularity.

Introduction

The Challenge

The Plan

Solution

VB B B

• Hardware Redundancy– Insertion of F-T components into circuit– Done Manually (Old days)– Automatic Insertion Tools (At Present)

• Process– Identify element(s) to be modified– Replication of selected element(s)– Selecting one set of output from different outputs coming from

replicated element(s)

Background and Related Work

• Hardware Redundancy (Contd.)– Initial Conditions – Input synthesizable design files

– Pre-processing tasks – Identify type, number of elements present

and their characteristics

– Similar to simplified elaboration for synthesis

– Specify the Hardware Redundancy technique to be followed

• Information Redundancy– Selection of elements (Memory – IM, DM, Register Files)

– Nearly entire module modification to deal with

– Modification of data types and operators in order to process

encoded information

– Insertion of encoders, decoders and checkers in original design

– Adding appropriate operators in F-T library

– Declaration of target objects with the extra bits

• Information Redundancy (Contd.)– Insert an encoder at a selected point

– Extend the size of selected data to accommodate extra bits

required by the redundant code used

– Perform the functionality on the coded data

– Insert a decoder/checker at a selected output point to get back

the original data

Make a design Fault Tolerant by introducing

components into the design using various Hardware

Redundancy Techniques. Provide a Fault Tolerant

Library to choose components from. Synthesize the

original and new design to compare overhead

introduced in terms of area and time.

Problem Statement Formulation

• Introduce Fault tolerance at Modular level

• Target for Coarse granularity

Assumptions

• User will input all the Synthesizable design files

• At any given instant of time, only a single

instance of a module may be fault prone.

• User will only input files written in Verilog HDL

Taming the Bull

• In which stage of design should this be tackled? RTL or netlist

• In netlist – Finer control over granularity, but higher design complexity

• In RTL – Difficult to have smaller granularity, but relatively simple design

• This is where our tool helps

Approach• Accept design files and top level module from

user.• Identify different modules and their hierarchies

present in the design.• Accept options from user.• Update the design with fault tolerance.• Verify the design.

Design

Scheme of Fault Tolerant Insertion Tool

Front End - GUI

Technology: Java Swing Look and Feel: Windows 8

Section 1• Welcome Screen• Upload Design files• View/Update selected files• Enter top-level module

• Fork() a child process to call back-end search engine

Section 2• Hierarchical View• Returns from back-end• JTree Component used • Different levels – modules

and instantiations

• Singleton selection on leaf node - select an instance

Section 3• Select Redundancy Type• Scan characteristics of

Instantiated Module Parameters passed Bus-width of parameters

• Introduction of Library Component into design

• Success Message Dialog Box to inform user

Logical Components of Tool

FT Insertion

Library

Search Engine

Front End Back End

Search Engine block• FT insertion block passes the Verilog design

files to search engine block.• Searches for all modules in the design and

populates them in an array.• Starts a recursive process to identify all the

instances and their hierarchies. • Returns the hierarchical information to FT

insertion.

Library• Following hardware redundancies are supported.1. TMR2. 5MR3. Hybrid4. Sift-out5. Pair and Spare

TMR • Instance is replicated thrice and a Voter is

added. Parameterized voter to support any bus width

• Similar to TMR Voter….

Hybrid Redundancy• Implemented the design proposed by Daniel P.

Siewiorek et al.• Made minor modifications to circuit to support

scalability.

Implementation of Hybrid Redundancy P

S Status reg Comp block

Sift-Out Modular Redundancy• Implemented the design proposed by Paulo T. De

Sousa et al.• Made minor modifications

Implementation of Sift-out Redundancy

comparator and registerE C

Pair and Spare

comparator

Switch

Library Options

Area and Delay Overhead

Micro-op Generator

Data PathMicro-op inst gen

Inst_gen

Offset_reg_num_gen

Offset_gen

Reg_num_gen

Priority Encoder

Area Overhead for Micro-op Generator

• Area without FT – 7628.1

Module / FT technique

5MR Hybrid (3,2) Sift-out (5)

Data_path 28023.1 28220.7 28214.2

FSM 11215.3 11420.8 11415.7

Offset_Regnum gen

17925.6 18128.2 18123.4

Reg_Num_Gen 16968.4 17212 17205.3

Act low decoder 8378.1 8661.9 8656

DUTs• PIIR filter• Micro-op Generator• 5 stage pipelined micro-processor

Future Work• Other types of hardware redundancies can be

added to library modules without changing other parts of tools.

• Information redundancy can also be added, but it will involve change in the tool and will need more information from user.

Conclusion• Tool that introduces fault tolerance in a Digital

System is successfully developed.• The tool is tested on three different designs.• Overhead of various fault tolerance techniques

is calculated and compared.

Tools Used• Java• Perl• Design Vision• Quartus

Tool for Customizing Fault Tolerance in a System

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