Post on 14-Feb-2016
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Update on GTK ASIC development
presented by A. KlugeCERN/PH-ESEApril 4, 2011
OutlineIntroduction, strategyASIC architectureStatus of
Pixel matrix: Front-end, trim DACs, inPixel configuration
Transmission line, receiver, hitArbiterTDC: delay line, charge pump,
hit registersRead-out & configuration master
OutlookA. Kluge
45 x 40 pixel full matrix
Addr.
Addr.
Addr.
Hit Arbiter Hit Arbiter Hit Arbiter
LVDSH
it Reg1
Addr.
Hit Arbiter
45
4045 45 45 45
Ref CLK320MHz
serializerDLL Digital processing
Hit R
eg2
Hit R
eg1H
it Reg2
Hit R
eg1H
it Reg2
Hit R
eg1H
it Reg2
32
A. Kluge
Data format Nominal transmission: 2.4 Gbits/s, High speed: 3.2 Gbits/s All words: 48 bits (6 bytes) long 8b10 encoded bit stream 60 bits data word frame word idle (komma) word: no hits available to transmit, 6 * comma character (ie. K28.5) sync word: after reset and after each force_sync command (can be sent repetitive)for 4 * 106 cycles, 100 ms @ 2.4 Gbit/s, 6 * comma character (ie. K27.7) link checking sequence, known pattern (ie. counter) sent upon request Header contains frame counter every 6.4 µs Data contains dynamic range up to 6.4 µs + 1 overroll counter bit
Data format-hit word normal mode (48 bit)
Status/data selector 1 bit Leading coarse time 12 bit 1bit rollover indicator+2048(11bit)*3.125 ns=6.4 µs
Leading coarse time selector 1 bit Leading fine time 5 bit 98 ps -> 3.125 ns Trailing coarse time 5 bit 32*3.125 ns = 100 ns Trailing fine time 5 bit 98 ps -> 3.125 ns Trailing coarse time selector 1 bit Address 7 bit (90 pixel groups) Address-hit arbiter 5 bit Address pileup 5 bit Error bit (SEU or overflow) 1 bit
___________________________________________________________________________________
Total 48 bit
Data format-status words
Two words
status/data selector 2 (for each one word)*2 bit 11 status word 10 error word, FIFO overflow information
frame counter 28 bit 2**28*6.4 µs=1718 s # of hits in previous frame 7 bit 2**22=4E6, hits per quarter chip = 130 Mhits/s /4* 6.4 µs = 208 512 7
bit
# of SEU in previous frame 6 bit 2**6=64, 64/6.4µs = 10E7
Check sum 16 bit spare info 37 bit
___________________________________________________________________________________
Total 96 bit = 2 * 48
idle word (48 bit)
6 * Komma K28.5___________________________________________________________________________________
Total 6 * 48 bit
sync word (48 bit)
6 * Komma K27.7___________________________________________________________________________________
Total 6 * 48 bit
Operation Test Powerclk_dig lvds_in 2 Test_out <37
downto 0>Cmos or analog or lvds
38 VDDanalog1.2 power 13
clk_dll lvds_in 2 Test_in <39 downto 0>
Cmos or analog or lvds
40 VDDtdc1.2 power 6
serial_conf_in lvds_in 2 VDDdigital1.2 power 7
reset_coarse_frame_count
lvds_in 2 Optional VDDserializer(min.3 pairs/serializer)
power 12
reset_global cmos_in# 1 address <3 downto 0>
cmos (4)
reset_dll cmos_in# 1 Jtag_trst cmos (1) VDDlvds2.5 power 1
serial_conf_out lvds_out 2 Jtag_tck cmos (1) VDDlvdsMultiSerial2.5
power 2
reset_bandgap cmos_in 1 Jtag_tms cmos (1) GNDanalog1.2 power 13
serial_out<3 downto 0>
CML_out 8 Jtag_tdi cmos (1) GNDtdc1.2 power 6
temp
<1 downto 0>
analog_out
2 C_chan <7 downto 0>
cmos ? GNDdigital1.2 power 7
test_pulse_in diff analog_in
2 Jtag_tdo cmos (1) GNDserializer(min.3 pairs/serializer)
power 12
multiSerial_out<19 downto 0>
lvds_out 20
seu lvds_out
2
GNDlvds2.5 power 1
Mode GNDlvdsMultiSerial2.5
power 2
bandgap_override
analogInOut
1
mode_parallel_out
cmos_in 1 12-2*0.215 mm / 0.073 mm = 158
134wo()
clockMuxMode cmos_in 3# possibly LVDS
I/O
Pixel matrix: Front-end, trim DACs, inPixel configuration
A. Kluge
pixel matrix
A. Kluge
J. Kaplon
2 column structure
A. Kluge
J. Kaplon
pixel cell
A. Kluge
Discriminator has beenadapted for the threshold trim DAC
5 bit inPixel trim DAC added
inPixel configuration addedinPixel configuration is based on serial chain of 4 columns controlled by EOC located master, TMR SEU protection scheme, along with single bit self correction possibility
J. Kaplon & M. Noy
Transmission line receiver hitArbiter
A. Kluge
Transmission line, receiver, hitArbiter
Transmission driver & line & receiver unchanged from prototype
hitArbiter (5 to 1 Mux maintaining time information) improved: qualified with VHDL hit generator reflecting
beam profile (1 GHz)
output: pixel address & 2 time stamps (hit)
& OR pixel address & no time stamp (pileup)
efficiency center column, center pixel group, 1GHz beam: (hit+pileup info)/particles = 99.8%
hit/particles = 99.1%A. Kluge
hitArbiter
A. Kluge
TDC: delay line, charge pump, enocoder, fine hitRegisters
layout placed in 300 µm column DLL code encoder added delay line & output buffer scheme power consumption
reduced to 19.7 mW per delay line TDC expert design review
charge pump, fine hit registers layout unmodified parallel read-out to hit registers added
startup state machine still need to be integrated delay line output to hit registers qualified and buffered bus structure to connect hitArbiter, TDC, hitRegisters
implemented and qualified
A. Kluge
TDC
A. Kluge G. Aglieri
TDC
A. Kluge G. Aglieri
TDC: delay line, charge pump, encoder, fine
hitRegisters
A. Kluge G. Aglieri
TDC: DLL & charge pump
A. Kluge L. Perktold
Fine hit registers
A. Kluge
G. Aglieri
TDC: encoder
A. Kluge
G. Aglieri
Read-out & configuration master Configuration master:
based on simple serial protocol being designed in standard cell at the
moment
Standard cell & custom cell read-out will be tackled after the afore mentioned blocks
A. Kluge
Verifications Single block verification (analog, digital) Full matrix and automatic functional
simulation (mixed mode, fully HDL based) using hitGenerator as particle stimulus using correct configuration data
SEU simulations
A. Kluge
Outlook & SummaryPixel matrix:
Front-end, trim DACs, inPixel configuration
Transmission line, receiver, hitArbiterTDC: delay line, charge pump,
hit registersRead-outChip assemblyFunctional & tape-out simulationsA. Kluge
A. Kluge
Implementation data transmission; 60bit/5IO Multi Serial60bit:
60 bits (8b10); 5 I/O pairs FIFO read-frequency for 50% contingency on 132 Mhits/s 50
MHz / quarter chip * 60 bit /5 pairs (10 bits serializer) 3000 /5 = 600 MHz per LVDS pair
Input frequency comes from PLL or from outside, either 2.4 Gbit/s on pad or 480 MHz for all pads & synchronous logic
if synchronous logic works with 480 MHz only 480 MHz * 5 = 2400 Mbit/s / 60 40 Mhits/s (21 % (132 Mhits/s) +54 % (104 Mhit/s))
Worst case synchronous logic works with 320 MHz only 320 MHz * 5 = 1600 Mbit/s / 60
26.7 Mhits/s (-19 % (132 Mhits/s) +3 % (104 Mhit/s)) synchronous logic works with 240 MHz only 240MHz * 5 = 1200 Mbit/s / 60
20 Mhits/s (-39 % (132 Mhits/s) -23 % (104 Mhit/s))