Update on the Design Implementation Methodology for the 130nm process Microelecronics User Group...

transcript

Update on the Design Implementation Methodology

for the 130nm process

Microelecronics User Group meetingTWEPP 2010 – Aachen

Sandro BonaciniCERN PH/ESE

sandro.bonacini@cern.ch

Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

Motivation

Mixed Signal Design flow methodology Open Access based

Implementation of Digital-On-Top ASICs Script based flow

Using the IBM 130 nm standard cell library

Design flow components Tools

Virtuoso 6.1.3 (OA based) SOC Encounter 8.1 (velocity) Conformal 8.1 EXT 8.1.4 (QRC) Assura 3.2 Calibre 2009.3

Design Kits IBM CMOS8RF DM design kit V1.7

3 thin, 2 thick, 3 RF metals. IBM CMOS8RF LM design kit V1.7

6 thin, 2 thick metals.

Enhancements Digital library

I/O pads Implement missing Cadence/Virtuoso views

Functional and symbol views for simulation Fixed existing views

Pin mismatches of power pads Abstract power pin width Layout fixes

New corner cells with 45 degrees bend Standard cells

New filler cells conforming to PC & RX pattern density rules New double vias for denser routing / better yield

Enhancements Implementation flow

Added support for multiple power domains Analog, digital, …

Support for P&R of mixed signal ASICs and third-party IP blocks Better integration between Virtuoso and Encounter

Automatic final netlist import into Virtuoso Automated physical verification

DRC and LVS Other fixes

Scan chain reordering Antenna rule definition for Encounter Two-steps routing for DM metal stack to avoid antenna violations

1st pass on 3 metals (only thin) 2nd pass on 5 metals (thin+thick)

“Digital on Top” Design Flow

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SOC_EncounterChip Design

VirtuosoAnalog Block Creation

Access

RTL synthesis

Floorplanning& power routing

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

SignoffRC extraction

Timing analysis

Clock tree synthesis

Routing

Timing optimization

Tape-out

Automated task

User task

Logical Equivalence

Checking

RTL synthesis

Floorplanning& power routing

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

Timing analysis

Routing

Timing optimization

Tape-out

Automated task

User task

Logical Equivalence

Checking

Mixed-signal example design

Analog IP block: DAC Digital IP block: SRAM Digital block: I2C slave

Synthesizable RTL code Triple Module Redundancy

Two separate power supplies Analog, digital

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A realistic example of a Mixed Signal ASIC to demonstrate the design flow:

Synthesis: RTL Compiler [rc] Timing constraints:

Clock definitions Input delays,

fanout, transition, etc.

Output load, etc.

Design import: Encounter Reference design used in the AMS

workshop: I2C slave connected to

SRAM DAC (with separate analog power supply) registers

DACSRAM

Floorplanning & power routing

Define Chip/core size target area utilization I/O placement module placement in

case of TMR or other special constraints

Power planning/routing Core/block rings and

stripes DAC SRAM

Power/ground connections

Placement

Tap cellsStandard

cellsScan-chain reordering

Placement

Scan-chain reorder

Open AccessFloorplannedDesign [.oa]

Connect cells power/ground

Add tap cells

Open AccessPlaced

Design [.oa]

Reports

Placement

Scan-chain reorder

Open AccessFloorplannedDesign [.oa]

Connect cells power/ground

Add tap cells

Open AccessPlaced

Design [.oa]

Reports

Multiple power domains

Analog & digital blocks

Separate power supplies.

Insertion of Power Breaker peripheral pads.

DACSRAM

Clock tree synthesis & signal

routing

Routing onthin metals

Routing on all metals

Timing optimization

Open AccessPlaced

Design [.oa]

Routing

Open AccessRouted

Design [.oa]

Timing optimization

Reports

Timing optimization

Open AccessPlaced

Design [.oa]

Routing

Open AccessRouted

Design [.oa]

Timing optimization

Reports

DFM: Antenna fix

Re-routes long nets Inserts tie-down

diodes

Cells & metal fill

Open AccessRouted

Design [.oa]

Antenna fix

Via optimization

Timing analysis

Open AccessFinal

Design [.oa]

Signoff timingreport

Delay file[.sdf]

Final netlist[.v]

Cells & metal fill

Open AccessRouted

Design [.oa]

Antenna fix

Via optimization

Timing analysis

Open AccessFinal

Design [.oa]

Signoff timingreport

Delay file[.sdf]

Final netlist[.v]

Via optimization

Cells & metal fill

Back to Virtuoso !

ASIC design is present in Virtuoso. Scripts take care of

changing abstracts into real layouts

Automatic import of netlist

DAC SRAM

Calibre DRC – Assura LVS

Thank you…

Implementation of digital-on-topmixed signal ASICs Using the IBM 130 nm standard cell library Defined methodology compatible with mixed signal

design flows Presented in the AMS courses

Future plans Add signal integrity checks

Celtic Automate additional DRC checks (ortho/grid, …)

Update on the Design Implementation Methodology for the 130nm process Microelecronics User Group...

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