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transcript
NTU GIEE EECS
VLSI Crash Course
Synthesis
Yi-Long Liou
Energy-Efficient Circuit and System Lab
Jul. 17, 2018
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Reference
Modify from
Computer-Aided VLSI System Design (CVSD)
Logic Synthesis with Design Compiler (CIC)
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Outline
Introduction
Synopsys Graphical Environment
DC-TCL: Introduction
Setting Design Environment
Setting Design Constraints
Synthesis Report and Analysis
Gate-Level Simulation
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Outline
Introduction
Synopsys Graphical Environment
DC-TCL: Introduction
Setting Design Environment
Setting Design Constraints
Synthesis Report and Analysis
Gate-Level Simulation
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Cell-Based Design Flow
Logic synthesis
Place&Route
Gate-Level netlist
Post layout
Gate-Level netlist
GDS layout
RTL code always @ (posedge clk)
if (in1==1)
a=c+d
else
a=c-d
Formal
Formal
LVS
RTL Simulation
Lint check
code coverage analysis
Gate level Simulation
Static Timing Analysis
Power Analysis
Gate level Simulation
Static Timing Analysis
Power Analysis
Extraction
DRC
transistor netlist
Tape out
Transistor-level Simulation
Transistor-level STA
Power Analysis
Implenentation Verification
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Synthesis Design Flow
Specification
RTL Coding Prepare
Setting Design Environment
Setting Design Constraint
Compile Design
Analysis
Cell
Library
Gate-level Cell-based Netlist
Develop the HDL design description
and simulate the design description
to verify that it is correct
Set up the .synopsys_dc.setup file.
Set the appropriate technology,
synthetic, and symbol libraries, target
libraries, and link libraries.
Set the necessary compilation options,
including options to read in the input
files and specify the output formats.
Read the HDL design description
Define the design.
Set design attributes
Define environmental conditions
Set design rules
Set realistic constraints
(timing and area goals)
Determine a compile methodology
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What is Synthesis
source /usr/cad/synopsys/CIC/synthesis.cshrc
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What is Synthesis
Synthesis = translation + optimization + mapping
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Logic Synthesis Overview
+ - x / cos sin
c = a + b
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HDL Compiler
In schematic view, we can see the Verilog file is translated
into Design Compiler as Synopsys design block with a
GTECH library (the Synopsys default)
always @(reset or set) begin
if (reset)
y=1'b0;
else if (set)
y=1'b1; end always @(gate or reset)
begin
if (reset)
t=1'b0; else if (gate) t=d; end
HDL
Comipler
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Design Compiler
Design Compiler maps Synopsys design block to gate level
design with a user specified library
Technology
Library
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Design Compiler Interaction
Three ways to interface
Design Vision (GUI)
dc_shell (Legacy Interface)
Design
Compiler (DC)
dc_shell –t (TCL Interface)
Command line
GUI
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RTL Coding Related to Synthesis
Syntax
Each-variable is assigned in the same always block
Delay is for simulation, not for synthesis
Memory case: #1 in nonblocking block v.s +notimingcheck
Synopsys full_case / parallel_case
Partition for synthesis
Separate combinational and sequential part
Separate control and VLSI-design strategy
Register at input/output
Special-case needs constraint setting
Clock gating
Multi-cycle
False path
Asynchronous logic
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STA (Static Timing Analysis)
Sequential circuits are usually constrained by clock specify
1.CLK pin of Flop1 to D pin of Flop2
2.Input port to a D pin of Flop.
3.Q pin of flop to an output port
4.Input to output port through purely combinational logic
Clock cycle >= DFFclk-Qdelay + combinational delay + DFFsetup
DFFclk-Qdelay + combinational delay >= DFFhold
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Trade-off between Speed and Area
Synthesis is Constraint Driven
Technology Independent
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What .synopsys_dc.setup Defined
search_path: the path to search for unsolved reference library or
design
target_library: the ASIC technology that the design is mapped to
link_library: the library used for interpreting input description
Any cells instantiated in your HDL code
Wire Load or Operating Condition models used during synthesis
symbol_library: used during schematic generation
synthetic_library: designware library to be used
Other variables
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Synopsys Related Files
Set your .synopsys_dc.setup
set company "EECS“
set designer "Student“
set search_path “ . $Your_path/CBDK_TSMC018/SynopsysDC/db/ \
./Memory/ $search_path“
set target_library “ slow.db fast.db tpz973gvwc.db tpz973gvbc.db \
SRAM2048x20_slow_syn.db SRAM2048x20_fast_syn.db “
set link_library “ * $target_library dw_foundation.sldb “
set symbol_library “ tsmc18.sdb generic.sdb “
set synthetic_library “ dw_foundation.sldb “
set verilogout_no_tri true
set hdlin_enable_presto_for_vhdl "TRUE“
set sh_enable_line_editing true
keep 100
alias h history
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Outline
Introduction
Synopsys Graphical Environment
DC-TCL:Introduction
Setting Design Environment
Setting Design Constraints
Synthesis Report and Analysis
Gate-Level Simulation
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Invoke Design Vision
Linux%> dv &
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Optimization Using the Design Vision
File/Read or File/Analyze & File/Elaborate
Attributes – set up Design Environment & Goals
(record in script sdc files)
Analysis/Report - check if set up is OK
Analysis/Check Design
Tools/Design Optimization
Analysis/Report
File/Save
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Read File
Read netlists or other design descriptions into Design Compiler
File/Read
Support many different formats: Verilog: .v
VHDL: .vhd
System Verilog: .sv
EDIF
PLA(Berkeley Espresso): .pla
Synopsys internal formats
DB(binary): .db
equation: .eqn
state table: .st
Equivalent dc_shell command : dc_shell> read_file –format verilog lab1.v
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Analyze & Elaborate
Use analyze and elaborate to bring Verilog or VHDL
files into design compiler memory
Analyze does syntax checking and produces an
intermediate .syn .mr .pvl files to be stored in a
design library
Elaborate looks in the design library for the
intermediate file and builds the design up into
design compiler memory (as design block)
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Analyze
Check VHDL & Verilog for syntax
and synthesizability
Create intermediate .syn .mr .pvl
files and places them in library
specified – design library
File/Analyze
Equivalent dc_shell command : dc_shell> analyze -format verilog –library WORK counter.v
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Elaborate
Elaborate after analyze to
bring design into Design
Compiler memory using
generic components (GTECH)
Look in the design library for
intermediate file for design
specified
File/Elaborate
Equivalent dc_shell command : dc_shell> elaborate counter -architecture verilog -library WORK
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Describe the Design Environment
You can use Design Vision to constrain your design
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Link Design
Analysis/Link Design
Execute link -all before you optimize your design
To ensure all sub-elements of your hierarchical
design are available
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Check Design
Analysis/Check Design
Execute check_design before you optimize your design
Two types of messages are issued
Error
Error: In design ‘bcd7segs’, cell ‘decoder’ has more
pins than it’s reference ‘d1’ has ports
Warnings
Warning: In design ‘converter’, port ‘A’ is not
connected to any nets
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Compile the Design
The compile command optimizes and maps the current_design
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Report the Design
From Design report and Timing analysis, you can find the set
attributes and the results after optimization
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Outline
Introduction
Synopsys Graphical Environment
DC-TCL: Introduction
Setting Design Environment
Setting Design Constraints
Synthesis Report and Analysis
Gate-Level Simulation
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DC-TCL(Tool Command Language)
TCL script = sequence of commands
.synopsys_setup / my_script.tcl / DUT_syn.sdc
Separate line ; Comments #
GUI interface v.s. DC-TCL command
dv –f script.tcl
dc_shell>help get_* TCL Basics
Function arguments
Return string result
Variable Substitution
Syntax: $varName (set a b v.s set a $b)
Nested Commands
Syntax: [commands..] (set a “b-3 is [expr $b-3]”)
get_, all_ command syntax
Search the current design for names of the given object types
Syntax: [get_type [-hierarchy] [name_list]] (set_dont_touch [get_cells * -hier])
[all_inputs]…
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Design Objects
A circuit that performs one or more logical
functions
An instance of a design or library primitive within
A design
The name of the original design that a cell
instance “points to”
The input or output of a cell
input or output of a design
The wire that connects ports to pins and/or pins
to each other
Waveform applied to a port or pin identified as a clock
source
Design:
Cell:
Reference:
Port:
Pin:
Net:
Clock:
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Design Objects
Module TOP(A, B, C, D, CLK, OUT1);
input A, B,C, D, CLK;
output [1:0] OUT1;
wire INV0, INV1, BUS0, BUS1;
ENCODER U1 (.AIN(A), .BIN(B), .CIN(C), .DIN(D), .Q0(BUS0), .Q1(BUS1));
INV U2 (.A(BUS0, .Z(INV0))),
U3 (.A(BUS1, .Z(INV1)));
REGFILE U4(.D0(INV0), .D1(INV1), .CLK(CLK), .Q[0](OUT[0]), .Q[1](OUT[1]));
endmodule
clock port
reference and design
cell
wire
pin
pin cannot
appear by itself,
must accompany
with cell
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Design Objects Exercise
Make a list of all the ports in the design?{ get_ports A,B,CLK,SUM }
Make a list of all the cells that have the letter “U” in their name?
{ get_cells *U* ADDER/U1, DFF/U2 }
Make a list of all the nets ending with “CLK”? { get_nets *CLK CLK }
Make a list of all the “Q” pins in the design? { get_pins */Q U2/Q }
Make a list of all the references? { ADDER,DFF }
pin cannot appear by itself,
must accompany with cell
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Outline
Introduction
Synopsys Graphical Environment
DC-TCL: Introduction
Setting Design Environment
Setting Design Constraints
Synthesis Report and Analysis
Gate-Level Simulation
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Why Describes
the Real World Environment
Beware that the defaults are not realistic conditions
Input drive is not infinite
Capacitive loading is usually not zero
Consider process, temperature, and voltage (PVT) variation
The operating environment affects the components
selected from target library and timing through your
design.
The real world environment you define describes the
conditions that the circuit will operate within.
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Describing Design Environment (1/2)
set_load
set_output_delay
create_clock
1 set_operating_conditions
3 set_driving_cell 4
5 set_input_delay
set_wire_load_model
6 2
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Describing Design Environment (2/2)
For STA, every node should be known: • RC value
• Inside DUT: Tech lib 1. standard cell/external-IP 2. wire load model
• Outside DUT: • set_drive / set_driving_cell • set_load
• I/O delay • set_input_delay
• set_output_delay
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1. Setting Operating Condition
Attributes/Operating Environment/Operating Condition
Equivalent dc_shell command :
dc_shell> set_operating_conditions -max_library slow -max slow
-min_library fast -min fast
Name Process Temp Volt
Slow 1 125 1.62
Typical 1 25 1.8
Fast 1 -40 1.98
Step 1
Step 2
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2. Setting Wire Load Model
Wire load model estimates wire capacitance based on chip
area & cell fanout
Attributes/Operating Environment/Wire Load
Equivalent dc_shell command :
dc_shell> set_wire_load_model –name tsmc18_w10 –library slow
Step 1
Step 2
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Drive Strength & Load for Pads
Input Drive Strength for Pads Output Load for Pads
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3. & 4. Input Drive Strength & Output Loading
Consider for IO Pads (Synthesis w IO)
Setting Input Drive Strength
Setting Output Loading
Remember to add IO.db
into target_library in .synopsys_setup
dc_shell command :
dc_shell> set_driving_cell –library tpz973gvwc –lib_cell PDIDGZ –pin {C} [all_inputs]
dc_shell command :
dc_shell> set_load [load_of “tpz973gvwc/PDT16DGZ/I” ] [all_outputs]
c
TSMC18: PDIDGZ
pad
R
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Port Report
dc_shell command :
dc_shell> report_port -verbose {port_list }
Design/Report ports Step 1 Step 2
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STA (Static Timing Analysis)
Sequential circuits are usually constrained by clock specify
1.CLK pin of Flop1 to D pin of Flop2
2.Input port to a D pin of Flop.
3.Q pin of flop to an output port
4.Input to output port through purely combinational logic
Clock cycle >= DFFclk-Qdelay + combinational delay + DFFsetup
DFFclk-Qdelay + combinational delay >= DFFhold
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Input/Output Delay
Clock cycle >= DFFclk-Qdelay + c + DFFsetup
Clock cycle >= DFFclk-Qdelay + a + b + DFFsetup
Input delay = DFFclk-Qdelay + a
Clock cycle >= DFFclk-Qdelay + d + e + DFFsetup
Output delay = e + DFFsetup
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5. Setting Input Delay
Select input ports
Attributes/Operating Environment/Input Delay
Relative to clock trigger time
Equivalent dc_shell command :
dc_shell> set_input_delay –clock clk –max 6.4 [get_ports in1]
dc_shell> set_input_delay –clock clk –min 4.4 [get_ports in1]
Step 1 Step 2
Step 3
Attention!
The step should execute
after clock specify
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6. Setting Output Delay
Select output ports
Attributes/Operating Environment/Output Delay
Relative to clock trigger time
Step 1
Step 2
Step 3
Equivalent dc_shell command :
dc_shell> set_output_delay –clock clk –max 5.3 [get_ports out1]
dc_shell> set_output_delay –clock clk –min 4.4 [get_ports out1]
Attention!
The step should execute
after clock specify
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SDC about
Setting Design Environment
1 2 3 4 5 6
set cycle 20
set t_in [expr $cycle/2]
set t_out 0.5
# Constraint setting
# Clock constraints
create_clock -name clk -period $cycle [get_ports clk]
set_fix_hold
set_dont_touch_network
set_ideal_network
set_clock_uncertainty
set_clock_latency
[get_clocks clk]
[get_clocks clk]
[get_ports clk]
0.1 [get_clocks clk]
0.5 [get_clocks clk]
# Other constraints
set_max_fanout 6 [all_inputs]
# Environment setting
set_operating_conditions -min_library fast -min fast -max_library slow -max slow
set_wire_load_model -name tsmc13_wl10 -library slow set_drive
set_load 1 [all_inputs]
1 [all_outputs]
set_input_delay $t_in -clock clk [remove_from_collection [all_inputs] [get_ports clk]]
set_output_delay $t_out -clock clk [all_outputs]
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Outline
Introduction
Synopsys Graphical Environment
DC-TCL: Introduction
Setting Design Environment
Setting Design Constraints
Optimization Constraints
Basic clock constraints concept
Constraints & STA for Special Circuits
Constraint for Power & Area
Design Rule Constraint
Synthesis Report and Analysis
Gate-Level Simulation
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Basic Clock Constraints
Clock七大法則:
Period & Waveform
Fix timing issue:
Fix hold
Issue handled in P&R CTS Stage
Don’t touch
Set ideal network (告知DC無skew問題,之後利用uncertainty悲觀模擬解決)
Uncertainty
Skew
Latency
Source latency (option)
Network latency
Transition
Input transition
測試機台環境→適用whole system情況 DUT is submodule: set driving strength
Clock transition
In P&R,限制其後接的FF數
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Specify Clock Constrains
Select clock port
Attributes/Specify Clock
Step 1
Step 2
create_clock : define clock’s waveform
set_fix_hold : respect the hold time requirement of all clocked flip-flops
dc_shell> create_clock -name clk -period 10 -waveform {0 5} { clk } //2nd clk: ports name
dc_shell> set_fix_hold [ get_clocks clk]
set_dont_touch_network : do not re-buffer the clock network
dc_shell> set_ideal_network [ get_ports clk ]
set_ideal_network
dc_shell> set_dont_touch_network [ get_clocks clk ]
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STA (Static Timing Analysis)
Sequential circuits are usually constrained by clock specify
1.CLK pin of Flop1 to D pin of Flop2
2.Input port to a D pin of Flop.
3.Q pin of flop to an output port
4.Input to output port through purely combinational logic
Clock cycle >= DFFclk-Qdelay + combinational delay + DFFsetup
DFFclk-Qdelay + combinational delay >= DFFhold
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Clock Skew Issue
Arrival(FF1) = 0.5ns
Arrival(FF2) = 1.2ns
Arrival(FF1) = 1.2ns
Arrival(FF2) = 0.5ns
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Setting Clock Uncertainty
Different clock arrival time
Models clock skew effects on the clock
After CTS in P&R
real propagated skew is considered!
Experie
Small circuits: 0.1ns
Large circuits: 0.3ns
Timing report
Equivalent dc_shell command :
dc_shell> set_clock_uncertainty 0.1 [get_clocks clk]
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Setting Clock Latency
Equivalent dc_shell command :
dc_shell> set_clock_latency –source 3 [get_clocks clk]
dc_shell> set_clock_latency 1 [get_clocks clk]
Source latency
Network latency
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Combinational Circuit –
Max Delay Constraints
For combinational circuits only
Select the start & end points of the timing path
Attributes/Optimization Constraints/Timing Constraints
Equivalent dc_shell command :
dc_shell> set_max_delay 1 from [all_inputs] –to [all_outputs]
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Setting Area & Power Constraint
Attributes/Optimization Constraints/Design Constraints
Equivalent dc_shell command :
dc_shell> set_max_area 0
Area unit(follow unit defined in
library):
1. Equivalent gate counts Gate counts
= Chip Report Area / NAND2 Area
2. um x um
3. Transistors
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Design Rule Constraints
Design rules constraints can’t be violated at any cost, even if it
will violate the timing and area goal
Design rules constraints restrict how many cells are connected
to one another based on capacitance, transition and fanout
You may apply more conservative design rules to: Anticipate the interface environment your block will see
Prevent the design from operating cell close to their limits, where
performance degrades rapidly
Three kinds of design rule constraint are set:
set_max_transition
set_max_fanout
set_max_capacitance
set_max_transition 0.2 [get_ports IN1]
set_max_fanout 6 [get_ports IN1]
set_max_capacitance 2 [get_ports IN1]
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Constraints Priority
During the optimization, there exists a constraint priority
relationship.
Design Rule Constraint
(max_transition, max_fanout, max_capacitance)
Timing constraint (max_delay, min_delay)
Power constraint
Area constraint
Use set_cost_priority command to modify the order
Equivalent dc_shell command :
dc_shell> set_cost_priority [ -default] [-delay] [cost_list] EX : set_cost_priority {max_fanout max_capacitance max_delay}
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SDC about Setting Design Constraint
set cycle 20
set t_in [expr $cycle/2]
set t_out 0.5
# Constraint setting
# Clock constraints
create_clock -name clk -period $cycle [get_ports clk]
set_fix_hold
set_dont_touch_network
set_ideal_network
set_clock_uncertainty
set_clock_latency
[get_clocks clk]
[get_clocks clk]
[get_ports clk]
0.1 [get_clocks clk]
0.5 [get_clocks clk]
# Other constraints
set_max_fanout 6 [all_inputs]
# Environment setting
set_operating_conditions -min_library fast -min fast -max_library slow -max slow
set_wire_load_model -name tsmc13_wl10 -library slow set_drive
set_load 1 [all_inputs]
1 [all_outputs]
set_input_delay $t_in -clock clk [remove_from_collection [all_inputs] [get_ports clk]]
set_output_delay $t_out -clock clk [all_outputs]
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Check Design
After you set up the deign attributes & design
constraints, we recommend the next step is to
check design
Analysis/Check Design
Example: multiple instance
How to handle ?
uniquify
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Uniquify
Create a unique design file for each instance
May select one cell or entire design hierarchy to be uniquify
Allow design to be customized to its interface
Select the most top design of
the hierarchy
Hierarchy/Uniquify/Hierarchy
Step 1
Step 2
Equivalent dc_shell command :
dc_shell> uniquify
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Check Constraints & Attributes
Use the following reports to check constraints & attributes
before compiling
Deign/Report Constrants
Step 1
Step 2
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Save Constraints & Attributes
Save attributes & constraints setting as the design setup file
in TCL command format
File/Save Info/Design Setup
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Another method
Execute Script File
Execute TCL command script file, use
File/Execute Script
Step 1
Step 2
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Compile
Equivalent dc_shell command :
dc_shell> compile –exact_map –map_effort high –bounaray_optimization
Step 1 Step 2
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Assign Problem
The syntax of “assign” may cause problems in the LVS
Equivalent dc_shell command :
dc_shell> set_fix_multiple_port_nets -all -buffer_constants
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Floating Port Removing
Due to some ports in the standard cells are
not used in your design
Equivalent dc_shell command :
dc_shell> remove_unconnected_ports -blast_buses [get_cells -hierarchical *]
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Change Naming Rule
Purpose: Let the naming-rule definitions in the gate-level
netlist are the same as in the timing file (e.g. *.sdf file)
Also, the wrong naming rules may cause problems in the LVS
Bus[5] → Bus_5_
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Report Timing Path clock or reset has big delay
set_ideal_network
Problem: High Fan-out Net
report_net_fanout –high_fanout
compile –inc –map_effort high
1. set hign_fanout_net_threshold 0
2. Find high fanout net
report_net_fanout –high_fanout
set_dont_touch_network
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Outline
Introduction
Synopsys Graphical Environment
DC-TCL: Introduction
Setting Design Environment
Setting Design Constraints
Synthesis Report and Analysis
Gate-Level Simulation
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Timing Report
Timing/Report Timing Path
Step 1
Step 2
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Timing Report (from STA)
Start End
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Area Report
Don’t care net area!
External IP
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Outline
Introduction
Synopsys Graphical Environment
DC-TCL: Introduction
Setting Design Environment
Setting Design Constraints
Synthesis Report and Analysis
Gate-Level Simulation
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Gate-Level Simulation (Verilog)
Write out gate-level netlist
1. File/Save As Verilog
2. > write -format verilog -hierarchy -output chip_syn.v
Get SDF(Standard Delay Format)
> write_sdf –version 2.1 chip_syn.sdf
Modify your testbench file to include timing delay(Back annotate)
$sdf_annotate (“the_SDF_FILE_NAME”, top_module_instance_name);
Gate level simulation with timing information:
>> ncverilog testbench.v chip_syn.v –v tsmc18.v +access+r
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Thanks for Listening