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P LUG -AND -P LAY DIGITAL C ONTROLLERS FOR SCALABLE L OW -P OWER
SWITCH -M ODE P OWER SUPPLIES
by
Jason Weinstein
A thesis submitted in conformity with the requirements for the degree of
Master of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto
Copyright by Jason Weinstein, 2009
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ABSTRACT
Plug-and-Play Digital Controllers for Scalable Low-Power Switch-Mode Power Supplies
by
Jason Weinstein
Master of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto
2009
The purpose of this thesis is to present a novel controller structure for scalable switch-mode
power supplies targeting low power applications. The design employs masterless control,
where each phase is responsible for its own control in a multiphase system. The controller is
capable of automatically configuring itself to work with a single phase system or a
multiphase system. The configuration process allows each controller to determine the
number of phases in the system, as well as to synchronize and sequence the phases. With
this architecture, the same controller design can be used in many types of applications
requiring different numbers of phases, resulting in a decrease in cost and design effort. The
proposed design has been verified experimentally on FPGA and IC implementations.
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DEDICATION
Dedicated in memory of my mother, Livia Singer.
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Acknowledgements
I could not have completed this work without the help of others. First, I would like to thank
my supervisor, Prof. Aleksandar Prodi , for providing me with this opportunity. His
guidance, knowledge, and support have truly gone above and beyond my expectations.
I would also like to thank my friends in the Laboratory for Low-Power Management and
Integrated Switch-Mode Power Supplies. In particular I would like to acknowledge Zdravko
Lukic, Amir Parayandeh, and Massimo Tarulli for their invaluable assistance with
completing this work.
Finally, I would like to thank the Department of Electrical and Computer Engineering as well
as Toshiba Corporation for sponsoring this project.
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TABLE OF CONTENTS
1. Introduction ....................................................................................................................... 1
1.1 Thesis Objectives ................................................................................................... 1
1.2 Thesis Overview .................................................................................................... 2
2. Prior Art and Motivation ................................................................................................. 3
2.1 Multiphase SMPS Systems .................................................................................... 3
2.2 Scalable SMPS Systems ......................................................................................... 8
2.3 Modular DC-DC Converters for Medium to High Power Applications ................ 9
2.4 Scalable Low-Power SMPS Systems ................................................................... 10
2.5 Auto-Tuning Controllers for SMPS ..................................................................... 13
3. System Description .......................................................................................................... 15
3.1 System Overview ................................................................................................. 15
3.2 System Benefits .................................................................................................... 19
3.3 Component Descriptions ...................................................................................... 20
3.3.1 Communication Block .............................................................................. 20
3.3.1.1 Communication Protocol ............................................................. 22
3.3.1.2 Transmitter and Receiver ............................................................. 24
3.3.1.3 Transmission Gate ....................................................................... 26
3.3.2 Phase Detector .......................................................................................... 29
3.3.2.1 Phase Detection Process .............................................................. 29
3.3.2.2 Starting Phase Identification ........................................................ 31
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3.3.3 LC Estimator and Sequencer .................................................................... 36
3.3.3.1 Charged-Based Inductance Estimation Method ........................... 37
3.3.3.2 LC Estimator and Sequencer Architecture .................................. 41
3.3.4 Digitally-Controlled DLL ......................................................................... 46
3.3.4.1 Selection of the Timing Phase ..................................................... 47
3.3.4.2 Clock Generation Architecture .................................................... 48
3.3.5 Regular Operation .................................................................................... 53
4. Experimental Verification and Results ......................................................................... 56
4.1 Experimental Systems .......................................................................................... 56
4.1.1 FPGA-Based Implementation .................................................................. 56
4.1.2 IC Implementation .................................................................................... 57
4.1.2.1 Chip Overview ............................................................................. 57
4.1.2.2 On-Chip Components .................................................................. 60
4.2 Experimental Results ........................................................................................... 62
4.2.1 Single Phase Operation ............................................................................ 63
4.2.2 Multiphase Operation ............................................................................... 65
4.2.3 Phase Sequencing ..................................................................................... 69
4.2.4 Communication Protocol .......................................................................... 74
5. Conclusion ....................................................................................................................... 76
5.1 Thesis Summary and Contributions ..................................................................... 76
5.2 Future Work ......................................................................................................... 77
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Appendix A: Verilog HDL for Digital Blocks ............................................................... 80
Appendix B: Gate-Level Netlist for Communication Block ...................................... 128
Appendix C: PCB Board and Schematics ................................................................... 135
References ............................................................................................................................ 140
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LIST OF TABLES
Table 3.1: Communication block inputs and outputs ................................................................... 27
Table 3.2: An example of phase reordering based on charge times with 4 phases. ...................... 46
Table 3.3: Required output frequencies and periods for a system operating at a switching
frequency of 1 MHz for various numbers of phases. .................................................................... 48
Table 4.1: Chip area required by each component ....................................................................... 60
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LIST OF FIGURES
Figure 2.1: Multiphase buck converter with n phases .............................................................. 4
Figure 2.2: A comparison of interleaved and non-interleaved switching ................................. 6
Figure 2.3: Centrally controlled scalable SMPS system ......................................................... 11
Figure 3.1: System overview .................................................................................................. 16
Figure 3.2: Block diagram of the plug-and-play controller .................................................... 17
Figure 3.3: Flowchart showing the general operation of each plug-and-play controller ........ 18
Figure 3.4: Communication block diagram ............................................................................ 21
Figure 3.5: Example of a data transmission of the value 4b1010 .......................................... 24
Figure 3.6: A comparison of series mode and bus mode with four phases ............................ 28
Figure 3.7: The phase detection process with four phases ...................................................... 31
Figure 3.8: PCB routing for starting phase identification ....................................................... 33
Figure 3.9: PCB routing for starting phase detection using a RC filter .................................. 34
Figure 3.10: Starting phase detection done with an RC filter ................................................. 35
Figure 3.11: Ripple cancelation for a 6-phase system with identical inductances ................. 39
Figure 3.12: Combined ripple for a 6-phase system where 2 consecutive phases have
different inductance values ..................................................................................................... 40
Figure 3.13: Ripple cancelation in a 6-phase system with optimized phase sequencing ....... 40
Figure 3.14: The charging and discharging process for estimating the LC products ............. 43
Figure 3.15: Flowchart for the phase sequencing algorithm ................................................... 45
Figure 3.16: Digitally-Controlled DLL block diagram ........................................................... 49
Figure 3.17: Flowchart of the operation of the Digital Frequency Compensator .................. 52
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CHAPTER 1: I NTRODUCTION 1
Chapter 1
Introduction
The topic of this thesis is the design and practical implementation of plug-and-play digital
controllers for scalable low-power switch-mode power supplies (SMPS). The objective is to
produce a controller capable of operating both in single phase mode as well as multiphase
mode, with a variable number of phases. As a result, the same controller design can be
reused in applications requiring one or only a few phases in addition to those requiring many
phases.
1.1 Thesis Objectives
The aim of this thesis is to develop a scalable architecture for low-power applications.
Scalable controllers have been adopted for medium to high power applications, but have not
yet been widely employed for low-power SMPS (applications consuming between several
watts and several hundred watts of power) partly due to the challenges relating to auto-
configuration and synchronization of power modules. The goal of this work is to introduce a
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CHAPTER 1: I NTRODUCTION 2
solution to these challenges that is cost-effective for a wide range of low-power applications.
Another objective is to allow the design to be easily modified to work with other features in
the future, such as current-programmed mode control and auto-tuning compensation.
1.2 Thesis Overview
The thesis proceeds in Chapter 2 with an overview of multiphase systems and existing
solutions for scalable power systems. Motivation for the masterless approach for scalable
low-power SMPS controllers is provided. Chapter 3 proposes a novel design for a scalable
controller. An overview of the system is provided, as well as descriptions of its key
components. In Chapter 4 FPGA and IC prototype systems are presented and experimental
results are demonstrated, verifying the functionality of the proposed system. Finally, Chapter
5 highlights the major elements of this thesis and recommends potential related work for the
future.
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CHAPTER 2: PRIOR ART AND MOTIVATION 3
Chapter 2
Prior Art and Motivation
In this chapter, the goals of multiphase SMPS are explained. The tradeoffs between
multiphase and single phase systems lead to the desire for scalable solutions. Existing
solutions for scalable converters have allowed flexibility in terms of the number of phases in
a converter, but have several drawbacks that limit their use in a wide range of practical low-
power applications.
2.1 Multiphase SMPS Systems
A popular practice in the implementation of SMPS systems is to place two or more power
stages, or phases, in parallel to form a multiphase system, as shown in Figure 2.1.
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CHAPTER 2: PRIOR ART AND MOTIVATION 4
Figure 2.1: Multiphase buck converter with n phases
In a multiphase system, two or more power stages are arranged such that they share a
common input voltage source and a common output load. This is in contrast to a single
phase system, which contains only one filter and requires only one switching signal (or one
set of switching signals in the case of a synchronous rectified single phase system). The
phases are connected in parallel and have separate switching networks and LC filters. This
paralleling results in many important advantages compared to a single phase system [1]:
The output voltage ripple is reduced through the interleaving of the phases.
Interleaving denotes that the switching sequences of the phases are evenly spaced
from each other over the course of one switching cycle. As an example, Figure 2.2
illustrates interleaving with 3 phases, where the switching signals of the phases are
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CHAPTER 2: PRIOR ART AND MOTIVATION 5
placed 120 apart from each other. This advantage has an important implication: the
value of the output filter can be reduced while still satisfying the maximum ripple
requirement, resulting in a reduction in cost and size.
The dynamic response of the system can be improved. For a multiphase system with
n phases each with an inductance L, the total equivalent inductance is L/n, which
enables the system to respond faster to load changes. Also, with interleaved
switching signals, oversampling (sampling more than once per switching cycle) can
allow a faster system response since the duty ratio can be effectively updated more
than once per switching cycle. The input filter requirements are minimized through interleaving. In Figure 2.2, the
current drawn from the input source is shown for the case with 3 phases where an
interleaved switching pattern is used and for the case where all phases are switched
simultaneously, in phase with each other. In the case where interleaving is employed,
the peak magnitude of the current is 3 times smaller compared to the non-interleaved
case. Also, the frequency is 3 times larger. As a result, the size of the input filter
capacitor can be reduced. The purpose of this filter is to minimize noise as well as to
ensure that the input voltage remains stable.
Power efficiency can be improved by dynamically adding or dropping phases. For
applications with widely varying load conditions, high efficiency can be achieved
over the full operating range by turning phases on or off depending on the output
current, resulting in a higher and flatter efficiency curve. For example, at light loads,
running a SMPS with fewer phases will generally result in better efficiency.
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Multiphase systems can provide redundancy. With an intelligent controller, if one or
more phases fail, the remaining phases can continue to deliver the required power.
Heat distribution is improved in multiphase systems. Since the current is shared
among a number of phases, heat dissipates across a larger area, often eliminating the
need for a heat sink. Further, the need for expensive semiconductor switching
devices with very high current ratings is eliminated.
Due to improved heat distribution, for a given area multiphase systems have higher
current ratings.
Figure 2.2: A comparison of interleaved and non-interleaved switching
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CHAPTER 2: PRIOR ART AND MOTIVATION 7
The above advantages apply when comparing multiphase systems to single phase systems, as
well as when comparing a multiphase system with a large number of phases to another with
fewer phases.
The advantages of multiphase operation, however, come at a cost. Multiphase systems have
the following drawbacks compared to their single phase counterparts:
A larger number of components is required as each phase is added. Specifically,
additional power switches, gate drivers, and LC filter components are needed for each
additional phase (although the total size of the components does not necessarily grow
linearly with the number of phases).
The control of multiphase systems is more challenging, resulting in higher complexity
and cost in the controller. This is due mainly to the presence of multiple switching
networks.
Due to the many tradeoffs between single phase and multiphase systems of various sizes,
there is no single optimal number of phases for all SMPS applications. The number of
phases should be chosen only after carefully considering the requirements of each particular
application.
For example, a desktop computer would likely employ a multiphase SMPS to deliver power
to its state-of-the-art multicore processor. Modern processors can draw peak currents of 70
A or more [2]. In this type of application, the high current rating of the load would likely
outweigh the extra cost and space requirements of the multiphase converter. A cellular
phone, on the other hand, would most likely use a single phase power supply to deliver
power to its components. This type of application would have a relatively small current
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CHAPTER 2: PRIOR ART AND MOTIVATION 8
requirement. Furthermore, the size restriction due to portability combined with the
downward pressure on price would make a single phase system the better choice.
2.2 Scalable SMPS Systems
The advantages and disadvantages between multiphase and single phase systems (or between
multiphase systems with larger and smaller numbers of phases) bring about the appeal for
scalable SMPS systems. The idea is to allow a controller to be used in a system with a
number of phases that can vary within a specified range. This results in two significant
advantages.
Firstly, the same controller can be used for many different kinds of applications. If the
controller is capable of operating with, for example, anywhere from 1 to 10 phases, it can be
used in both low current and high current applications. The controller could be used in single
phase mode for powering a cellular phone. On the other hand, the controller could
alternatively be configured with more phases to deliver the necessary current to a computer
processor. In these cases, multiple unique, non-scalable controller designs could be replaced
with one scalable controller design. The advantage in this is the design re-use of the
controller. A single scalable controller design can be used in many different applications,
whereas a non-scalable controller with a fixed number of phases would need to be designed
with a specific number of phases for each new kind of application. A scalable design could
result in a significant savings in cost and time with the design and verification process.
Secondly, with a scalable controller, the number of phases can be changed as the power
requirements of an application vary. With a traditional non-scalable controller, when the
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CHAPTER 2: PRIOR ART AND MOTIVATION 9
current requirements of the load exceed the rated maximum value, the entire power supply
needs to be replaced. In contrast, with a scalable system, phases can be added or removed as
needed. For example, in the past it has often been the case that a new generation of computer
processors has a larger current requirement compared to the previous generation. If a
processor is upgraded to the latest generation, the new current requirements may exceed the
power supplys rating. With a non-scalable system, the entire power supply would need to
be replaced as well. On the other hand, with a scalable system, one or more phases could be
added, with the original hardware remaining intact. This could result in a considerable
savings in cost compared to a non-scalable system. There could also be a decrease in theenvironmental impact over the life cycle of the computer. With a non-scalable system, the
hassle of needing to replace the power supply in the future could be avoided by
overdesigning the system to have a power rating exceeding the present requirements,
however, this would result in an increase in cost.
2.3 Modular DC-DC Converters for Medium to High
Power Applications
Modular solutions have been developed for dc-dc conversion suitable for medium to high
power applications [3,4,5,6,7]. These solutions offer the advantage of allowing the user to
plug in additional modules to deliver the necessary power for a specific application. This
allows the same design to be reused in different kinds of applications and for the power
system to be easily changed as the applications power requirements vary over time.
However, the previously presented architectures are only suitable for medium to high power
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CHAPTER 2: PRIOR ART AND MOTIVATION 10
loads, such as automotive and telecommunications applications. They cannot be used
directly for portable or low-power applications such as cellular phones or laptop computers
due to their size, cost, losses, and voltage capabilities. [3] offers a scalable DC-DC solution,
but only provides output voltages of 24V, 28V, and 48V, making it unsuitable for portable
applications. A dynamic response of 1ms is achieved, which is poor compared to existing
state-of-the-art low-power switch-mode power supplies. [4] provides an output voltage of
46-52V, also too high for portable applications. Its dimensions (112mm x 44mm x 282mm)
and weight (1.1kg) also make it unsuitable for the applications of interest. In [5], the system
is designed for higher voltage and higher power automotive applications. The semiconductor components of the power stage are unsuitable for low-voltage applications. [6] presents
another modular dc-dc converter targeted for automotive applications that would require
overly complex hardware and would be too large for portable applications. It would also not
be suitable for producing the low output voltages required in many of todays portable
applications.
2.4 Scalable Low-Power SMPS Systems
Solutions for scalable low-power SMPS controllers have been recently developed
[8,9,10,11,12,13]. These systems employ centralized control, meaning that one chip is
responsible for controlling all phases present in the system. This type of system is depicted
in Figure 2.3.
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CHAPTER 2: PRIOR ART AND MOTIVATION 11
Figure 2.3: Centrally controlled scalable SMPS system
In this system, a central controller capable of operating with a variable number of phases is
employed. The key outputs of the controller are the pulse-width modulated switching signals
transmitted to each of the power stages ( MS 1, SR1, ..., MS n, SRn). These signals would be
connected directed to the gate drivers of the phases in Figure 2.1. The central controller is
responsible for compensating the pulse-width modulated switching signals for all phases in
order to achieve the desired output voltage. Ideally, the central controller should produceinterleaved switching signals in order to realize many of the advantages of multiphase
systems discussed in 2.1.
The central controller in Figure 2.3 can be made scalable, meaning that it can be capable of
operating with any number of phases from 1 to n, where n is the maximum number of phases
supported. The centrally controlled SMPS system of Figure 2.3 achieves the advantages of
scalability described in 2.2. The same controller can be used for different applications where
the number of phases ranges from 1 to n. Also, if the power requirements vary over time,
power stages can be added or removed and the controller can be reprogrammed to support
the new number of phases.
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CHAPTER 2: PRIOR ART AND MOTIVATION 12
However, the centrally controlled method results in a major drawback. In order to support a
large number of phases, the pin count of the controller must be sufficiently large. For a
multiphase synchronous buck converter system, there must usually be at least 2 pins
dedicated on the controller chip for each phase supported (one pin for each of the switching
signals). In practice, each supported phase would likely require more than 2 pins. To
measure the current of each phase, 2 additional pins would most likely be required, for a total
of at least 4 pins per phase. Measuring phase currents might be required for current-
programmed mode control, for achieving even current distribution among all phases, and for
over-current protection. This means that the pin requirements of the chip grow proportionally with the maximum number of phases supported. As the pin count of the
controller grows, the chip area will become pad-limited, meaning that extra silicon area
would be required, even if the additional area is not required for the controllers circuitry.
This extra silicon would result in a higher cost for each controller produced. As a result, a
scalable central controller that supports many phases would not be economically feasible for
applications requiring only a few phases. In addition, the power consumption of such a large
chip would be too high to achieve adequate efficiency for a single phase low power SMPS.
A centrally controlled scalable system would only be cost effective if it were scalable over
only a small range of phases, which would partially negate the advantages of scalable
systems.
Also, it is not be feasible to integrate gate drivers and MOSFETs into a centralized controller
that is scalable to support a large number of phases. The integration of gate drivers and
MOSFETs is a desirable feature because it reduces the component count of the power supply.
To support, for example, up to 10 phases, the controller would require 10 gate drivers and 10
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CHAPTER 2: PRIOR ART AND MOTIVATION 13
MOSFETs. If these components were integrated with the controller, this would result in an
extremely large chip area requirement, which would make the chip too costly for operation
with a single phase or only a few phases. Also, this solution would result in poor heat
distribution.
2.5 Auto-Tuning Controllers for SMPS
In recent years, auto-tuning algorithms have been developed for digital SMPS controllers
[14,15,16,17,18]. These auto-tuning algorithms allow the operation of the controller to be
tuned dynamically, such that near optimal performance can be achieved even if the power
stage parameters vary. In [18], for example, information about the power stage is extracted
by intentionally introducing oscillations through limit cycling. This information is
subsequently used to adjust the compensator. In [15] the compensator is adjusted using
information obtained through relay operation of the system.
Auto-tuning is a desirable feature because the parameters of a power stage can vary greatly
from their nominal values. For example, if the capacitor or inductor values differ from their
nominal values, the power stage will have a different corner frequency, which would affect
the dynamic performance of the power supply. As a result, systems without auto-tuning
usually need to be designed with the worst case scenario in mind to ensure stability, resulting
in sub-optimal dynamic response and efficiency. An alternative to auto-tuning could be to
use power stage components with very tight tolerances. However, this would lead to an
increase in cost and may not necessarily mitigate fluctuations due to temperature and aging.
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CHAPTER 2: PRIOR ART AND MOTIVATION 14
In the context of scalable multiphase systems, these auto-tuning algorithms can be valuable
since the dynamic characteristics of the system can vary not only due to component
tolerances but also due to the number of phases present in the system. The addition or
removal of phases results in different plant characteristics due to the interleaving switching
pattern in a multiphase converter as well as the parallel placement of multiple output filters.
Auto-tuning controllers could potentially be used to re-tune the systems compensation as
phases are added or removed from a multiphase system, resulting in optimized performance
over a wide phase count range.
Auto-tuning can also be used to configure the phases in a multiphase system in such a way
that the output ripple is reduced. In [19] a method is presented to minimize the ripple by
sequencing the phases in a manner that ensures that the output ripple is minimized.
These auto-tuning controllers, however, can potentially provide only a part of the solution for
the realization of plug-and-play scalable controllers. They do not address other practical
issues such as phase counting, phase synchronization, and inter-phase communication, which
are the main focus of this thesis.
The design of plug-and-play digital controllers can be divided into two challenges:
communication/system management and system control. The problem of system control is
being investigated by other members of our lab and does not fall within the scope of this
thesis. The thesis will investigate the communication and system management for plug-and-
play digital controllers for scalable converters.
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CHAPTER 3: SYSTEM DESCRIPTION 15
Chapter 3
System Description
3.1 System Overview
In this chapter, an overview of the systems design and operation is provided. The system,
shown in Figure 3.1, consists of one or more phases operating in an interleaved fashion.
Each phase comprises a power stage and a controller. The power stage includes a pair of
switches and a filter. The controllers of each phase are identical. The system operates
masterlessly, such that each phase is responsible for the control of its own switching pulses.
In order to synchronize the operation and provide a means for sharing information, the
controllers are linked through a one-wire communication line.
The design is a plug-and-play system, meaning that any number of phases can be
configured and the system will operate appropriately. It should be noted that the system does
not support hot-swapping, where phases can be added or removed while the system is
operating and supplying power.
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CHAPTER 3: SYSTEM DESCRIPTION 16
Ln L1
L5Phase 5
L2Phase 2
vout (t )
L3 L4
Phase 1
Phase 4 Phase 3
Sync/ comm.line
Phase n
Plug & playcontroller
line 1
line 2
vout (t )
V g
Out
Out 1
Out 2
Out 3
L o a
d
+
V g
Out 4
Out 5
Out n
Figure 3.1: System overview
Figure 3.2 illustrates the structure of each phase. It is a modification of a conventional
single-phase voltage mode controller. Since all controllers are identical, they each contain
the same components depicted in Figure 3.2. Data is transmitted and received using the dual-
mode Communication Block . The Communication Block is responsible for both transmitting
and receiving data. It is capable of operating in two modes: bus mode and series mode. The
communication mode in use at any point in time depends on the state of the switch S 1.
During initialization, the Phase Detector sets the scalable controllers into a ring
configuration in order to determine the number of phases present in the system. Once the
phase detection process has been completed, the Phase Detector closes the switch S 1 to allow
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CHAPTER 3: SYSTEM DESCRIPTION 17
bus communication. Next, the LC Estimator and Sequencer Block uses a charge-based
algorithm to detect the relative ratios of the phase inductor values. Based on this
measurement and those of the other phases, which are shared on the bus, each phase
independently determines its own unique position in the switching sequence of the entire
structure. The goal of reordering the phases is to minimize the total output ripple of the
converter.
Figure 3.2: Block diagram of the plug-and-play controller
Next, one of the phases is selected as the timing phase. The timing phase uses its Digitally-
Controller DLL to produce a clock signal with a frequency of nf s, where n is the number of
phases in the system and f s is the switching frequency. This clock signal is used to time when
data is transmitted onto the bus. The timing of the data transmissions is important in order to
achieve interleaved operation. After the Digitally-Controlled DLL has locked to the correct
frequency, regular operation of the system begins. At this point, all phases constantly
monitor the bus to determine when they should begin their respective switching periods. The
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CHAPTER 3: SYSTEM DESCRIPTION 18
error signal, e[n], is also transmitted across the bus. As is the case in a conventional single-
phase voltage mode controller, e[n] is sent to the compensator, which produces a control
signal for the digital pulse-width modulator (DPWM). The DPWM outputs a pulse-width
modulated signal for regulating the duty ratio of the power stage. The flowchart in Figure
3.3 illustrates the procedure performed by each plug-and-play controller, from start up until
regular operation.
Figure 3.3: Flowchart showing the general operation of each plug-and-play controller
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CHAPTER 3: SYSTEM DESCRIPTION 19
3.2 System Benefits
The system described in 3.1 provides several advantages compared to existing solutions. The
architecture is scalable, supporting both single phase and multiphase configurations.
Consequently, the controller can be used in a wide variety of applications and can support
future adjustments in the number of phases.
The architecture achieves the advantages of existing systems described in 2.4, and the
masterless control procedure allows scalability in a more cost effective manner. The silicon
area required for the controllers is always proportional to the number of phases. Since the
number of pins required per phase is fixed and no central controller is required, the system
can be used as a cost effective solution for supplying a functional block of a miniature battery
powered device in a single phase configuration. The design can also be used for a
multiphase setup, allowing for a high current rating, reduced ripple, improved dynamic
response, and superior heat distribution.
To further minimize the pin count, the gate drivers of power MOSFET switches could be
integrated directly with each phases controller. This would not be feasible in a system with
a centralized controller that supports many phases as the required area would be too large.
The gate drivers and power MOSFETs for each phase usually need to be on separate chips
due to heat distribution requirements. If the digital controller of the proposed system could
be integrated with each gate driver and MOSFET, the cost would be minimized if the area
required for the controller is small in comparison to the gate driver and MOSFET.
Furthermore, if a smaller CMOS technology is used for the digital controller, the space
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CHAPTER 3: SYSTEM DESCRIPTION 20
required is reduced in proportion to the technology. However, the area requirements for the
gate driver of MOSFET will remain relatively constant, since these devices must to sized to
meet the current requirements.
With a plug-and-play scalable system, higher efficiency can be achieved since the number of
phases can be adjusted according to the load requirements. Switch-mode power supplies can
achieve very high efficiencies, but the peak efficiency occurs only for a certain range of loads
for a given configuration. With a scalable design, the number of phases can be configured to
ensure that a high efficiency is achieved for the specified load, even if the load varies from
application to application or over time.
3.3 Component Descriptions
3.3.1 Communication Block
The Communication Block of Figure 3.4, present in each phases controller, receives and
transmits data among the phases. The Communication Block is necessary for both the start-
up configuration procedure as well as the regular operation of the system. It operates in two
modes: bus mode and series mode. In bus mode, the communication lines of all phases are
connected to each other. When one phase transmits data, the transmission is read by all other
phases. In series mode, on the other hand, the communication lines are not all connected to
each other. For a system with n phases, there are n communication lines, where each phases
communication line is connected only to the next phase in the ring. As a result, a
transmission from one phase can only be read by the very next phase in the ring. For
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CHAPTER 3: SYSTEM DESCRIPTION 21
example, if the phases are arranged as in Figure 3.1, a transmission from Phase 1 is only seen
by Phase 2 , a transmission from Phase 2 is only seen by Phase 3 , and so on.
Figure 3.4: Communication block diagram
Different communication modes are used at different steps of operation. During the phase
detection stage, series mode is employed to count the phases. During the remaining stages,
bus mode is enabled to allow information to be shared among all the phases. Communication
is performed using a single line in bus mode. This type of protocol has been selected in order to minimize the pin count. Each controller only requires two pins for communication, no
matter how many phases are present. An alternative parallel communication protocol would
require more pins. Also, if bus mode were not available, each controller would need to be
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CHAPTER 3: SYSTEM DESCRIPTION 22
directly connected to all other controllers, meaning that the pin requirements would grow
significantly with the number of phases. Furthermore, a plug-and-play controller supporting
a large number of phases would have many unused pins in applications with one or only a
few phases.
The communication line of each controller is connected to a pull-up network, meaning that it
is connected to VDD through a resistor. When the communication block is not transmitting,
it outputs a weak high signal or a high-impedance (Z). If no other phase is transmitting, the
output will remain in a high-impedance state. On the other hand, if another phase transmits
onto that node, the value is pulled to either a strong low (0) or a strong high (1).
The details of the Communication Block are shown in Figure 3.4. It consists of three main
components: a transmitter, a receiver, and a transmission gate. The communication protocol
is described in the following section, followed by explanations of each of the components.
3.3.1.1 Communication Protocol
A single-wire communication protocol has been used in order to minimize the pin count of
the controllers. With this protocol, only two pins on each controller are required for
communication, regardless of the number of phases present. The communication block uses
a serial timing-based protocol to transmit and receive data. Serial single-wire
communication protocols, such as [20], have been proven to be efficient, reliable choices.
The number of bits has been selected based on the minimum amount required to transmit
most packets of information. In this application, only four bits of data are required for
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CHAPTER 3: SYSTEM DESCRIPTION 23
transmitting most of the necessary information, such as the phase count and the ADC error
value. For the few cases where more than four bits are required, multiple transmissions are
performed.
Each phase is responsible for either transmitting or receiving data, depending on the stage of
operation. At the beginning of a transmission, the transmitting phase pulls its
comm_out_internal port low (see Figure 3.4). The receiving phase or phases observe this
transition and prepare to receive the data. After a certain delay, the transmitting phase
outputs the value of the first bit of data. This value is held, and after another short period of
time, the transmitting phase outputs the value of the second bit, and so on. Shortly after the
fourth bit is sent, the transmitting phase releases the output into a high-impedance state, and
the transmission is complete. Meanwhile, the receiving phase or phases sample the output at
specific times to read the data, one bit at a time.
A data transmission is shown in Figure 3.5. In this example, the transmitting phase sends a
value of 4b1010 (an arbitrary value in this example). The receiving phase or phases sample
their respective comm_in ports at the appropriate times, based on the clock signals, to read
the value of the transmission. The signal names correspond to the ports found in Figure 3.4.
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CHAPTER 3: SYSTEM DESCRIPTION 24
Figure 3.5: Example of a data transmission of the value 4b1010
3.3.1.2 Transmitter and Receiver
As described in the previous section, the transmitter uses a timing-based protocol to send 4
bits of data at a time. Both the transmitter and receiver use a series of delay cells to produce
clock signals indicating when the data should be changed to the next bit value (in the case of
the transmitter) and when the communication line should be sampled (in the case of the
receiver). These delay cells are illustrated in Figure 3.4. The first cell of the transmitter has
half the delay of the first delay cell of the receiver. The purpose of this is so that the delay of
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CHAPTER 3: SYSTEM DESCRIPTION 25
the receiver lags behind the transmitter, so that the sampling can occur at approximately the
midway point of each bit.
The example of Figure 3.5 demonstrates how the receivers clock lags behind the
transmitters clock. This mitigates any issues related to metastability and delay variations
between chips. If the communication line were sampled by the receiver at approximately the
same time as the transmitter changes the value, this could lead to metastability problems,
where the register outputs to not settle within the expected time and possibly record incorrect
values. Also, process variations may lead to slightly different delays among different phases.
Sampling at the midpoint allows for a margin of error in the delay. The transmissions have
been limited to only 4 bits at a time to allow for a large margin of error. If a large number of
bits where sent during each transmission, an error in delay time could accumulate after each
sampling point, eventually resulting in an incorrect reading.
If a very large number of phases were needed, further efforts could be put in place to improve
the robustness of the communication. First, the line could be oversampled to compensate for
mismatches in delay. Secondly, programmable delay cells could be used for producing the
clock signals. The cells could be dynamically adjusted such that their delays match those of
other phases.
The receiver indicates when it begins and finishes receiving data through the signals RXStart
and RXEnd . This serves two purposes. Firstly, the RXEnd signal indicates when the
controller may read RXData , the data received during the transmission. Secondly, these
signals are used for timing purposes. During regular operation of the system, these signals
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CHAPTER 3: SYSTEM DESCRIPTION 26
are used to specify when each phase should begin its switching cycle. The timing of the
starting point of each phases switching cycle is vital for proper interleaved operation.
3.3.1.3 Transmission Gate
The transmission gate, shown in Figure 3.4, allows the communication block to operate in
two modes: bus mode and series mode. The purpose of the transmission gate is to function
as an ideal switch, linking the communication input and output ports. When the mode is set
to series mode, comm_in for a given phase depends only on the comm_out signal from the
previous phase in the ring. For the example in Figure 3.1, this means that during series
mode, the output of Phase 1 is only seen by Phase 2 . Similarly, the comm_in signal of the
next phase in the ring depends only on the comm_out signal of the given phase. When bus
mode is active, comm_in is shorted to comm_out in all phases. This allows data sent from
any phase to be received by all the other phases in the ring. At any given time, all phases
operate in either bus mode or series mode. During transitions between series mode and bus
mode, the controllers do not transmit data for a certain period of time, to allow other phases
to complete their mode transitions. Table 3.1 summarizes all the possible scenarios for
different port values for each mode of operation. It shows the corresponding input and
output values for different values of comm_in , comm_out_internal , bus_mode , and
comm_out . A value of Z indicates high impedance and a value of X indicates an arbitrary
value. Cases which would require multiple phases to be transmitting data at the same time
are omitted, as this does not occur due to the design of the controllers.
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CHAPTER 3: SYSTEM DESCRIPTION 27
comm_in comm_out_internal bus_mode comm_out X Z 0 (series) ZZ 0 0 (series) 0Z 1 0 (series) 1Z Z 1 (bus) Z
0 0 1 (bus) 01 1 1 (bus) 1
Table 3.1: Communication block inputs and outputs
The transmission gate is made up of two transistors in parallel: one NMOS transistor and one
PMOS transistor. In series mode, the bus_mode signal is set such that both transistors are in
their off states. When comm_in is driven to a certain value, it will have no effect on
comm_out , and vice-versa. On the other hand, in bus mode, the bus_mode signal is set to
turn on both transistors. In this case when comm_in is driven to a certain value, comm_out
will be driven to that value, and vice-versa. This occurs because these ports behave as if they
are shorted together during bus mode, which is the desired behaviour. In bus mode, a logic
value of 1 is sent to the gate of the NMOS transistor and a logic value of 0 is sent to the gate
of the PMOS transistor. The controllers have been designed such that multiple phases will
never attempt to transmit data simultaneously. As a result, during bus mode, there is no
concern with two phases fighting with each other to pull the bus to opposite strong values. In
bus mode, the transmission gate is capable of relaying high, low, and high-impedance
signals. Since PMOS transistors pass high values well but low values poorly, and NMOS
transistors pass high values poorly but low values well, a parallel combination of both is
used.
A tri-state buffer would not be an appropriate choice for replacing the transmission gate
because it is not capable of passing a high impedance signal. A tri-state buffer can output a
high impedance signal based on its control signal, but not based solely on its input signal.
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CHAPTER 3: SYSTEM DESCRIPTION 28
Figure 3.6 compares series mode and bus mode operation. In this example there are four
phases, and thus four nodes (one node between phases 1 and 2, another between phases 2 and
3, and so on). In series mode, the transmission gate is turned off and signals do not pass from
one side to the other. In the example, Phase 1 sends a transmission, and Phase 2 , the very
next phase in the ring, is the only phase that receives the transmission. In bus mode, the
transmission gates are turned on and the phases behave as if comm_in is shorted to comm_out
in each phase. In this case when Phase 1 transmits data, all other phases in the system
receive the transmission.
Figure 3.6: A comparison of series mode and bus mode with four phases
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CHAPTER 3: SYSTEM DESCRIPTION 29
3.3.2 Phase Detector
The Phase Detector , present in each phases controller, is responsible for determining the
number of phases in the system. For multiphase operation, knowledge about the number of
phases is necessary for the timing required for interleaved operation, and to ensure that
proper communication occurs. The controller must also be capable of establishing whether
single phase operation should occur, if only one phase is present. The phase detection step is
the first process of the initialization procedure, occurring shortly after start-up.
During start-up, one of the phases is uniquely identified as the starting phase. The starting
phase is responsible for initializing the phase detection process. The other phases then
perform their respective tasks and the number of phases is determined.
3.3.2.1 Phase Detection Process
At the beginning of the phase detection process, the communication mode of all phases is set
to series mode. This is done so that each phase in the system can be uniquely counted, one
phase at a time. The phase detection process begins when the starting phase (identified using
one of the methods proposed in 3.3.2.2) transmits a value of 1 to the next phase in the ring.
Since series mode is used for communication at this point, only the next phase in the ring
receives this value. The next phase receives a value of 1, stores it in a register, increments it
to 2 and transmits this new value to the following phase. This process continues until the
starting phase receives a transmission from the final phase in the ring. The value received by
the starting phase corresponds to the total number of phases present in the system. After a
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CHAPTER 3: SYSTEM DESCRIPTION 30
sufficient period of time, all phases switch the communication method into bus mode and the
initial phase transmits the number of phases across the bus. At this point, each phase reads
the number of phases and has previously recorded its own unique position in the ring. The
next segment in the initialization procedure, the LC Estimation and Sequencing step, may
now begin.
Note that the limitation of the communication block sending 4 bits of data during each
transmission restricts multiphase operation to 2 4 1 = 15 phases. However, the controllers
could be designed such that the Phase Detector sends and receives two or more transmissions
at each step, supporting a much greater number of phases. For example, with two data
transmissions, the maximum number of phases would be 2 8 1 = 255 (although practical
considerations, such as the physical area required for the power stages, would likely limit the
number of phases to a number far less than 255).
An example of the phase detection process is shown in Figure 3.7, for the case with four
phases. For the case where there is only one phase, that phases comm_in port is directly
connected to its own comm_out port. In this case, the phase will transmit a value of 1 and
will immediately receive this transmission through its comm_in port, indicating that no other
phases are present in the system. With only one phase the LC Estimation and Sequencing
and Digitally-Controlled DLL steps are unnecessary and therefore omitted. Regular
operation begins immediately after the Phase Detector recognizes that only a single phase is
present.
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CHAPTER 3: SYSTEM DESCRIPTION 31
Figure 3.7: The phase detection process with four phases
3.3.2.2 Starting Phase Identification
A major challenge with this design is to ensure that exactly one phase begins the phase
counting procedure during start-up. If no phases begin the process, the system will fail to
start. On the other hand, if more than one phase begins, erroneous operation can occur. This
problem stems from the fact that all controllers are identical and are therefore expected to
behave in the exact same way. A solution is necessary that uniquely identifies one phase,
and only one phase, as the starting phase. One possible solution is to program one of the
phases as the starting phase. However, the process of programming all chips will result in an
increase in cost and extra pins may be required. Another solution would be to provide
unique master and slave controllers. In this case, each application would require one master
controller and as many slave controllers as necessary. However, this would require the
design of two distinct controllers. Also, the system would not be able to continue to operate
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CHAPTER 3: SYSTEM DESCRIPTION 32
if the master chip were to fail. These drawbacks may be unacceptable for high volume
applications. Another approach is to rely on random behaviour to select one phase as the
initial phase. However, random behaviour may not be a desirable solution since there may
be a risk of a conflict, where two phases select themselves as the initial phase. These
conflicts must either be avoided or handled appropriately, which presents a further challenge.
Two solutions which address these issues are proposed.
The first solution is illustrated in Figure 3.8. The controllers and power stages are connected
and routed on a printed circuit board (PCB). One of the phases has its comm_in pin
connected to the output of a tri-state buffer. The tri-state buffer is enabled only when reset is
active. When the reset signal is activated, each phase immediately reads the value of its
comm_in port. The one phase that sees its comm_in port pulled low at the instant that reset is
activated will designate itself as the starting phase. Since only one phase has its comm_in
port connected to the reset signal as a result of the PCB layout, only that one phase will
designate itself as the starting phase. This allows the initial phase to be uniquely identified in
a simple fashion, based on its arrangement on the PCB. This method does not rely on
random behaviour or programmability, yet the goal of using identical controllers is achieved.
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CHAPTER 3: SYSTEM DESCRIPTION 33
Figure 3.8: PCB routing for starting phase identification
An alternative solution is presented in Figure 3.9. In this case, the reset signal is connected
through a RC filter to one phase, and directly connected to the other phases. When the reset
signal is activated, the signal change propagates almost immediately to the phases with direct
connections to reset. However, for the phase connected to reset through the RC filter, the
signal change is delayed due to the time required to discharge the capacitance.
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CHAPTER 3: SYSTEM DESCRIPTION 34
Figure 3.9: PCB routing for starting phase detection using a RC filter
As soon as a phase receives a reset signal, it checks whether its comm_in port has been pulled
low. If so, it designates itself as the starting phase. Otherwise, it is not the starting phase and
pulls its comm_out port low. In the example in Figure 3.9, the reset signal for the initial
phase ( Phase 1 ) passes through a RC filter, causing a delay. The reset signal immediately
passes to the other phases, which pull down their respective comm_out ports. As a result, by
the time the reset signal reaches Phase 1 , Phase 4 has already received the reset signal and
has pulled its comm_out port low. Phase 1 sees that its comm_in port (connected to the
comm_out port of Phase 4 ) has been pulled low and designates itself as the initial phase. An
example of waveforms for the reset procedure is shown in Figure 3.10 for a case with 4
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CHAPTER 3: SYSTEM DESCRIPTION 35
phases. In this case Phase 1 is the starting phase. The RC filter produces a delay of t d in the
reset signal, causing Phase 1 to sample comm_out 4 after it has been pulled down.
Figure 3.10: Starting phase detection done with an RC filter
Either of these methods results in one phase being uniquely identified as the starting phase.
In both cases, the controllers of all phases are identical, but one phase has a slightly different
arrangement on the PCB. The advantage of the first method is that an RC filter is not
required, although it requires an external tri-state buffer. The tri-state buffer method would
be suitable for cases where external digital hardware already exists, such as in cases where a
supervising FPGA or microprocessor is employed. In cases where no digital hardware exists,
the simplicity of an RC filter would be advantageous.
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CHAPTER 3: SYSTEM DESCRIPTION 36
3.3.3 LC Estimator and Sequencer
One of the primary advantages of multiphase operation in switch-mode power supplies is
ripple cancelation. In order to achieve this advantage, the phases must be interleaved,
meaning that the starting positions of the switching signals are evenly spaced over the course
of each switching cycle. By interleaving the phases, the rising slope of one inductors
current can coincide with the falling slope of another inductors current, thus reducing the
total ripple. However, variances in the inductance values among the phases can greatly
mitigate the effects of ripple cancelation, due to differences in the current slope. Due to non-
idealities in production, an inductance may vary from its nominal value [21]. The work
presented in [19] introduces a method of measuring the inductor current ripple in each
individual phase during start-up, and re-ordering the phases in such a way that the ripple is
minimized even in the presence of inductor non-idealities. The idea is to re-order the phases
such that phases with similar current ripples are switched 180 apart from each other. In this
way, similar variances in ripple between pairs of phases can cancel each other out, which
results in a reduction in total current ripple.
Reducing the output ripple in this manner introduces two requirements: the controller must
be able to place phases into an arbitrary sequence and it must be able to estimate and
compare the values of the inductors in all phases. The design of the Communication Block
allows the phases to be sequenced in any order because bus mode is employed after the phase
detection process is complete. During bus mode, the arrangement of the phases on the PCB
is no longer relevant and, as a result, the phases can be sequenced in any order. The
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CHAPTER 3: SYSTEM DESCRIPTION 37
introduction of the LC Estimator and Sequencer allows the inductances to be estimated and
the phases to be placed in an arrangement that mitigates the total output ripple.
3.3.3.1 Charged-Based Inductance Estimation Method
The method presented in [19] allows the inductances of all phases in a multiphase converter
to be estimated. The method employs current sensors to measure the steady-state current
ripple contribution of each of the phases. The steady-state peak-to-peak current ripple
contribution from one phase can be found to be the following, using a low voltage ripple
approximation [22]:
Equation 1The steady-state peak-to-peak current ripple is defined as the difference between the
maximum and minimum values of a current waveform over the course of a switching period
during steady-state operation, when the input voltage source and output load have remained
constant for a sufficient period of time. Equation 1 indicates that the peak-to-peak current
ripple contribution of a phase is inversely proportional to its inductance. The method of [19]
measures the current ripple of each phase directly using current sensors during a start-up
procedure and places phases with similar inductance values 180 apart from each other. The
specification that is most important is the peak-to-peak output voltage ripple. However, the
voltage ripple directly depends on the current ripple, since the current ripple from the
inductors flows into the output capacitor, causing a proportional fluctuation in output voltage.
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CHAPTER 3: SYSTEM DESCRIPTION 38
The size of the total output current ripple directly depends on the following conditions: the
number of phases, the inductance of each phase, the duty ratio, and the order of the phases.
Uneven current sharing among phases in a multiphase system does not affect the ripple. The
phase shift of each current waveform also affects the total current ripple, however, for this
analysis it is assumed that the phases are evenly shifted over the course of a switching cycle
(with n phases the phase shift is equal to 360/ n). Uniform phase shifting is achieved with
the Digitally-Controlled DLL , described in 3.3.4.
Of the parameters that affect the total output current ripple, the order of the phases is the one
which is most feasible to vary. It would be possible to alter the ripple by varying the duty
ratio; however, the duty ratio is set by the compensator in order to achieve the desired output
voltage. The number of phases is selected for various reasons including cost and dc current
requirements. The inductances of all phases may not be equal due to manufacturing
dissimilarities, temperature, and aging. On the other hand, the design of the dual-mode
Communication Block allows the phases in a multiphase setup to be placed into any
sequence, thus making it feasible to vary the phase order dynamically.
An example showing the current ripple of a system with 6 phases is found in Figure 3.11. In
this case, all phases have the same inductance, and hence have identical steady-state current
ripples (1.0 A). The total or combined current ripple is the sum of the instantaneous
individual ripples since the inductors are connected in parallel. The ripples of all phases
nearly cancel each other out, resulting in a combined total ripple of only 0.33 A. This
demonstrates how multiphase operation can result in reduced output ripple. Figure 3.12, on
the other hand illustrates the case where 2 phases have different inductances than the other 4
phases. These 2 phases have smaller inductances, resulting in a larger phase current ripple of
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CHAPTER 3: SYSTEM DESCRIPTION 39
2.0 A, compared to 1.0 A in the other phases. When these phases are placed adjacent to each
other in the switching sequence, a total current ripple of 3.22 A occurs. In Figure 3.13, the
phases have the same inductances and current ripples as in the case of Figure 3.12. However,
the 2 phases with smaller inductances have been placed 180 apart from each other in the
switching sequence. This results in a large reduction in total current ripple; the total current
ripple is now only 1.00 A. This illustrates how reordering the phases can result in a
significant improvement in the output ripple. Note that other factors also affect the size and
shape of the output ripple. For example, when the product of the duty ratio and the number
of phases is an integer and the inductances are equal, the ripple is completely eliminatedthrough cancellations.
Figure 3.11: Ripple cancelation for a 6-phase system with identical inductances
0 0.5 1 1.5 2
x 10-6
-2
0
2
A m p
l i t u
d e
[ A ]
Time [s]
Individual Phase Waveforms
Phases with 1.0 A ripple
0 0.5 1 1.5 2
x 10-6
-2
0
2
A m p
l i t u
d e
[ A ]
Time [s]
Waveform Sum
Total current ripple: 0.33 A
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CHAPTER 3: SYSTEM DESCRIPTION 40
Figure 3.12: Combined ripple for a 6-phase system where 2 consecutive phases have similar inductance values,mismatched with the other phases
Figure 3.13: Ripple cancelation in a 6-phase system with optimized phase sequencing
0 0.5 1 1.5 2
x 10-6
-2
0
2
A m p
l i t u
d e
[ A ]
Time [s]
Individual Phase Waveforms
Phases with 1.0 A ripplePhases with 2.0 A ripple
0 0.5 1 1.5 2
x 10-6
-2
0
2
A m p
l i t u
d e
[ A ]
Time [s]
Waveform Sum
Total current ripple: 3.22 A
0 0.5 1 1.5 2
x 10-6
-2
0
2
A m p
l i t u
d e
[ A ]
Time [s]
Individual Phase Waveforms
Phases with 1.0 A ripplePhases with 2.0 A ripple
0 0.5 1 1.5 2
x 10-6
-2
0
2
A m p
l i t u
d e
[ A ]
Time [s]
Waveform Sum
Total current ripple: 1.00 A
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CHAPTER 3: SYSTEM DESCRIPTION 41
3.3.3.2 LC Estimator and Sequencer Architecture
The proposed method for mitigating the systems output ripple involves estimating the
inductance of each phase and subsequently reordering the phases to achieve a reduced ripple.
An algorithm for reordering phases similar to the one presented in [19] is employed here.
However, the method for estimating the inductance in each phase has been modified to work
without current sensors. The process involves each phase charging and discharging the
output capacitance before regular operation begins. During this process the charge times of
the phases are recorded and compared.
The load should not be connected during the LC product estimation process because the
output voltage is lower than the rated value. As a result, this process works under the
assumption that a Power-Good signal is present. This feature is quite common in many
practical applications, such as CPUs. For example, [2,23] employ a Power-Good signal.
During initialization, the phases each take turns independently charging the output capacitor,
while the switching signals of the other phases are disabled and the load is disconnected.
The phase that is currently active switches at a low duty ratio value and charges the output to
a value well below the rated value. This is accomplished by setting the switch S 2 such that
the ADC reference is set to V ref 1, which is lower than the steady-state output voltage, V ref 2, as
shown in Figure 3.2. A low duty ratio is used to avoid a large inrush current that could
potentially damage the power stage components. Once the specified output voltage is
reached, the output capacitor is discharged until no energy remains in the inductor and
capacitor. The time taken to charge the output capacitor to the specified value is measured,
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CHAPTER 3: SYSTEM DESCRIPTION 42
and transmitted to the other phases, using the communication bus. The remaining phases
repeat this process one at a time, such that in the end, the charge times of all phases are
known. The phases perform this task in the order they were counted during the phase
detection process. Consequently, all phases implicitly know when they should begin the
process.
The corner frequency of the power stage of a single phase buck converter is defined as
follows:
Equation 2
This frequency determines the system response speed of each phase operating individually.
For a given capacitance, a larger inductance will result in a larger charge time. In a
multiphase converter where only one phase is active, the corner frequency can be defined as
the following:
Equation 3
In this case, Li is the inductance of phase i. The output capacitance is shared and therefore
the same for all phases. For a fixed capacitance, the charge time depends only on the
inductance. As a result, a phase with a large inductance will result in a long charge time, and
this corresponds to a small steady-state current ripple contribution for that phase.
The LC estimation process is illustrated in Figure 3.14. Before beginning the LC Estimation
and Sequencing step, all controllers switch into bus mode to allow information to be shared
among all phases. Switch S 2 in each phase is set such that the ADC reference is set to V ref 1,
which is below the rated output voltage reference, V ref 2, as illustrated in Figure 3.2. The
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CHAPTER 3: SYSTEM DESCRIPTION 43
starting phase begins the procedure by switching at a fixed duty ratio in open-loop while the
other phases wait. As soon as an output voltage of V ref 1 is reached, the starting phase stops
and discharges the output. The time taken to charge the output, in units of switching periods,
is recorded. The initial phase transmits this charge time to all other phases in the system, and
the other phases store the value in registers. Since only 4 bits of data are sent during each
transmission, multiple data transmissions are used in case the charge time may exceed 2 4
switching cycles. At this point the second phase repeats this process, and so on. When all
phases have finished, each phase has knowledge of its own charge time and the charge times
of all other phases. These charge times are now used to order the phases, minimizing thetotal ripple.
Figure 3.14: The charging and discharging process for estimating the LC products
The phases each independently determine their order in the switching cycle. A flowchart of
the algorithm is shown in Figure 3.15. Each phase compares its own charge time to those of
the other phases, and counts the number of phases with small charge times, or larger
estimated inductances. To avoid a conflict arising from multiple phases having identical
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CHAPTER 3: SYSTEM DESCRIPTION 44
estimated inductances, the ring order of each phase, found during the Phase Detection
process, is appended onto the charge times. This avoids the problem where multiple phases
place themselves in the same location of the switching sequence, which would lead to poor
interleaving, contradicting the purpose of the phase sequencing procedure. Each phase takes
the binary value corresponding to the number of phases with larger estimated inductances
appended with its ring order, and performs a circular bit shift on this value. The result of this
operation is a number ranging from 0 to ( n 1), where n is the number of phases in the
system. This number corresponds to each phases order in the switching sequence. This has
the effect of placing phases with similar estimated inductance values 180 apart from eachother in the switching sequence. Note that if the number of phases is odd, two phases cannot
be placed 180 apart from each other; however, they will be placed approximately 180 apart.
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CHAPTER 3: SYSTEM DESCRIPTION 45
Figure 3.15: Flowchart of the phase sequencing algorithm
Table 3.2 provides an example of phase reordering based on measured charge times. In this
example the first 2 phases in the ring have charge times of 10 switching cycles, the third
phase has a charge time of 5 cycles and the fourth phase has a charge time of 6 cycles.
Therefore, the first two phases have inductances that are larger than those of the last two
phases. Each phase counts the number of phases with smaller charge times compared to its
own charge time. In this example the first two phases would place themselves into the same
order. To resolve this issue, the charge times are appended with each phases position in the
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CHAPTER 3: SYSTEM DESCRIPTION 46
ring (found during the Phase Detection process), and these values are used during the
comparisons. The charge time appended with the ring position is unique for all phases since
the ring positions are unique and, as a result, the resulting phase orders are unique. Each
phase then performs a circular bit shift operation on this value to determine its switching
sequence order. The circular bit shift operation was chosen because its digital hardware
implementation is very simple. This has the effect of placing phases with similar values
calculated in column 4 of
Table 3.2 opposite each other in the switching sequence. The result of this operation will be
unique for each phase and the values will range from 0 to ( n 1). This operation also works properly with an odd number of phases; unique phase orders ranging from 0 to ( n 1) will
still be produced in these cases. Once the LC Estimation and Sequencing procedure is
complete, the Digitally-Controlled DLL step begins.
1. Phase ID 2. Charge Time
3. ChargeTime
Appendedwith
Phase ID
4. Number of Phases with
Smaller ChargeTimes
5. Switching
Sequence Order
Decimal Binary Decimal Binary Binary Decimal Binary Decimal Binary0 00 10 1010 1010-00 2 10 1 011 01 10 1010 1010-01 3 11 3 112 10 5 0101 0101-10 0 00 0 003 11 6 0110 0110-11 1 01 2 10
Table 3.2: An example of phase reordering based on charge times with 4 phases.
3.3.4 Digitally-Controlled DLL
The Digitally-Controlled DLL is used for timing the switching signals of the phases for
interleaved operation. In the proposed design, one of the phases is selected as the Timing
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CHAPTER 3: SYSTEM DESCRIPTION 47
Phase . This phase is responsible for dictating the timing of the beginning of the switching
cycles of all other phases, such that the switching pulses of all phases are evenly spaced.
3.3.4.1 Selection of the Timing Phase
The timing operations for interleaved operation are centralized in one of the phases in order
to ensure that the switching signals are evenly spaced. If the timing procedure were to be
distributed among all phases, there could be small discrepancies in timing due to process
variation among the controllers. In other words, the switching signals would not necessarily
be evenly spaced over the course of a switching period. Although this would still result in
approximate ripple cancelation, undesirable harmonic noise could be produced.
Another advantage of using only one phase for timing is that an external reference clock is
not required. This reduces the pin requirements of the controllers. The only requirement is
an internally generated clock signal with a frequency equal to the desired switching
frequency.
In the proposed design, all controllers are identical and they are therefore all capable of
producing the timing signals necessary for interleaved operation. The selection of the Timing
Phase could be arbitrary; it does not matter which phase is selected as long as exactly one
phase is designated as the Timing Phase . In the proposed design, the first phase in the
switching sequence is selected.
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CHAPTER 3: SYSTEM DESCRIPTION 48
3.3.4.2 Clock Generation Architecture
The purpose of the Digitally-Controlled DLL is to produce a clock signal with a frequency of
nf s for a system having n phases and a switching frequency of f s. A clock with a frequency of
nf s is required to evenly space the switching signals of all phases for interleaved operation.
Since the plug-and-play controllers are designed to function with an arbitrary number of
phases, the Digitally-Controlled DLL must be capable of producing clock signals of different
frequencies.
Table 3.3 lists the required output clock frequencies and periods of the Digitally-Controlled
DLL for a system operating at a switching frequency of 1 MHz (corresponding to a switching
period of 1s) with different quantities of phases.
n (number of phases) nf s (output frequency)[MHz] 1/( nf s) (output period) [ns]2 2 500.003 3 333.334 4 250.005 5 200.006 6 166.677 7 142.868 8 125.009 9 111.11
10 10 100.00
Table 3.3: Required output frequencies and periods for a system operating at a switching frequency of 1 MHzfor various phase counts
The Digitally-Controlled DLL , shown in Figure 3.16, has two main components: a
Programmable Ring Oscillator and a Digital Frequency Compensator . The Digital
Frequency Compensator adjusts the inputs to the Programmable Ring Oscillator such that
the desired output clock frequency is achieved. The inputs to this module are n, a digital
value corresponding to the number of phases, and a clock with a frequency of f s. the
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CHAPTER 3: SYSTEM DESCRIPTION 49
switching frequency. The outputs are a clock with a frequency of nf s and a signal indicating
when the correct output frequency has been achieved.
Figure 3.16: Digitally-Controlled DLL block diagram
The Programmable Ring Oscillator of Figure 3.16 consists of number of digitally
programmable delay cells arranged in a ring configuration and connected through 2-to-1
multiplexors. The delay cells are similar to the current-starved delay cells presented in [24].
A NAND-gate is also included in the ring for the inversion required to produce an oscillating
clock signal. The NAND-gate also allows the ring oscillator to be disabled, conserving
power when not needed. There are two methods of changing the output clock frequency: the
programmable delay cell control signals and the multiplexor inputs. Each programmable
delay cell has a digital control input that varies the propagation delay through the cell. The
multiplexors allow the number of programmable delay cells in the ring to be varied.
Depending on the multiplexor control signal, the previous delay cell can either be omitted or
included in the ring.
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CHAPTER 3: SYSTEM DESCRIPTION 50
The Digital Frequency Compensator is responsible for adjusting the delay cell and
multiplexor control signals in order to achieve the desired output clock frequency. The
module compares the frequency of the output to that of the input by measuring the number of
output clock cycles over the course of a large number of input clock cycles. Using this
feedback, it iteratively adjusts the Programmable Ring Oscillator control signals to produce
an output clock with a frequency as close as possible to nf s. Although the controller cannot
lock to a frequency of exactly nf s due to the quantization of the control signals, it behaves in a
similar fashion to a standard analog delay-locked loop. However, its control is performed in
a completely digital fashion.
A flowchart presenting the operation of the Digital Frequency Compensator is shown in
Figure 3.17. The delay cell and multiplexor control signals are first set to a starting value.
Next, a counter is enabled that counts the number of cycles of the output clock, clk_out .
Simultaneously, a counter is enabled that counts the number of cycles of the input clock,
which has a frequency of f s. After a period of M input clock cycles, the counters are disabled
and there outputs are compared. If the output clock counter is greater than nM , where n is the
number of phases, the ring oscillator is too fast. In this case, the control signals are adjusted
such that the delay of the ring oscillator is increased. The counting process repeats itself
until the output clock counter is less than nM . The reverse occurs for the latter case. In this
way, the control signals are adjusted in an iterative manner until an output frequency close to
the desired value is achieved. At this point, the Locked output of the Digitally-Controlled
DLL is raised and regular operation of the system may now begin.
The range and resolution of the Digitally-Controlled DLL depend on a number of factors. A
larger number of multiplexors and Programmable Delay Cells with shorter delays will result
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CHAPTER 3: SYSTEM DESCRIPTION 51
in a wider range of possible output frequencies. Also, adjusting the number of control
signals for the Programmable Delay Cells can increase the delay resolution and therefore can
allow the output frequency to be more closely matched to a frequency of nf s. It should be
noted that changing the specifications can result in different chip area and power
requirements, so a reasonable compromise should be chosen. Also, the Digitally-Controlled
DLL only needs to be capable of generating frequencies larger than 2 f s since the input clock
is used for timing with a single phase.
In the prototype design, the Digitally-Controlled DLL begins locking the output clock signal
only after the LC Product Estimation and Sequencing step is complete. However, in order to
reduce the time required for the initialization process, the Digitally-Controlled DLL could be
activated simultaneously with the LC Product Estimation and Sequencing block, directly
after the Phase Detection process is complete (the correct frequency can only be produced
once the number of phases is known).
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